diff options
| author | Borislav Petkov <bp@suse.de> | 2015-06-10 10:09:36 -0400 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2015-06-24 12:17:34 -0400 |
| commit | f2f3dca1b7a66cbc91f45b59b8606bb325fa869f (patch) | |
| tree | e88563f9e8a7298201007db8b239c5d251d2980c /drivers/edac/mce_amd_inj.c | |
| parent | 6f2b6422d4787ffa72bd81abdc1b503dbf87a49a (diff) | |
EDAC, mce_amd_inj: Cleanup and simplify README
Save us an indentation level, widen to 80 cols, make the text more
succinct and slender. Use i as the bank variable, same as what the
documentation uses.
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/mce_amd_inj.c')
| -rw-r--r-- | drivers/edac/mce_amd_inj.c | 66 |
1 files changed, 35 insertions, 31 deletions
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c index eb8356e2df3e..bfb0f350cb0e 100644 --- a/drivers/edac/mce_amd_inj.c +++ b/drivers/edac/mce_amd_inj.c | |||
| @@ -253,37 +253,41 @@ MCE_INJECT_GET(bank); | |||
| 253 | DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); | 253 | DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); |
| 254 | 254 | ||
| 255 | static const char readme_msg[] = | 255 | static const char readme_msg[] = |
| 256 | "\nDescription of the files and their usages:\n\n" | 256 | "Description of the files and their usages:\n" |
| 257 | "status: Set a value to be programmed into MCx_STATUS(bank)\n" | 257 | "\n" |
| 258 | "\t The status bits provide insight into the type of\n" | 258 | "Note1: i refers to the bank number below.\n" |
| 259 | "\t error that caused the MCE.\n\n" | 259 | "Note2: See respective BKDGs for the exact bit definitions of the files below\n" |
| 260 | "misc: Set value of MCx_MISC(bank)\n" | 260 | "as they mirror the hardware registers.\n" |
| 261 | "\t misc register provides auxiliary info about the error. This\n" | 261 | "\n" |
| 262 | "\t register is typically used for error thresholding purpose and\n" | 262 | "status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n" |
| 263 | "\t validity of the register is indicated by MCx_STATUS[MiscV]\n\n" | 263 | "\t attributes of the error which caused the MCE.\n" |
| 264 | "addr: Error address value to be written to MCx_ADDR(bank)\n" | 264 | "\n" |
| 265 | "\t This register is used to log address information associated\n" | 265 | "misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n" |
| 266 | "\t with the error.\n\n" | 266 | "\t used for error thresholding purposes and its validity is indicated by\n" |
| 267 | "Note: See respective BKDGs for the exact bit definitions of the\n" | 267 | "\t MCi_STATUS[MiscV].\n" |
| 268 | "\t above registers as they mirror the MCi_[STATUS | MISC | ADDR]\n" | 268 | "\n" |
| 269 | "\t hardware registers.\n\n" | 269 | "addr:\t Error address value to be written to MCi_ADDR. Log address information\n" |
| 270 | "bank: Specify the bank you want to inject the error into.\n" | 270 | "\t associated with the error.\n" |
| 271 | "\t The number of banks in a processor varies and is family/model\n" | 271 | "\n" |
| 272 | "\t dependent. So, a sanity check performed while writing.\n" | 272 | "cpu:\t The CPU to inject the error on.\n" |
| 273 | "\t Writing to this file will trigger a #MC or APIC interrupts or\n" | 273 | "\n" |
| 274 | "\t invoke the error decoder routines for AMD processors. The value\n" | 274 | "bank:\t Specify the bank you want to inject the error into: the number of\n" |
| 275 | "\t in 'flags' file decides which of above actions is triggered.\n\n" | 275 | "\t banks in a processor varies and is family/model-specific, therefore, the\n" |
| 276 | "flags: Write to this file to speficy the error injection policy.\n" | 276 | "\t supplied value is sanity-checked. Setting the bank value also triggers the\n" |
| 277 | "\t Allowed values:\n" | 277 | "\t injection.\n" |
| 278 | "\t\t\"sw\" - SW error injection, Only calls error decoder\n" | 278 | "\n" |
| 279 | "\t\t\troutines to print error info in human readable format\n" | 279 | "flags:\t Injection type to be performed. Writing to this file will trigger a\n" |
| 280 | "\t\t\"hw\" - HW error injection, Forces a #MC,\n" | 280 | "\t real machine check, an APIC interrupt or invoke the error decoder routines\n" |
| 281 | "\t\t\tcauses exception handler to handle the error\n" | 281 | "\t for AMD processors.\n" |
| 282 | "\t\t\tif UC or poll handler catches it if CE\n" | 282 | "\n" |
| 283 | "\t\t\tWarning: Might cause system panic if MCx_STATUS[PCC]\n" | 283 | "\t Allowed error injection types:\n" |
| 284 | "\t\t\tis set. For debug purposes, consider setting\n" | 284 | "\t - \"sw\": Software error injection. Decode error to a human-readable \n" |
| 285 | "\t\t\t/<debugfs_mountpoint>/mce/fake_panic\n" | 285 | "\t format only. Safe to use.\n" |
| 286 | "cpu: The cpu to inject the error on.\n\n"; | 286 | "\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n" |
| 287 | "\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n" | ||
| 288 | "\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n" | ||
| 289 | "\t before injecting.\n" | ||
| 290 | "\n"; | ||
| 287 | 291 | ||
| 288 | static ssize_t | 292 | static ssize_t |
| 289 | inj_readme_read(struct file *filp, char __user *ubuf, | 293 | inj_readme_read(struct file *filp, char __user *ubuf, |