diff options
author | Vinod Koul <vinod.koul@intel.com> | 2013-09-02 08:12:35 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2013-09-02 08:12:35 -0400 |
commit | 265d9c673d47fcd5812d69dc07104b706285de56 (patch) | |
tree | ebb686a2ecbf702c4a5cab975cf86fbc10dac5e7 /drivers/dma | |
parent | 592745e2f8afbaeafcf72645f0a2b0285644e091 (diff) | |
parent | e5ffa401eacd0e74178e20ba932200fc9fe41c07 (diff) |
Merge branch 'topic/sh' into for-linus
Conflicts:
drivers/dma/sh/Kconfig
drivers/dma/sh/shdmac.c
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r-- | drivers/dma/sh/Kconfig | 4 | ||||
-rw-r--r-- | drivers/dma/sh/Makefile | 5 | ||||
-rw-r--r-- | drivers/dma/sh/shdma-arm.h | 51 | ||||
-rw-r--r-- | drivers/dma/sh/shdma-base.c | 26 | ||||
-rw-r--r-- | drivers/dma/sh/shdma-of.c | 3 | ||||
-rw-r--r-- | drivers/dma/sh/shdma-r8a73a4.c | 77 | ||||
-rw-r--r-- | drivers/dma/sh/shdma.h | 16 | ||||
-rw-r--r-- | drivers/dma/sh/shdmac.c (renamed from drivers/dma/sh/shdma.c) | 160 | ||||
-rw-r--r-- | drivers/dma/sh/sudmac.c | 8 |
9 files changed, 232 insertions, 118 deletions
diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig index e2b94d16f41f..dadd9e010c0b 100644 --- a/drivers/dma/sh/Kconfig +++ b/drivers/dma/sh/Kconfig | |||
@@ -28,3 +28,7 @@ config RCAR_HPB_DMAE | |||
28 | depends on SH_DMAE_BASE | 28 | depends on SH_DMAE_BASE |
29 | help | 29 | help |
30 | Enable support for the Renesas R-Car series DMA controllers. | 30 | Enable support for the Renesas R-Car series DMA controllers. |
31 | |||
32 | config SHDMA_R8A73A4 | ||
33 | def_bool y | ||
34 | depends on ARCH_R8A73A4 && SH_DMAE != n | ||
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile index ccf17cb5af10..e856af23b789 100644 --- a/drivers/dma/sh/Makefile +++ b/drivers/dma/sh/Makefile | |||
@@ -1,4 +1,9 @@ | |||
1 | obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o | 1 | obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o |
2 | obj-$(CONFIG_SH_DMAE) += shdma.o | 2 | obj-$(CONFIG_SH_DMAE) += shdma.o |
3 | shdma-y := shdmac.o | ||
4 | ifeq ($(CONFIG_OF),y) | ||
5 | shdma-$(CONFIG_SHDMA_R8A73A4) += shdma-r8a73a4.o | ||
6 | endif | ||
7 | shdma-objs := $(shdma-y) | ||
3 | obj-$(CONFIG_SUDMAC) += sudmac.o | 8 | obj-$(CONFIG_SUDMAC) += sudmac.o |
4 | obj-$(CONFIG_RCAR_HPB_DMAE) += rcar-hpbdma.o | 9 | obj-$(CONFIG_RCAR_HPB_DMAE) += rcar-hpbdma.o |
diff --git a/drivers/dma/sh/shdma-arm.h b/drivers/dma/sh/shdma-arm.h new file mode 100644 index 000000000000..a2b8258426c9 --- /dev/null +++ b/drivers/dma/sh/shdma-arm.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * Renesas SuperH DMA Engine support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Electronics, Inc. | ||
5 | * | ||
6 | * This is free software; you can redistribute it and/or modify it under the | ||
7 | * terms of version 2 the GNU General Public License as published by the Free | ||
8 | * Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef SHDMA_ARM_H | ||
12 | #define SHDMA_ARM_H | ||
13 | |||
14 | #include "shdma.h" | ||
15 | |||
16 | /* Transmit sizes and respective CHCR register values */ | ||
17 | enum { | ||
18 | XMIT_SZ_8BIT = 0, | ||
19 | XMIT_SZ_16BIT = 1, | ||
20 | XMIT_SZ_32BIT = 2, | ||
21 | XMIT_SZ_64BIT = 7, | ||
22 | XMIT_SZ_128BIT = 3, | ||
23 | XMIT_SZ_256BIT = 4, | ||
24 | XMIT_SZ_512BIT = 5, | ||
25 | }; | ||
26 | |||
27 | /* log2(size / 8) - used to calculate number of transfers */ | ||
28 | #define SH_DMAE_TS_SHIFT { \ | ||
29 | [XMIT_SZ_8BIT] = 0, \ | ||
30 | [XMIT_SZ_16BIT] = 1, \ | ||
31 | [XMIT_SZ_32BIT] = 2, \ | ||
32 | [XMIT_SZ_64BIT] = 3, \ | ||
33 | [XMIT_SZ_128BIT] = 4, \ | ||
34 | [XMIT_SZ_256BIT] = 5, \ | ||
35 | [XMIT_SZ_512BIT] = 6, \ | ||
36 | } | ||
37 | |||
38 | #define TS_LOW_BIT 0x3 /* --xx */ | ||
39 | #define TS_HI_BIT 0xc /* xx-- */ | ||
40 | |||
41 | #define TS_LOW_SHIFT (3) | ||
42 | #define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */ | ||
43 | |||
44 | #define TS_INDEX2VAL(i) \ | ||
45 | ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ | ||
46 | (((i) & TS_HI_BIT) << TS_HI_SHIFT)) | ||
47 | |||
48 | #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) | ||
49 | #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) | ||
50 | |||
51 | #endif | ||
diff --git a/drivers/dma/sh/shdma-base.c b/drivers/dma/sh/shdma-base.c index 28ca36121631..d94ab592cc1b 100644 --- a/drivers/dma/sh/shdma-base.c +++ b/drivers/dma/sh/shdma-base.c | |||
@@ -171,7 +171,8 @@ static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan) | |||
171 | return NULL; | 171 | return NULL; |
172 | } | 172 | } |
173 | 173 | ||
174 | static int shdma_setup_slave(struct shdma_chan *schan, int slave_id) | 174 | static int shdma_setup_slave(struct shdma_chan *schan, int slave_id, |
175 | dma_addr_t slave_addr) | ||
175 | { | 176 | { |
176 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | 177 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); |
177 | const struct shdma_ops *ops = sdev->ops; | 178 | const struct shdma_ops *ops = sdev->ops; |
@@ -179,7 +180,7 @@ static int shdma_setup_slave(struct shdma_chan *schan, int slave_id) | |||
179 | 180 | ||
180 | if (schan->dev->of_node) { | 181 | if (schan->dev->of_node) { |
181 | match = schan->hw_req; | 182 | match = schan->hw_req; |
182 | ret = ops->set_slave(schan, match, true); | 183 | ret = ops->set_slave(schan, match, slave_addr, true); |
183 | if (ret < 0) | 184 | if (ret < 0) |
184 | return ret; | 185 | return ret; |
185 | 186 | ||
@@ -194,7 +195,7 @@ static int shdma_setup_slave(struct shdma_chan *schan, int slave_id) | |||
194 | if (test_and_set_bit(slave_id, shdma_slave_used)) | 195 | if (test_and_set_bit(slave_id, shdma_slave_used)) |
195 | return -EBUSY; | 196 | return -EBUSY; |
196 | 197 | ||
197 | ret = ops->set_slave(schan, match, false); | 198 | ret = ops->set_slave(schan, match, slave_addr, false); |
198 | if (ret < 0) { | 199 | if (ret < 0) { |
199 | clear_bit(slave_id, shdma_slave_used); | 200 | clear_bit(slave_id, shdma_slave_used); |
200 | return ret; | 201 | return ret; |
@@ -236,7 +237,7 @@ bool shdma_chan_filter(struct dma_chan *chan, void *arg) | |||
236 | if (!schan->dev->of_node && match >= slave_num) | 237 | if (!schan->dev->of_node && match >= slave_num) |
237 | return false; | 238 | return false; |
238 | 239 | ||
239 | ret = ops->set_slave(schan, match, true); | 240 | ret = ops->set_slave(schan, match, 0, true); |
240 | if (ret < 0) | 241 | if (ret < 0) |
241 | return false; | 242 | return false; |
242 | 243 | ||
@@ -259,7 +260,7 @@ static int shdma_alloc_chan_resources(struct dma_chan *chan) | |||
259 | */ | 260 | */ |
260 | if (slave) { | 261 | if (slave) { |
261 | /* Legacy mode: .private is set in filter */ | 262 | /* Legacy mode: .private is set in filter */ |
262 | ret = shdma_setup_slave(schan, slave->slave_id); | 263 | ret = shdma_setup_slave(schan, slave->slave_id, 0); |
263 | if (ret < 0) | 264 | if (ret < 0) |
264 | goto esetslave; | 265 | goto esetslave; |
265 | } else { | 266 | } else { |
@@ -680,7 +681,9 @@ static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |||
680 | * channel, while using it... | 681 | * channel, while using it... |
681 | */ | 682 | */ |
682 | config = (struct dma_slave_config *)arg; | 683 | config = (struct dma_slave_config *)arg; |
683 | ret = shdma_setup_slave(schan, config->slave_id); | 684 | ret = shdma_setup_slave(schan, config->slave_id, |
685 | config->direction == DMA_DEV_TO_MEM ? | ||
686 | config->src_addr : config->dst_addr); | ||
684 | if (ret < 0) | 687 | if (ret < 0) |
685 | return ret; | 688 | return ret; |
686 | break; | 689 | break; |
@@ -831,8 +834,8 @@ static irqreturn_t chan_irqt(int irq, void *dev) | |||
831 | int shdma_request_irq(struct shdma_chan *schan, int irq, | 834 | int shdma_request_irq(struct shdma_chan *schan, int irq, |
832 | unsigned long flags, const char *name) | 835 | unsigned long flags, const char *name) |
833 | { | 836 | { |
834 | int ret = request_threaded_irq(irq, chan_irq, chan_irqt, | 837 | int ret = devm_request_threaded_irq(schan->dev, irq, chan_irq, |
835 | flags, name, schan); | 838 | chan_irqt, flags, name, schan); |
836 | 839 | ||
837 | schan->irq = ret < 0 ? ret : irq; | 840 | schan->irq = ret < 0 ? ret : irq; |
838 | 841 | ||
@@ -840,13 +843,6 @@ int shdma_request_irq(struct shdma_chan *schan, int irq, | |||
840 | } | 843 | } |
841 | EXPORT_SYMBOL(shdma_request_irq); | 844 | EXPORT_SYMBOL(shdma_request_irq); |
842 | 845 | ||
843 | void shdma_free_irq(struct shdma_chan *schan) | ||
844 | { | ||
845 | if (schan->irq >= 0) | ||
846 | free_irq(schan->irq, schan); | ||
847 | } | ||
848 | EXPORT_SYMBOL(shdma_free_irq); | ||
849 | |||
850 | void shdma_chan_probe(struct shdma_dev *sdev, | 846 | void shdma_chan_probe(struct shdma_dev *sdev, |
851 | struct shdma_chan *schan, int id) | 847 | struct shdma_chan *schan, int id) |
852 | { | 848 | { |
diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c index 966aaab0b4d3..06473a05fe4e 100644 --- a/drivers/dma/sh/shdma-of.c +++ b/drivers/dma/sh/shdma-of.c | |||
@@ -45,9 +45,6 @@ static int shdma_of_probe(struct platform_device *pdev) | |||
45 | const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev); | 45 | const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev); |
46 | int ret; | 46 | int ret; |
47 | 47 | ||
48 | if (!lookup) | ||
49 | return -EINVAL; | ||
50 | |||
51 | ret = of_dma_controller_register(pdev->dev.of_node, | 48 | ret = of_dma_controller_register(pdev->dev.of_node, |
52 | shdma_of_xlate, pdev); | 49 | shdma_of_xlate, pdev); |
53 | if (ret < 0) | 50 | if (ret < 0) |
diff --git a/drivers/dma/sh/shdma-r8a73a4.c b/drivers/dma/sh/shdma-r8a73a4.c new file mode 100644 index 000000000000..4fb99970a3ea --- /dev/null +++ b/drivers/dma/sh/shdma-r8a73a4.c | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * Renesas SuperH DMA Engine support for r8a73a4 (APE6) SoCs | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Electronics, Inc. | ||
5 | * | ||
6 | * This is free software; you can redistribute it and/or modify it under the | ||
7 | * terms of version 2 the GNU General Public License as published by the Free | ||
8 | * Software Foundation. | ||
9 | */ | ||
10 | #include <linux/sh_dma.h> | ||
11 | |||
12 | #include "shdma-arm.h" | ||
13 | |||
14 | const unsigned int dma_ts_shift[] = SH_DMAE_TS_SHIFT; | ||
15 | |||
16 | static const struct sh_dmae_slave_config dma_slaves[] = { | ||
17 | { | ||
18 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | ||
19 | .mid_rid = 0xd1, /* MMC0 Tx */ | ||
20 | }, { | ||
21 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | ||
22 | .mid_rid = 0xd2, /* MMC0 Rx */ | ||
23 | }, { | ||
24 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | ||
25 | .mid_rid = 0xe1, /* MMC1 Tx */ | ||
26 | }, { | ||
27 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | ||
28 | .mid_rid = 0xe2, /* MMC1 Rx */ | ||
29 | }, | ||
30 | }; | ||
31 | |||
32 | #define DMAE_CHANNEL(a, b) \ | ||
33 | { \ | ||
34 | .offset = (a) - 0x20, \ | ||
35 | .dmars = (a) - 0x20 + 0x40, \ | ||
36 | .chclr_bit = (b), \ | ||
37 | .chclr_offset = 0x80 - 0x20, \ | ||
38 | } | ||
39 | |||
40 | static const struct sh_dmae_channel dma_channels[] = { | ||
41 | DMAE_CHANNEL(0x8000, 0), | ||
42 | DMAE_CHANNEL(0x8080, 1), | ||
43 | DMAE_CHANNEL(0x8100, 2), | ||
44 | DMAE_CHANNEL(0x8180, 3), | ||
45 | DMAE_CHANNEL(0x8200, 4), | ||
46 | DMAE_CHANNEL(0x8280, 5), | ||
47 | DMAE_CHANNEL(0x8300, 6), | ||
48 | DMAE_CHANNEL(0x8380, 7), | ||
49 | DMAE_CHANNEL(0x8400, 8), | ||
50 | DMAE_CHANNEL(0x8480, 9), | ||
51 | DMAE_CHANNEL(0x8500, 10), | ||
52 | DMAE_CHANNEL(0x8580, 11), | ||
53 | DMAE_CHANNEL(0x8600, 12), | ||
54 | DMAE_CHANNEL(0x8680, 13), | ||
55 | DMAE_CHANNEL(0x8700, 14), | ||
56 | DMAE_CHANNEL(0x8780, 15), | ||
57 | DMAE_CHANNEL(0x8800, 16), | ||
58 | DMAE_CHANNEL(0x8880, 17), | ||
59 | DMAE_CHANNEL(0x8900, 18), | ||
60 | DMAE_CHANNEL(0x8980, 19), | ||
61 | }; | ||
62 | |||
63 | const struct sh_dmae_pdata r8a73a4_dma_pdata = { | ||
64 | .slave = dma_slaves, | ||
65 | .slave_num = ARRAY_SIZE(dma_slaves), | ||
66 | .channel = dma_channels, | ||
67 | .channel_num = ARRAY_SIZE(dma_channels), | ||
68 | .ts_low_shift = TS_LOW_SHIFT, | ||
69 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | ||
70 | .ts_high_shift = TS_HI_SHIFT, | ||
71 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | ||
72 | .ts_shift = dma_ts_shift, | ||
73 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | ||
74 | .dmaor_init = DMAOR_DME, | ||
75 | .chclr_present = 1, | ||
76 | .chclr_bitwise = 1, | ||
77 | }; | ||
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h index 9314e93225db..758a57b51875 100644 --- a/drivers/dma/sh/shdma.h +++ b/drivers/dma/sh/shdma.h | |||
@@ -28,18 +28,19 @@ struct sh_dmae_chan { | |||
28 | struct shdma_chan shdma_chan; | 28 | struct shdma_chan shdma_chan; |
29 | const struct sh_dmae_slave_config *config; /* Slave DMA configuration */ | 29 | const struct sh_dmae_slave_config *config; /* Slave DMA configuration */ |
30 | int xmit_shift; /* log_2(bytes_per_xfer) */ | 30 | int xmit_shift; /* log_2(bytes_per_xfer) */ |
31 | u32 __iomem *base; | 31 | void __iomem *base; |
32 | char dev_id[16]; /* unique name per DMAC of channel */ | 32 | char dev_id[16]; /* unique name per DMAC of channel */ |
33 | int pm_error; | 33 | int pm_error; |
34 | dma_addr_t slave_addr; | ||
34 | }; | 35 | }; |
35 | 36 | ||
36 | struct sh_dmae_device { | 37 | struct sh_dmae_device { |
37 | struct shdma_dev shdma_dev; | 38 | struct shdma_dev shdma_dev; |
38 | struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS]; | 39 | struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS]; |
39 | struct sh_dmae_pdata *pdata; | 40 | const struct sh_dmae_pdata *pdata; |
40 | struct list_head node; | 41 | struct list_head node; |
41 | u32 __iomem *chan_reg; | 42 | void __iomem *chan_reg; |
42 | u16 __iomem *dmars; | 43 | void __iomem *dmars; |
43 | unsigned int chcr_offset; | 44 | unsigned int chcr_offset; |
44 | u32 chcr_ie_bit; | 45 | u32 chcr_ie_bit; |
45 | }; | 46 | }; |
@@ -61,4 +62,11 @@ struct sh_dmae_desc { | |||
61 | #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\ | 62 | #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\ |
62 | struct sh_dmae_device, shdma_dev.dma_dev) | 63 | struct sh_dmae_device, shdma_dev.dma_dev) |
63 | 64 | ||
65 | #ifdef CONFIG_SHDMA_R8A73A4 | ||
66 | extern const struct sh_dmae_pdata r8a73a4_dma_pdata; | ||
67 | #define r8a73a4_shdma_devid (&r8a73a4_dma_pdata) | ||
68 | #else | ||
69 | #define r8a73a4_shdma_devid NULL | ||
70 | #endif | ||
71 | |||
64 | #endif /* __DMA_SHDMA_H */ | 72 | #endif /* __DMA_SHDMA_H */ |
diff --git a/drivers/dma/sh/shdma.c b/drivers/dma/sh/shdmac.c index b388b12f078e..3d0472b78f5f 100644 --- a/drivers/dma/sh/shdma.c +++ b/drivers/dma/sh/shdmac.c | |||
@@ -20,6 +20,8 @@ | |||
20 | 20 | ||
21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/of.h> | ||
24 | #include <linux/of_device.h> | ||
23 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
24 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
25 | #include <linux/dmaengine.h> | 27 | #include <linux/dmaengine.h> |
@@ -35,6 +37,15 @@ | |||
35 | #include "../dmaengine.h" | 37 | #include "../dmaengine.h" |
36 | #include "shdma.h" | 38 | #include "shdma.h" |
37 | 39 | ||
40 | /* DMA register */ | ||
41 | #define SAR 0x00 | ||
42 | #define DAR 0x04 | ||
43 | #define TCR 0x08 | ||
44 | #define CHCR 0x0C | ||
45 | #define DMAOR 0x40 | ||
46 | |||
47 | #define TEND 0x18 /* USB-DMAC */ | ||
48 | |||
38 | #define SH_DMAE_DRV_NAME "sh-dma-engine" | 49 | #define SH_DMAE_DRV_NAME "sh-dma-engine" |
39 | 50 | ||
40 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ | 51 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
@@ -49,27 +60,37 @@ | |||
49 | static DEFINE_SPINLOCK(sh_dmae_lock); | 60 | static DEFINE_SPINLOCK(sh_dmae_lock); |
50 | static LIST_HEAD(sh_dmae_devices); | 61 | static LIST_HEAD(sh_dmae_devices); |
51 | 62 | ||
52 | static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data) | 63 | /* |
64 | * Different DMAC implementations provide different ways to clear DMA channels: | ||
65 | * (1) none - no CHCLR registers are available | ||
66 | * (2) one CHCLR register per channel - 0 has to be written to it to clear | ||
67 | * channel buffers | ||
68 | * (3) one CHCLR per several channels - 1 has to be written to the bit, | ||
69 | * corresponding to the specific channel to reset it | ||
70 | */ | ||
71 | static void channel_clear(struct sh_dmae_chan *sh_dc) | ||
53 | { | 72 | { |
54 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | 73 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); |
74 | const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel + | ||
75 | sh_dc->shdma_chan.id; | ||
76 | u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0; | ||
55 | 77 | ||
56 | __raw_writel(data, shdev->chan_reg + | 78 | __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset); |
57 | shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset); | ||
58 | } | 79 | } |
59 | 80 | ||
60 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) | 81 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
61 | { | 82 | { |
62 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); | 83 | __raw_writel(data, sh_dc->base + reg); |
63 | } | 84 | } |
64 | 85 | ||
65 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | 86 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) |
66 | { | 87 | { |
67 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); | 88 | return __raw_readl(sh_dc->base + reg); |
68 | } | 89 | } |
69 | 90 | ||
70 | static u16 dmaor_read(struct sh_dmae_device *shdev) | 91 | static u16 dmaor_read(struct sh_dmae_device *shdev) |
71 | { | 92 | { |
72 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); | 93 | void __iomem *addr = shdev->chan_reg + DMAOR; |
73 | 94 | ||
74 | if (shdev->pdata->dmaor_is_32bit) | 95 | if (shdev->pdata->dmaor_is_32bit) |
75 | return __raw_readl(addr); | 96 | return __raw_readl(addr); |
@@ -79,7 +100,7 @@ static u16 dmaor_read(struct sh_dmae_device *shdev) | |||
79 | 100 | ||
80 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | 101 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) |
81 | { | 102 | { |
82 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); | 103 | void __iomem *addr = shdev->chan_reg + DMAOR; |
83 | 104 | ||
84 | if (shdev->pdata->dmaor_is_32bit) | 105 | if (shdev->pdata->dmaor_is_32bit) |
85 | __raw_writel(data, addr); | 106 | __raw_writel(data, addr); |
@@ -91,14 +112,14 @@ static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) | |||
91 | { | 112 | { |
92 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | 113 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); |
93 | 114 | ||
94 | __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32)); | 115 | __raw_writel(data, sh_dc->base + shdev->chcr_offset); |
95 | } | 116 | } |
96 | 117 | ||
97 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | 118 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) |
98 | { | 119 | { |
99 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | 120 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); |
100 | 121 | ||
101 | return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32)); | 122 | return __raw_readl(sh_dc->base + shdev->chcr_offset); |
102 | } | 123 | } |
103 | 124 | ||
104 | /* | 125 | /* |
@@ -133,7 +154,7 @@ static int sh_dmae_rst(struct sh_dmae_device *shdev) | |||
133 | for (i = 0; i < shdev->pdata->channel_num; i++) { | 154 | for (i = 0; i < shdev->pdata->channel_num; i++) { |
134 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | 155 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
135 | if (sh_chan) | 156 | if (sh_chan) |
136 | chclr_write(sh_chan, 0); | 157 | channel_clear(sh_chan); |
137 | } | 158 | } |
138 | } | 159 | } |
139 | 160 | ||
@@ -167,7 +188,7 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) | |||
167 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) | 188 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
168 | { | 189 | { |
169 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | 190 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
170 | struct sh_dmae_pdata *pdata = shdev->pdata; | 191 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
171 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | 192 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | |
172 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | 193 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); |
173 | 194 | ||
@@ -180,7 +201,7 @@ static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) | |||
180 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | 201 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) |
181 | { | 202 | { |
182 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | 203 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
183 | struct sh_dmae_pdata *pdata = shdev->pdata; | 204 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
184 | int i; | 205 | int i; |
185 | 206 | ||
186 | for (i = 0; i < pdata->ts_shift_num; i++) | 207 | for (i = 0; i < pdata->ts_shift_num; i++) |
@@ -240,9 +261,9 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) | |||
240 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) | 261 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
241 | { | 262 | { |
242 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | 263 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
243 | struct sh_dmae_pdata *pdata = shdev->pdata; | 264 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
244 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; | 265 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; |
245 | u16 __iomem *addr = shdev->dmars; | 266 | void __iomem *addr = shdev->dmars; |
246 | unsigned int shift = chan_pdata->dmars_bit; | 267 | unsigned int shift = chan_pdata->dmars_bit; |
247 | 268 | ||
248 | if (dmae_is_busy(sh_chan)) | 269 | if (dmae_is_busy(sh_chan)) |
@@ -253,8 +274,8 @@ static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) | |||
253 | 274 | ||
254 | /* in the case of a missing DMARS resource use first memory window */ | 275 | /* in the case of a missing DMARS resource use first memory window */ |
255 | if (!addr) | 276 | if (!addr) |
256 | addr = (u16 __iomem *)shdev->chan_reg; | 277 | addr = shdev->chan_reg; |
257 | addr += chan_pdata->dmars / sizeof(u16); | 278 | addr += chan_pdata->dmars; |
258 | 279 | ||
259 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), | 280 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
260 | addr); | 281 | addr); |
@@ -309,7 +330,7 @@ static const struct sh_dmae_slave_config *dmae_find_slave( | |||
309 | struct sh_dmae_chan *sh_chan, int match) | 330 | struct sh_dmae_chan *sh_chan, int match) |
310 | { | 331 | { |
311 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | 332 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
312 | struct sh_dmae_pdata *pdata = shdev->pdata; | 333 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
313 | const struct sh_dmae_slave_config *cfg; | 334 | const struct sh_dmae_slave_config *cfg; |
314 | int i; | 335 | int i; |
315 | 336 | ||
@@ -323,7 +344,7 @@ static const struct sh_dmae_slave_config *dmae_find_slave( | |||
323 | } else { | 344 | } else { |
324 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) | 345 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) |
325 | if (cfg->mid_rid == match) { | 346 | if (cfg->mid_rid == match) { |
326 | sh_chan->shdma_chan.slave_id = cfg->slave_id; | 347 | sh_chan->shdma_chan.slave_id = i; |
327 | return cfg; | 348 | return cfg; |
328 | } | 349 | } |
329 | } | 350 | } |
@@ -332,7 +353,7 @@ static const struct sh_dmae_slave_config *dmae_find_slave( | |||
332 | } | 353 | } |
333 | 354 | ||
334 | static int sh_dmae_set_slave(struct shdma_chan *schan, | 355 | static int sh_dmae_set_slave(struct shdma_chan *schan, |
335 | int slave_id, bool try) | 356 | int slave_id, dma_addr_t slave_addr, bool try) |
336 | { | 357 | { |
337 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | 358 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
338 | shdma_chan); | 359 | shdma_chan); |
@@ -340,8 +361,10 @@ static int sh_dmae_set_slave(struct shdma_chan *schan, | |||
340 | if (!cfg) | 361 | if (!cfg) |
341 | return -ENXIO; | 362 | return -ENXIO; |
342 | 363 | ||
343 | if (!try) | 364 | if (!try) { |
344 | sh_chan->config = cfg; | 365 | sh_chan->config = cfg; |
366 | sh_chan->slave_addr = slave_addr ? : cfg->addr; | ||
367 | } | ||
345 | 368 | ||
346 | return 0; | 369 | return 0; |
347 | } | 370 | } |
@@ -505,7 +528,8 @@ static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, | |||
505 | struct shdma_chan *schan; | 528 | struct shdma_chan *schan; |
506 | int err; | 529 | int err; |
507 | 530 | ||
508 | sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | 531 | sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan), |
532 | GFP_KERNEL); | ||
509 | if (!sh_chan) { | 533 | if (!sh_chan) { |
510 | dev_err(sdev->dma_dev.dev, | 534 | dev_err(sdev->dma_dev.dev, |
511 | "No free memory for allocating dma channels!\n"); | 535 | "No free memory for allocating dma channels!\n"); |
@@ -517,7 +541,7 @@ static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, | |||
517 | 541 | ||
518 | shdma_chan_probe(sdev, schan, id); | 542 | shdma_chan_probe(sdev, schan, id); |
519 | 543 | ||
520 | sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | 544 | sh_chan->base = shdev->chan_reg + chan_pdata->offset; |
521 | 545 | ||
522 | /* set up channel irq */ | 546 | /* set up channel irq */ |
523 | if (pdev->id >= 0) | 547 | if (pdev->id >= 0) |
@@ -541,7 +565,6 @@ static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, | |||
541 | err_no_irq: | 565 | err_no_irq: |
542 | /* remove from dmaengine device node */ | 566 | /* remove from dmaengine device node */ |
543 | shdma_chan_remove(schan); | 567 | shdma_chan_remove(schan); |
544 | kfree(sh_chan); | ||
545 | return err; | 568 | return err; |
546 | } | 569 | } |
547 | 570 | ||
@@ -552,14 +575,9 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |||
552 | int i; | 575 | int i; |
553 | 576 | ||
554 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { | 577 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { |
555 | struct sh_dmae_chan *sh_chan = container_of(schan, | ||
556 | struct sh_dmae_chan, shdma_chan); | ||
557 | BUG_ON(!schan); | 578 | BUG_ON(!schan); |
558 | 579 | ||
559 | shdma_free_irq(&sh_chan->shdma_chan); | ||
560 | |||
561 | shdma_chan_remove(schan); | 580 | shdma_chan_remove(schan); |
562 | kfree(sh_chan); | ||
563 | } | 581 | } |
564 | dma_dev->chancnt = 0; | 582 | dma_dev->chancnt = 0; |
565 | } | 583 | } |
@@ -636,7 +654,7 @@ static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) | |||
636 | * This is an exclusive slave DMA operation, may only be called after a | 654 | * This is an exclusive slave DMA operation, may only be called after a |
637 | * successful slave configuration. | 655 | * successful slave configuration. |
638 | */ | 656 | */ |
639 | return sh_chan->config->addr; | 657 | return sh_chan->slave_addr; |
640 | } | 658 | } |
641 | 659 | ||
642 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) | 660 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) |
@@ -658,9 +676,15 @@ static const struct shdma_ops sh_dmae_shdma_ops = { | |||
658 | .get_partial = sh_dmae_get_partial, | 676 | .get_partial = sh_dmae_get_partial, |
659 | }; | 677 | }; |
660 | 678 | ||
679 | static const struct of_device_id sh_dmae_of_match[] = { | ||
680 | {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,}, | ||
681 | {} | ||
682 | }; | ||
683 | MODULE_DEVICE_TABLE(of, sh_dmae_of_match); | ||
684 | |||
661 | static int sh_dmae_probe(struct platform_device *pdev) | 685 | static int sh_dmae_probe(struct platform_device *pdev) |
662 | { | 686 | { |
663 | struct sh_dmae_pdata *pdata = dev_get_platdata(&pdev->dev); | 687 | const struct sh_dmae_pdata *pdata; |
664 | unsigned long irqflags = IRQF_DISABLED, | 688 | unsigned long irqflags = IRQF_DISABLED, |
665 | chan_flag[SH_DMAE_MAX_CHANNELS] = {}; | 689 | chan_flag[SH_DMAE_MAX_CHANNELS] = {}; |
666 | int errirq, chan_irq[SH_DMAE_MAX_CHANNELS]; | 690 | int errirq, chan_irq[SH_DMAE_MAX_CHANNELS]; |
@@ -669,6 +693,11 @@ static int sh_dmae_probe(struct platform_device *pdev) | |||
669 | struct dma_device *dma_dev; | 693 | struct dma_device *dma_dev; |
670 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; | 694 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
671 | 695 | ||
696 | if (pdev->dev.of_node) | ||
697 | pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data; | ||
698 | else | ||
699 | pdata = dev_get_platdata(&pdev->dev); | ||
700 | |||
672 | /* get platform data */ | 701 | /* get platform data */ |
673 | if (!pdata || !pdata->channel_num) | 702 | if (!pdata || !pdata->channel_num) |
674 | return -ENODEV; | 703 | return -ENODEV; |
@@ -696,33 +725,22 @@ static int sh_dmae_probe(struct platform_device *pdev) | |||
696 | if (!chan || !errirq_res) | 725 | if (!chan || !errirq_res) |
697 | return -ENODEV; | 726 | return -ENODEV; |
698 | 727 | ||
699 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | 728 | shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device), |
700 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | 729 | GFP_KERNEL); |
701 | return -EBUSY; | ||
702 | } | ||
703 | |||
704 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | ||
705 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | ||
706 | err = -EBUSY; | ||
707 | goto ermrdmars; | ||
708 | } | ||
709 | |||
710 | err = -ENOMEM; | ||
711 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); | ||
712 | if (!shdev) { | 730 | if (!shdev) { |
713 | dev_err(&pdev->dev, "Not enough memory\n"); | 731 | dev_err(&pdev->dev, "Not enough memory\n"); |
714 | goto ealloc; | 732 | return -ENOMEM; |
715 | } | 733 | } |
716 | 734 | ||
717 | dma_dev = &shdev->shdma_dev.dma_dev; | 735 | dma_dev = &shdev->shdma_dev.dma_dev; |
718 | 736 | ||
719 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | 737 | shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan); |
720 | if (!shdev->chan_reg) | 738 | if (IS_ERR(shdev->chan_reg)) |
721 | goto emapchan; | 739 | return PTR_ERR(shdev->chan_reg); |
722 | if (dmars) { | 740 | if (dmars) { |
723 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | 741 | shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars); |
724 | if (!shdev->dmars) | 742 | if (IS_ERR(shdev->dmars)) |
725 | goto emapdmars; | 743 | return PTR_ERR(shdev->dmars); |
726 | } | 744 | } |
727 | 745 | ||
728 | if (!pdata->slave_only) | 746 | if (!pdata->slave_only) |
@@ -783,8 +801,8 @@ static int sh_dmae_probe(struct platform_device *pdev) | |||
783 | 801 | ||
784 | errirq = errirq_res->start; | 802 | errirq = errirq_res->start; |
785 | 803 | ||
786 | err = request_irq(errirq, sh_dmae_err, irqflags, | 804 | err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags, |
787 | "DMAC Address Error", shdev); | 805 | "DMAC Address Error", shdev); |
788 | if (err) { | 806 | if (err) { |
789 | dev_err(&pdev->dev, | 807 | dev_err(&pdev->dev, |
790 | "DMA failed requesting irq #%d, error %d\n", | 808 | "DMA failed requesting irq #%d, error %d\n", |
@@ -862,7 +880,6 @@ chan_probe_err: | |||
862 | sh_dmae_chan_remove(shdev); | 880 | sh_dmae_chan_remove(shdev); |
863 | 881 | ||
864 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) | 882 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
865 | free_irq(errirq, shdev); | ||
866 | eirq_err: | 883 | eirq_err: |
867 | #endif | 884 | #endif |
868 | rst_err: | 885 | rst_err: |
@@ -873,21 +890,9 @@ rst_err: | |||
873 | pm_runtime_put(&pdev->dev); | 890 | pm_runtime_put(&pdev->dev); |
874 | pm_runtime_disable(&pdev->dev); | 891 | pm_runtime_disable(&pdev->dev); |
875 | 892 | ||
876 | platform_set_drvdata(pdev, NULL); | ||
877 | shdma_cleanup(&shdev->shdma_dev); | 893 | shdma_cleanup(&shdev->shdma_dev); |
878 | eshdma: | 894 | eshdma: |
879 | if (dmars) | ||
880 | iounmap(shdev->dmars); | ||
881 | emapdmars: | ||
882 | iounmap(shdev->chan_reg); | ||
883 | synchronize_rcu(); | 895 | synchronize_rcu(); |
884 | emapchan: | ||
885 | kfree(shdev); | ||
886 | ealloc: | ||
887 | if (dmars) | ||
888 | release_mem_region(dmars->start, resource_size(dmars)); | ||
889 | ermrdmars: | ||
890 | release_mem_region(chan->start, resource_size(chan)); | ||
891 | 896 | ||
892 | return err; | 897 | return err; |
893 | } | 898 | } |
@@ -896,14 +901,9 @@ static int sh_dmae_remove(struct platform_device *pdev) | |||
896 | { | 901 | { |
897 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | 902 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); |
898 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; | 903 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
899 | struct resource *res; | ||
900 | int errirq = platform_get_irq(pdev, 0); | ||
901 | 904 | ||
902 | dma_async_device_unregister(dma_dev); | 905 | dma_async_device_unregister(dma_dev); |
903 | 906 | ||
904 | if (errirq > 0) | ||
905 | free_irq(errirq, shdev); | ||
906 | |||
907 | spin_lock_irq(&sh_dmae_lock); | 907 | spin_lock_irq(&sh_dmae_lock); |
908 | list_del_rcu(&shdev->node); | 908 | list_del_rcu(&shdev->node); |
909 | spin_unlock_irq(&sh_dmae_lock); | 909 | spin_unlock_irq(&sh_dmae_lock); |
@@ -913,31 +913,11 @@ static int sh_dmae_remove(struct platform_device *pdev) | |||
913 | sh_dmae_chan_remove(shdev); | 913 | sh_dmae_chan_remove(shdev); |
914 | shdma_cleanup(&shdev->shdma_dev); | 914 | shdma_cleanup(&shdev->shdma_dev); |
915 | 915 | ||
916 | if (shdev->dmars) | ||
917 | iounmap(shdev->dmars); | ||
918 | iounmap(shdev->chan_reg); | ||
919 | |||
920 | platform_set_drvdata(pdev, NULL); | ||
921 | |||
922 | synchronize_rcu(); | 916 | synchronize_rcu(); |
923 | kfree(shdev); | ||
924 | |||
925 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
926 | if (res) | ||
927 | release_mem_region(res->start, resource_size(res)); | ||
928 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
929 | if (res) | ||
930 | release_mem_region(res->start, resource_size(res)); | ||
931 | 917 | ||
932 | return 0; | 918 | return 0; |
933 | } | 919 | } |
934 | 920 | ||
935 | static const struct of_device_id sh_dmae_of_match[] = { | ||
936 | { .compatible = "renesas,shdma", }, | ||
937 | { } | ||
938 | }; | ||
939 | MODULE_DEVICE_TABLE(of, sh_dmae_of_match); | ||
940 | |||
941 | static struct platform_driver sh_dmae_driver = { | 921 | static struct platform_driver sh_dmae_driver = { |
942 | .driver = { | 922 | .driver = { |
943 | .owner = THIS_MODULE, | 923 | .owner = THIS_MODULE, |
diff --git a/drivers/dma/sh/sudmac.c b/drivers/dma/sh/sudmac.c index 8369c6f02dcc..c7e9cdff0708 100644 --- a/drivers/dma/sh/sudmac.c +++ b/drivers/dma/sh/sudmac.c | |||
@@ -150,7 +150,8 @@ static const struct sudmac_slave_config *sudmac_find_slave( | |||
150 | return NULL; | 150 | return NULL; |
151 | } | 151 | } |
152 | 152 | ||
153 | static int sudmac_set_slave(struct shdma_chan *schan, int slave_id, bool try) | 153 | static int sudmac_set_slave(struct shdma_chan *schan, int slave_id, |
154 | dma_addr_t slave_addr, bool try) | ||
154 | { | 155 | { |
155 | struct sudmac_chan *sc = to_chan(schan); | 156 | struct sudmac_chan *sc = to_chan(schan); |
156 | const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id); | 157 | const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id); |
@@ -298,11 +299,8 @@ static void sudmac_chan_remove(struct sudmac_device *su_dev) | |||
298 | int i; | 299 | int i; |
299 | 300 | ||
300 | shdma_for_each_chan(schan, &su_dev->shdma_dev, i) { | 301 | shdma_for_each_chan(schan, &su_dev->shdma_dev, i) { |
301 | struct sudmac_chan *sc = to_chan(schan); | ||
302 | |||
303 | BUG_ON(!schan); | 302 | BUG_ON(!schan); |
304 | 303 | ||
305 | shdma_free_irq(&sc->shdma_chan); | ||
306 | shdma_chan_remove(schan); | 304 | shdma_chan_remove(schan); |
307 | } | 305 | } |
308 | dma_dev->chancnt = 0; | 306 | dma_dev->chancnt = 0; |
@@ -393,7 +391,6 @@ static int sudmac_probe(struct platform_device *pdev) | |||
393 | chan_probe_err: | 391 | chan_probe_err: |
394 | sudmac_chan_remove(su_dev); | 392 | sudmac_chan_remove(su_dev); |
395 | 393 | ||
396 | platform_set_drvdata(pdev, NULL); | ||
397 | shdma_cleanup(&su_dev->shdma_dev); | 394 | shdma_cleanup(&su_dev->shdma_dev); |
398 | 395 | ||
399 | return err; | 396 | return err; |
@@ -407,7 +404,6 @@ static int sudmac_remove(struct platform_device *pdev) | |||
407 | dma_async_device_unregister(dma_dev); | 404 | dma_async_device_unregister(dma_dev); |
408 | sudmac_chan_remove(su_dev); | 405 | sudmac_chan_remove(su_dev); |
409 | shdma_cleanup(&su_dev->shdma_dev); | 406 | shdma_cleanup(&su_dev->shdma_dev); |
410 | platform_set_drvdata(pdev, NULL); | ||
411 | 407 | ||
412 | return 0; | 408 | return 0; |
413 | } | 409 | } |