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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-10-14 07:43:04 -0400
committerVinod Koul <vinod.koul@intel.com>2015-10-14 10:27:12 -0400
commit4ab54f696dc5299d7db9d924f28f408dc0404f1b (patch)
tree26cc25591b009af4b0f79ab89c07190691f436a4 /drivers/dma/edma.c
parente4402a129faca71ddd160d89ef7750da0ce2d6c4 (diff)
dmaengine: edma: Read channel mapping support only once from HW
Instead of directly reading it from CCCFG register take the information out once when we set up the configuration from the HW. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/edma.c')
-rw-r--r--drivers/dma/edma.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index d105d1ae0f13..4b2ccc9de0ad 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -223,6 +223,7 @@ struct edma_cc {
223 unsigned num_region; 223 unsigned num_region;
224 unsigned num_slots; 224 unsigned num_slots;
225 unsigned num_tc; 225 unsigned num_tc;
226 bool chmap_exist;
226 enum dma_event_q default_queue; 227 enum dma_event_q default_queue;
227 228
228 bool unused_chan_list_done; 229 bool unused_chan_list_done;
@@ -1930,11 +1931,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1930 value = GET_NUM_EVQUE(cccfg); 1931 value = GET_NUM_EVQUE(cccfg);
1931 ecc->num_tc = value + 1; 1932 ecc->num_tc = value + 1;
1932 1933
1934 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1935
1933 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); 1936 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1934 dev_dbg(dev, "num_region: %u\n", ecc->num_region); 1937 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1935 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); 1938 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1936 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); 1939 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1937 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); 1940 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1941 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1938 1942
1939 /* Nothing need to be done if queue priority is provided */ 1943 /* Nothing need to be done if queue priority is provided */
1940 if (pdata->queue_priority_mapping) 1944 if (pdata->queue_priority_mapping)
@@ -2223,7 +2227,7 @@ static int edma_probe(struct platform_device *pdev)
2223 queue_priority_mapping[i][1]); 2227 queue_priority_mapping[i][1]);
2224 2228
2225 /* Map the channel to param entry if channel mapping logic exist */ 2229 /* Map the channel to param entry if channel mapping logic exist */
2226 if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) 2230 if (ecc->chmap_exist)
2227 edma_direct_dmach_to_param_mapping(ecc); 2231 edma_direct_dmach_to_param_mapping(ecc);
2228 2232
2229 for (i = 0; i < ecc->num_region; i++) { 2233 for (i = 0; i < ecc->num_region; i++) {
@@ -2293,7 +2297,7 @@ static int edma_pm_resume(struct device *dev)
2293 queue_priority_mapping[i][1]); 2297 queue_priority_mapping[i][1]);
2294 2298
2295 /* Map the channel to param entry if channel mapping logic */ 2299 /* Map the channel to param entry if channel mapping logic */
2296 if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) 2300 if (ecc->chmap_exist)
2297 edma_direct_dmach_to_param_mapping(ecc); 2301 edma_direct_dmach_to_param_mapping(ecc);
2298 2302
2299 for (i = 0; i < ecc->num_channels; i++) { 2303 for (i = 0; i < ecc->num_channels; i++) {