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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-09 03:02:35 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-09 03:02:35 -0400
commit1236d6bb6e19fc72ffc6bbcdeb1bfefe450e54ee (patch)
tree47da3feee8e263e8c9352c85cf518e624be3c211 /drivers/crypto
parent750b1a6894ecc9b178c6e3d0a1170122971b2036 (diff)
parent8a5776a5f49812d29fe4b2d0a2d71675c3facf3f (diff)
Merge 4.14-rc4 into staging-next
We want the staging/iio fixes in here as well to handle merge issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/caam/Kconfig5
-rw-r--r--drivers/crypto/caam/ctrl.c19
-rw-r--r--drivers/crypto/caam/regs.h59
-rw-r--r--drivers/crypto/inside-secure/safexcel_cipher.c2
-rw-r--r--drivers/crypto/inside-secure/safexcel_hash.c2
-rw-r--r--drivers/crypto/talitos.c9
6 files changed, 46 insertions, 50 deletions
diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index e36aeacd7635..1eb852765469 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -1,6 +1,7 @@
1config CRYPTO_DEV_FSL_CAAM 1config CRYPTO_DEV_FSL_CAAM
2 tristate "Freescale CAAM-Multicore driver backend" 2 tristate "Freescale CAAM-Multicore driver backend"
3 depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE 3 depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
4 select SOC_BUS
4 help 5 help
5 Enables the driver module for Freescale's Cryptographic Accelerator 6 Enables the driver module for Freescale's Cryptographic Accelerator
6 and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). 7 and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
@@ -141,10 +142,6 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API
141 To compile this as a module, choose M here: the module 142 To compile this as a module, choose M here: the module
142 will be called caamrng. 143 will be called caamrng.
143 144
144config CRYPTO_DEV_FSL_CAAM_IMX
145 def_bool SOC_IMX6 || SOC_IMX7D
146 depends on CRYPTO_DEV_FSL_CAAM
147
148config CRYPTO_DEV_FSL_CAAM_DEBUG 145config CRYPTO_DEV_FSL_CAAM_DEBUG
149 bool "Enable debug output in CAAM driver" 146 bool "Enable debug output in CAAM driver"
150 depends on CRYPTO_DEV_FSL_CAAM 147 depends on CRYPTO_DEV_FSL_CAAM
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index dacb53fb690e..027e121c6f70 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -7,6 +7,7 @@
7#include <linux/device.h> 7#include <linux/device.h>
8#include <linux/of_address.h> 8#include <linux/of_address.h>
9#include <linux/of_irq.h> 9#include <linux/of_irq.h>
10#include <linux/sys_soc.h>
10 11
11#include "compat.h" 12#include "compat.h"
12#include "regs.h" 13#include "regs.h"
@@ -19,6 +20,8 @@ bool caam_little_end;
19EXPORT_SYMBOL(caam_little_end); 20EXPORT_SYMBOL(caam_little_end);
20bool caam_dpaa2; 21bool caam_dpaa2;
21EXPORT_SYMBOL(caam_dpaa2); 22EXPORT_SYMBOL(caam_dpaa2);
23bool caam_imx;
24EXPORT_SYMBOL(caam_imx);
22 25
23#ifdef CONFIG_CAAM_QI 26#ifdef CONFIG_CAAM_QI
24#include "qi.h" 27#include "qi.h"
@@ -28,19 +31,11 @@ EXPORT_SYMBOL(caam_dpaa2);
28 * i.MX targets tend to have clock control subsystems that can 31 * i.MX targets tend to have clock control subsystems that can
29 * enable/disable clocking to our device. 32 * enable/disable clocking to our device.
30 */ 33 */
31#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
32static inline struct clk *caam_drv_identify_clk(struct device *dev, 34static inline struct clk *caam_drv_identify_clk(struct device *dev,
33 char *clk_name) 35 char *clk_name)
34{ 36{
35 return devm_clk_get(dev, clk_name); 37 return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
36} 38}
37#else
38static inline struct clk *caam_drv_identify_clk(struct device *dev,
39 char *clk_name)
40{
41 return NULL;
42}
43#endif
44 39
45/* 40/*
46 * Descriptor to instantiate RNG State Handle 0 in normal mode and 41 * Descriptor to instantiate RNG State Handle 0 in normal mode and
@@ -430,6 +425,10 @@ static int caam_probe(struct platform_device *pdev)
430{ 425{
431 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; 426 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
432 u64 caam_id; 427 u64 caam_id;
428 static const struct soc_device_attribute imx_soc[] = {
429 {.family = "Freescale i.MX"},
430 {},
431 };
433 struct device *dev; 432 struct device *dev;
434 struct device_node *nprop, *np; 433 struct device_node *nprop, *np;
435 struct caam_ctrl __iomem *ctrl; 434 struct caam_ctrl __iomem *ctrl;
@@ -451,6 +450,8 @@ static int caam_probe(struct platform_device *pdev)
451 dev_set_drvdata(dev, ctrlpriv); 450 dev_set_drvdata(dev, ctrlpriv);
452 nprop = pdev->dev.of_node; 451 nprop = pdev->dev.of_node;
453 452
453 caam_imx = (bool)soc_device_match(imx_soc);
454
454 /* Enable clocking */ 455 /* Enable clocking */
455 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); 456 clk = caam_drv_identify_clk(&pdev->dev, "ipg");
456 if (IS_ERR(clk)) { 457 if (IS_ERR(clk)) {
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 2b5efff9ec3c..17cfd23a38fa 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -67,6 +67,7 @@
67 */ 67 */
68 68
69extern bool caam_little_end; 69extern bool caam_little_end;
70extern bool caam_imx;
70 71
71#define caam_to_cpu(len) \ 72#define caam_to_cpu(len) \
72static inline u##len caam##len ## _to_cpu(u##len val) \ 73static inline u##len caam##len ## _to_cpu(u##len val) \
@@ -154,13 +155,10 @@ static inline u64 rd_reg64(void __iomem *reg)
154#else /* CONFIG_64BIT */ 155#else /* CONFIG_64BIT */
155static inline void wr_reg64(void __iomem *reg, u64 data) 156static inline void wr_reg64(void __iomem *reg, u64 data)
156{ 157{
157#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 158 if (!caam_imx && caam_little_end) {
158 if (caam_little_end) {
159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); 159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
160 wr_reg32((u32 __iomem *)(reg), data); 160 wr_reg32((u32 __iomem *)(reg), data);
161 } else 161 } else {
162#endif
163 {
164 wr_reg32((u32 __iomem *)(reg), data >> 32); 162 wr_reg32((u32 __iomem *)(reg), data >> 32);
165 wr_reg32((u32 __iomem *)(reg) + 1, data); 163 wr_reg32((u32 __iomem *)(reg) + 1, data);
166 } 164 }
@@ -168,41 +166,40 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
168 166
169static inline u64 rd_reg64(void __iomem *reg) 167static inline u64 rd_reg64(void __iomem *reg)
170{ 168{
171#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 169 if (!caam_imx && caam_little_end)
172 if (caam_little_end)
173 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | 170 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
174 (u64)rd_reg32((u32 __iomem *)(reg))); 171 (u64)rd_reg32((u32 __iomem *)(reg)));
175 else 172
176#endif 173 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
177 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | 174 (u64)rd_reg32((u32 __iomem *)(reg) + 1));
178 (u64)rd_reg32((u32 __iomem *)(reg) + 1));
179} 175}
180#endif /* CONFIG_64BIT */ 176#endif /* CONFIG_64BIT */
181 177
178static inline u64 cpu_to_caam_dma64(dma_addr_t value)
179{
180 if (caam_imx)
181 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
182 (u64)cpu_to_caam32(upper_32_bits(value)));
183
184 return cpu_to_caam64(value);
185}
186
187static inline u64 caam_dma64_to_cpu(u64 value)
188{
189 if (caam_imx)
190 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
191 (u64)caam32_to_cpu(upper_32_bits(value)));
192
193 return caam64_to_cpu(value);
194}
195
182#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 196#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
183#ifdef CONFIG_SOC_IMX7D 197#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
184#define cpu_to_caam_dma(value) \ 198#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
185 (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
186 (u64)cpu_to_caam32(upper_32_bits(value)))
187#define caam_dma_to_cpu(value) \
188 (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \
189 (u64)caam32_to_cpu(upper_32_bits(value)))
190#else
191#define cpu_to_caam_dma(value) cpu_to_caam64(value)
192#define caam_dma_to_cpu(value) caam64_to_cpu(value)
193#endif /* CONFIG_SOC_IMX7D */
194#else 199#else
195#define cpu_to_caam_dma(value) cpu_to_caam32(value) 200#define cpu_to_caam_dma(value) cpu_to_caam32(value)
196#define caam_dma_to_cpu(value) caam32_to_cpu(value) 201#define caam_dma_to_cpu(value) caam32_to_cpu(value)
197#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 202#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
198
199#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
200#define cpu_to_caam_dma64(value) \
201 (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
202 (u64)cpu_to_caam32(upper_32_bits(value)))
203#else
204#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
205#endif
206 203
207/* 204/*
208 * jr_outentry 205 * jr_outentry
diff --git a/drivers/crypto/inside-secure/safexcel_cipher.c b/drivers/crypto/inside-secure/safexcel_cipher.c
index d2207ac5ba19..5438552bc6d7 100644
--- a/drivers/crypto/inside-secure/safexcel_cipher.c
+++ b/drivers/crypto/inside-secure/safexcel_cipher.c
@@ -386,7 +386,7 @@ static int safexcel_cipher_exit_inv(struct crypto_tfm *tfm)
386 struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm); 386 struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
387 struct safexcel_crypto_priv *priv = ctx->priv; 387 struct safexcel_crypto_priv *priv = ctx->priv;
388 struct skcipher_request req; 388 struct skcipher_request req;
389 struct safexcel_inv_result result = { 0 }; 389 struct safexcel_inv_result result = {};
390 int ring = ctx->base.ring; 390 int ring = ctx->base.ring;
391 391
392 memset(&req, 0, sizeof(struct skcipher_request)); 392 memset(&req, 0, sizeof(struct skcipher_request));
diff --git a/drivers/crypto/inside-secure/safexcel_hash.c b/drivers/crypto/inside-secure/safexcel_hash.c
index 3f819399cd95..3980f946874f 100644
--- a/drivers/crypto/inside-secure/safexcel_hash.c
+++ b/drivers/crypto/inside-secure/safexcel_hash.c
@@ -419,7 +419,7 @@ static int safexcel_ahash_exit_inv(struct crypto_tfm *tfm)
419 struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm); 419 struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
420 struct safexcel_crypto_priv *priv = ctx->priv; 420 struct safexcel_crypto_priv *priv = ctx->priv;
421 struct ahash_request req; 421 struct ahash_request req;
422 struct safexcel_inv_result result = { 0 }; 422 struct safexcel_inv_result result = {};
423 int ring = ctx->base.ring; 423 int ring = ctx->base.ring;
424 424
425 memset(&req, 0, sizeof(struct ahash_request)); 425 memset(&req, 0, sizeof(struct ahash_request));
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 79791c690858..dff88838dce7 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1756,9 +1756,9 @@ static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1756 req_ctx->swinit = 0; 1756 req_ctx->swinit = 0;
1757 } else { 1757 } else {
1758 desc->ptr[1] = zero_entry; 1758 desc->ptr[1] = zero_entry;
1759 /* Indicate next op is not the first. */
1760 req_ctx->first = 0;
1761 } 1759 }
1760 /* Indicate next op is not the first. */
1761 req_ctx->first = 0;
1762 1762
1763 /* HMAC key */ 1763 /* HMAC key */
1764 if (ctx->keylen) 1764 if (ctx->keylen)
@@ -1769,7 +1769,7 @@ static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1769 1769
1770 sg_count = edesc->src_nents ?: 1; 1770 sg_count = edesc->src_nents ?: 1;
1771 if (is_sec1 && sg_count > 1) 1771 if (is_sec1 && sg_count > 1)
1772 sg_copy_to_buffer(areq->src, sg_count, edesc->buf, length); 1772 sg_copy_to_buffer(req_ctx->psrc, sg_count, edesc->buf, length);
1773 else 1773 else
1774 sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count, 1774 sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count,
1775 DMA_TO_DEVICE); 1775 DMA_TO_DEVICE);
@@ -3057,7 +3057,8 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
3057 t_alg->algt.alg.hash.final = ahash_final; 3057 t_alg->algt.alg.hash.final = ahash_final;
3058 t_alg->algt.alg.hash.finup = ahash_finup; 3058 t_alg->algt.alg.hash.finup = ahash_finup;
3059 t_alg->algt.alg.hash.digest = ahash_digest; 3059 t_alg->algt.alg.hash.digest = ahash_digest;
3060 t_alg->algt.alg.hash.setkey = ahash_setkey; 3060 if (!strncmp(alg->cra_name, "hmac", 4))
3061 t_alg->algt.alg.hash.setkey = ahash_setkey;
3061 t_alg->algt.alg.hash.import = ahash_import; 3062 t_alg->algt.alg.hash.import = ahash_import;
3062 t_alg->algt.alg.hash.export = ahash_export; 3063 t_alg->algt.alg.hash.export = ahash_export;
3063 3064