Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto update from Herbert Xu:
 - add multibuffer infrastructure (single_task_running scheduler helper,
   OKed by Peter on lkml.
 - add SHA1 multibuffer implementation for AVX2.
 - reenable "by8" AVX CTR optimisation after fixing counter overflow.
 - add APM X-Gene SoC RNG support.
 - SHA256/SHA512 now handles unaligned input correctly.
 - set lz4 decompressed length correctly.
 - fix algif socket buffer allocation failure for 64K page machines.
 - misc fixes

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (47 commits)
  crypto: sha - Handle unaligned input data in generic sha256 and sha512.
  Revert "crypto: aesni - disable "by8" AVX CTR optimization"
  crypto: aesni - remove unused defines in "by8" variant
  crypto: aesni - fix counter overflow handling in "by8" variant
  hwrng: printk replacement
  crypto: qat - Removed unneeded partial state
  crypto: qat - Fix typo in name of tasklet_struct
  crypto: caam - Dynamic allocation of addresses for various memory blocks in CAAM.
  crypto: mcryptd - Fix typos in CRYPTO_MCRYPTD description
  crypto: algif - avoid excessive use of socket buffer in skcipher
  arm64: dts: add random number generator dts node to APM X-Gene platform.
  Documentation: rng: Add X-Gene SoC RNG driver documentation
  hwrng: xgene - add support for APM X-Gene SoC RNG support
  crypto: mv_cesa - Add missing #define
  crypto: testmgr - add test for lz4 and lz4hc
  crypto: lz4,lz4hc - fix decompression
  crypto: qat - Use pci_enable_msix_exact() instead of pci_enable_msix()
  crypto: drbg - fix maximum value checks on 32 bit systems
  crypto: drbg - fix sparse warning for cpu_to_be[32|64]
  crypto: sha-mb - sha1_mb_alg_state can be static
  ...

4 files changed, 16 insertions, 68 deletions

diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
index 6a92284a86b2..244d73378f0e 100644
--- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
+++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
@@ -111,7 +111,7 @@ static int adf_chr_drv_create(void)
         drv_device = device_create(adt_ctl_drv.drv_class, NULL,
                                    MKDEV(adt_ctl_drv.major, 0),
                                    NULL, DEVICE_NAME);
-        if (!drv_device) {
+        if (IS_ERR(drv_device)) {
                 pr_err("QAT: failed to create device\n");
                 goto err_cdev_del;
         }
diff --git a/drivers/crypto/qat/qat_common/adf_transport_internal.h b/drivers/crypto/qat/qat_common/adf_transport_internal.h
index f854bac276b0..c40546079981 100644
--- a/drivers/crypto/qat/qat_common/adf_transport_internal.h
+++ b/drivers/crypto/qat/qat_common/adf_transport_internal.h
@@ -75,7 +75,7 @@ struct adf_etr_ring_data {
 
 struct adf_etr_bank_data {
         struct adf_etr_ring_data rings[ADF_ETR_MAX_RINGS_PER_BANK];
-        struct tasklet_struct resp_hanlder;
+        struct tasklet_struct resp_handler;
         void __iomem *csr_addr;
         struct adf_accel_dev *accel_dev;
         uint32_t irq_coalesc_timer;
diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c
index 59df48872955..3e26fa2b293f 100644
--- a/drivers/crypto/qat/qat_common/qat_algs.c
+++ b/drivers/crypto/qat/qat_common/qat_algs.c
@@ -105,7 +105,7 @@ struct qat_alg_cd {
 #define MAX_AUTH_STATE_SIZE sizeof(struct icp_qat_hw_auth_algo_blk)
 
 struct qat_auth_state {
-        uint8_t data[MAX_AUTH_STATE_SIZE];
+        uint8_t data[MAX_AUTH_STATE_SIZE + 64];
 } __aligned(64);
 
 struct qat_alg_session_ctx {
@@ -113,10 +113,6 @@ struct qat_alg_session_ctx {
         dma_addr_t enc_cd_paddr;
         struct qat_alg_cd *dec_cd;
         dma_addr_t dec_cd_paddr;
-        struct qat_auth_state *auth_hw_state_enc;
-        dma_addr_t auth_state_enc_paddr;
-        struct qat_auth_state *auth_hw_state_dec;
-        dma_addr_t auth_state_dec_paddr;
         struct icp_qat_fw_la_bulk_req enc_fw_req_tmpl;
         struct icp_qat_fw_la_bulk_req dec_fw_req_tmpl;
         struct qat_crypto_instance *inst;
@@ -150,8 +146,9 @@ static int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 static int qat_alg_do_precomputes(struct icp_qat_hw_auth_algo_blk *hash,
                                   struct qat_alg_session_ctx *ctx,
                                   const uint8_t *auth_key,
-                                  unsigned int auth_keylen, uint8_t *auth_state)
+                                  unsigned int auth_keylen)
 {
+        struct qat_auth_state auth_state;
         struct {
                 struct shash_desc shash;
                 char ctx[crypto_shash_descsize(ctx->hash_tfm)];
@@ -161,12 +158,13 @@ static int qat_alg_do_precomputes(struct icp_qat_hw_auth_algo_blk *hash,
         struct sha512_state sha512;
         int block_size = crypto_shash_blocksize(ctx->hash_tfm);
         int digest_size = crypto_shash_digestsize(ctx->hash_tfm);
-        uint8_t *ipad = auth_state;
+        uint8_t *ipad = auth_state.data;
         uint8_t *opad = ipad + block_size;
         __be32 *hash_state_out;
         __be64 *hash512_state_out;
         int i, offset;
 
+        memset(auth_state.data, '\0', MAX_AUTH_STATE_SIZE + 64);
         desc.shash.tfm = ctx->hash_tfm;
         desc.shash.flags = 0x0;
 
@@ -298,10 +296,6 @@ static int qat_alg_init_enc_session(struct qat_alg_session_ctx *ctx,
         void *ptr = &req_tmpl->cd_ctrl;
         struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
         struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
-        struct icp_qat_fw_la_auth_req_params *auth_param =
-                (struct icp_qat_fw_la_auth_req_params *)
-                ((char *)&req_tmpl->serv_specif_rqpars +
-                 sizeof(struct icp_qat_fw_la_cipher_req_params));
 
         /* CD setup */
         cipher->aes.cipher_config.val = QAT_AES_HW_CONFIG_ENC(alg);
@@ -312,8 +306,7 @@ static int qat_alg_init_enc_session(struct qat_alg_session_ctx *ctx,
         hash->sha.inner_setup.auth_counter.counter =
                 cpu_to_be32(crypto_shash_blocksize(ctx->hash_tfm));
 
-        if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen,
-                                   (uint8_t *)ctx->auth_hw_state_enc))
+        if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen))
                 return -EFAULT;
 
         /* Request setup */
@@ -359,9 +352,6 @@ static int qat_alg_init_enc_session(struct qat_alg_session_ctx *ctx,
         hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
                         ((sizeof(struct icp_qat_hw_auth_setup) +
                          round_up(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);
-        auth_param->u1.auth_partial_st_prefix = ctx->auth_state_enc_paddr +
-                        sizeof(struct icp_qat_hw_auth_counter) +
-                        round_up(hash_cd_ctrl->inner_state1_sz, 8);
         ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);
         ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
         return 0;
@@ -399,8 +389,7 @@ static int qat_alg_init_dec_session(struct qat_alg_session_ctx *ctx,
         hash->sha.inner_setup.auth_counter.counter =
                 cpu_to_be32(crypto_shash_blocksize(ctx->hash_tfm));
 
-        if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen,
-                                   (uint8_t *)ctx->auth_hw_state_dec))
+        if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen))
                 return -EFAULT;
 
         /* Request setup */
@@ -450,9 +439,6 @@ static int qat_alg_init_dec_session(struct qat_alg_session_ctx *ctx,
         hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
                         ((sizeof(struct icp_qat_hw_auth_setup) +
                          round_up(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);
-        auth_param->u1.auth_partial_st_prefix = ctx->auth_state_enc_paddr +
-                        sizeof(struct icp_qat_hw_auth_counter) +
-                        round_up(hash_cd_ctrl->inner_state1_sz, 8);
         auth_param->auth_res_sz = digestsize;
         ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);
         ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
@@ -512,10 +498,6 @@ static int qat_alg_setkey(struct crypto_aead *tfm, const uint8_t *key,
                 dev = &GET_DEV(ctx->inst->accel_dev);
                 memset(ctx->enc_cd, 0, sizeof(struct qat_alg_cd));
                 memset(ctx->dec_cd, 0, sizeof(struct qat_alg_cd));
-                memset(ctx->auth_hw_state_enc, 0,
-                       sizeof(struct qat_auth_state));
-                memset(ctx->auth_hw_state_dec, 0,
-                       sizeof(struct qat_auth_state));
                 memset(&ctx->enc_fw_req_tmpl, 0,
                        sizeof(struct icp_qat_fw_la_bulk_req));
                 memset(&ctx->dec_fw_req_tmpl, 0,
@@ -548,22 +530,6 @@ static int qat_alg_setkey(struct crypto_aead *tfm, const uint8_t *key,
                         spin_unlock(&ctx->lock);
                         goto out_free_enc;
                 }
-                ctx->auth_hw_state_enc =
-                        dma_zalloc_coherent(dev, sizeof(struct qat_auth_state),
-                                            &ctx->auth_state_enc_paddr,
-                                            GFP_ATOMIC);
-                if (!ctx->auth_hw_state_enc) {
-                        spin_unlock(&ctx->lock);
-                        goto out_free_dec;
-                }
-                ctx->auth_hw_state_dec =
-                        dma_zalloc_coherent(dev, sizeof(struct qat_auth_state),
-                                            &ctx->auth_state_dec_paddr,
-                                            GFP_ATOMIC);
-                if (!ctx->auth_hw_state_dec) {
-                        spin_unlock(&ctx->lock);
-                        goto out_free_auth_enc;
-                }
         }
         spin_unlock(&ctx->lock);
         if (qat_alg_init_sessions(ctx, key, keylen))
@@ -572,14 +538,6 @@ static int qat_alg_setkey(struct crypto_aead *tfm, const uint8_t *key,
         return 0;
 
 out_free_all:
-        dma_free_coherent(dev, sizeof(struct qat_auth_state),
-                          ctx->auth_hw_state_dec, ctx->auth_state_dec_paddr);
-        ctx->auth_hw_state_dec = NULL;
-out_free_auth_enc:
-        dma_free_coherent(dev, sizeof(struct qat_auth_state),
-                          ctx->auth_hw_state_enc, ctx->auth_state_enc_paddr);
-        ctx->auth_hw_state_enc = NULL;
-out_free_dec:
         dma_free_coherent(dev, sizeof(struct qat_alg_cd),
                           ctx->dec_cd, ctx->dec_cd_paddr);
         ctx->dec_cd = NULL;
@@ -924,16 +882,6 @@ static void qat_alg_exit(struct crypto_tfm *tfm)
         if (ctx->dec_cd)
                 dma_free_coherent(dev, sizeof(struct qat_alg_cd),
                                   ctx->dec_cd, ctx->dec_cd_paddr);
-        if (ctx->auth_hw_state_enc)
-                dma_free_coherent(dev, sizeof(struct qat_auth_state),
-                                  ctx->auth_hw_state_enc,
-                                  ctx->auth_state_enc_paddr);
-
-        if (ctx->auth_hw_state_dec)
-                dma_free_coherent(dev, sizeof(struct qat_auth_state),
-                                  ctx->auth_hw_state_dec,
-                                  ctx->auth_state_dec_paddr);
-
         qat_crypto_put_instance(inst);
 }
 
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_isr.c b/drivers/crypto/qat/qat_dh895xcc/adf_isr.c
index d4172dedf775..67ec61e51185 100644
--- a/drivers/crypto/qat/qat_dh895xcc/adf_isr.c
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_isr.c
@@ -70,9 +70,9 @@ static int adf_enable_msix(struct adf_accel_dev *accel_dev)
         for (i = 0; i < msix_num_entries; i++)
                 pci_dev_info->msix_entries.entries[i].entry = i;
 
-        if (pci_enable_msix(pci_dev_info->pci_dev,
-                            pci_dev_info->msix_entries.entries,
-                            msix_num_entries)) {
+        if (pci_enable_msix_exact(pci_dev_info->pci_dev,
+                                  pci_dev_info->msix_entries.entries,
+                                  msix_num_entries)) {
                 pr_err("QAT: Failed to enable MSIX IRQ\n");
                 return -EFAULT;
         }
@@ -89,7 +89,7 @@ static irqreturn_t adf_msix_isr_bundle(int irq, void *bank_ptr)
         struct adf_etr_bank_data *bank = bank_ptr;
 
         WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0);
-        tasklet_hi_schedule(&bank->resp_hanlder);
+        tasklet_hi_schedule(&bank->resp_handler);
         return IRQ_HANDLED;
 }
 
@@ -217,7 +217,7 @@ static int adf_setup_bh(struct adf_accel_dev *accel_dev)
         int i;
 
         for (i = 0; i < hw_data->num_banks; i++)
-                tasklet_init(&priv_data->banks[i].resp_hanlder,
+                tasklet_init(&priv_data->banks[i].resp_handler,
                              adf_response_handler,
                              (unsigned long)&priv_data->banks[i]);
         return 0;
@@ -230,8 +230,8 @@ static void adf_cleanup_bh(struct adf_accel_dev *accel_dev)
         int i;
 
         for (i = 0; i < hw_data->num_banks; i++) {
-                tasklet_disable(&priv_data->banks[i].resp_hanlder);
-                tasklet_kill(&priv_data->banks[i].resp_hanlder);
+                tasklet_disable(&priv_data->banks[i].resp_handler);
+                tasklet_kill(&priv_data->banks[i].resp_handler);
         }
 }