crypto: qat - Intel(R) QAT DH895xcc accelerator

This patch adds DH895xCC hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.

Acked-by: John Griffin <john.griffin@intel.com>
Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com>
Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

9 files changed, 1499 insertions, 0 deletions

diff --git a/drivers/crypto/qat/qat_dh895xcc/Makefile b/drivers/crypto/qat/qat_dh895xcc/Makefile
new file mode 100644
index 000000000000..8e4924d6a54b
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/Makefile
@@ -0,0 +1,8 @@
+ccflags-y := -I$(CURDIR)/drivers/crypto/qat/qat_common
+obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc.o
+qat_dh895xcc-objs := adf_drv.o \
+                adf_isr.o \
+                adf_dh895xcc_hw_data.o \
+                adf_hw_arbiter.o \
+                qat_admin.o \
+                adf_admin.o
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_admin.c b/drivers/crypto/qat/qat_dh895xcc/adf_admin.c
new file mode 100644
index 000000000000..978d6c56639d
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_admin.c
@@ -0,0 +1,144 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <adf_accel_devices.h>
+#include "adf_drv.h"
+#include "adf_dh895xcc_hw_data.h"
+
+#define ADF_ADMINMSG_LEN 32
+
+struct adf_admin_comms {
+        dma_addr_t phy_addr;
+        void *virt_addr;
+        void __iomem *mailbox_addr;
+        struct mutex lock;      /* protects adf_admin_comms struct */
+};
+
+int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev,
+                           uint32_t ae, void *in, void *out)
+{
+        struct adf_admin_comms *admin = accel_dev->admin;
+        int offset = ae * ADF_ADMINMSG_LEN * 2;
+        void __iomem *mailbox = admin->mailbox_addr;
+        int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE;
+        int times, received;
+
+        mutex_lock(&admin->lock);
+
+        if (ADF_CSR_RD(mailbox, mb_offset) == 1) {
+                mutex_unlock(&admin->lock);
+                return -EAGAIN;
+        }
+
+        memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN);
+        ADF_CSR_WR(mailbox, mb_offset, 1);
+        received = 0;
+        for (times = 0; times < 50; times++) {
+                msleep(20);
+                if (ADF_CSR_RD(mailbox, mb_offset) == 0) {
+                        received = 1;
+                        break;
+                }
+        }
+        if (received)
+                memcpy(out, admin->virt_addr + offset +
+                       ADF_ADMINMSG_LEN, ADF_ADMINMSG_LEN);
+        else
+                pr_err("QAT: Failed to send admin msg to accelerator\n");
+
+        mutex_unlock(&admin->lock);
+        return received ? 0 : -EFAULT;
+}
+
+int adf_init_admin_comms(struct adf_accel_dev *accel_dev)
+{
+        struct adf_admin_comms *admin;
+        struct adf_bar *pmisc = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
+        void __iomem *csr = pmisc->virt_addr;
+        void __iomem *mailbox = csr + ADF_DH895XCC_MAILBOX_BASE_OFFSET;
+        uint64_t reg_val;
+
+        admin = kzalloc_node(sizeof(*accel_dev->admin), GFP_KERNEL,
+                             accel_dev->numa_node);
+        if (!admin)
+                return -ENOMEM;
+        admin->virt_addr = dma_zalloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
+                                               &admin->phy_addr, GFP_KERNEL);
+        if (!admin->virt_addr) {
+                dev_err(&GET_DEV(accel_dev), "Failed to allocate dma buff\n");
+                kfree(admin);
+                return -ENOMEM;
+        }
+        reg_val = (uint64_t)admin->phy_addr;
+        ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32);
+        ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val);
+        mutex_init(&admin->lock);
+        admin->mailbox_addr = mailbox;
+        accel_dev->admin = admin;
+        return 0;
+}
+
+void adf_exit_admin_comms(struct adf_accel_dev *accel_dev)
+{
+        struct adf_admin_comms *admin = accel_dev->admin;
+
+        if (!admin)
+                return;
+
+        if (admin->virt_addr)
+                dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
+                                  admin->virt_addr, admin->phy_addr);
+
+        mutex_destroy(&admin->lock);
+        kfree(admin);
+        accel_dev->admin = NULL;
+}
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
new file mode 100644
index 000000000000..ef05825cc651
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -0,0 +1,214 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <adf_accel_devices.h>
+#include "adf_dh895xcc_hw_data.h"
+#include "adf_drv.h"
+
+/* Worker thread to service arbiter mappings based on dev SKUs */
+static const uint32_t thrd_to_arb_map_sku4[] = {
+        0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
+        0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+static const uint32_t thrd_to_arb_map_sku6[] = {
+        0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
+        0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
+        0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
+};
+
+static struct adf_hw_device_class dh895xcc_class = {
+        .name = ADF_DH895XCC_DEVICE_NAME,
+        .type = DEV_DH895XCC,
+        .instances = 0
+};
+
+static uint32_t get_accel_mask(uint32_t fuse)
+{
+        return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
+                          ADF_DH895XCC_ACCELERATORS_MASK;
+}
+
+static uint32_t get_ae_mask(uint32_t fuse)
+{
+        return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
+}
+
+static uint32_t get_num_accels(struct adf_hw_device_data *self)
+{
+        uint32_t i, ctr = 0;
+
+        if (!self || !self->accel_mask)
+                return 0;
+
+        for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
+                if (self->accel_mask & (1 << i))
+                        ctr++;
+        }
+        return ctr;
+}
+
+static uint32_t get_num_aes(struct adf_hw_device_data *self)
+{
+        uint32_t i, ctr = 0;
+
+        if (!self || !self->ae_mask)
+                return 0;
+
+        for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
+                if (self->ae_mask & (1 << i))
+                        ctr++;
+        }
+        return ctr;
+}
+
+static uint32_t get_misc_bar_id(struct adf_hw_device_data *self)
+{
+        return ADF_DH895XCC_PMISC_BAR;
+}
+
+static uint32_t get_etr_bar_id(struct adf_hw_device_data *self)
+{
+        return ADF_DH895XCC_ETR_BAR;
+}
+
+static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
+{
+        int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
+            >> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
+
+        switch (sku) {
+        case ADF_DH895XCC_FUSECTL_SKU_1:
+                return DEV_SKU_1;
+        case ADF_DH895XCC_FUSECTL_SKU_2:
+                return DEV_SKU_2;
+        case ADF_DH895XCC_FUSECTL_SKU_3:
+                return DEV_SKU_3;
+        case ADF_DH895XCC_FUSECTL_SKU_4:
+                return DEV_SKU_4;
+        default:
+                return DEV_SKU_UNKNOWN;
+        }
+        return DEV_SKU_UNKNOWN;
+}
+
+void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
+                             uint32_t const **arb_map_config)
+{
+        switch (accel_dev->accel_pci_dev.sku) {
+        case DEV_SKU_1:
+                *arb_map_config = thrd_to_arb_map_sku4;
+                break;
+
+        case DEV_SKU_2:
+        case DEV_SKU_4:
+                *arb_map_config = thrd_to_arb_map_sku6;
+                break;
+        default:
+                pr_err("QAT: The configuration doesn't match any SKU");
+                *arb_map_config = NULL;
+        }
+}
+
+static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
+{
+        struct adf_hw_device_data *hw_device = accel_dev->hw_device;
+        struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
+        void __iomem *csr = misc_bar->virt_addr;
+        unsigned int val, i;
+
+        /* Enable Accel Engine error detection & correction */
+        for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
+                val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
+                val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
+                ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
+                val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
+                val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
+                ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
+        }
+
+        /* Enable shared memory error detection & correction */
+        for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
+                val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
+                val |= ADF_DH895XCC_ERRSSMSH_EN;
+                ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
+                val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
+                val |= ADF_DH895XCC_ERRSSMSH_EN;
+                ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
+        }
+}
+
+void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
+{
+        hw_data->dev_class = &dh895xcc_class;
+        hw_data->instance_id = dh895xcc_class.instances++;
+        hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
+        hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
+        hw_data->pci_dev_id = ADF_DH895XCC_PCI_DEVICE_ID;
+        hw_data->num_logical_accel = 1;
+        hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
+        hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
+        hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
+        hw_data->alloc_irq = adf_isr_resource_alloc;
+        hw_data->free_irq = adf_isr_resource_free;
+        hw_data->enable_error_correction = adf_enable_error_correction;
+        hw_data->hw_arb_ring_enable = adf_update_ring_arb_enable;
+        hw_data->hw_arb_ring_disable = adf_update_ring_arb_enable;
+        hw_data->get_accel_mask = get_accel_mask;
+        hw_data->get_ae_mask = get_ae_mask;
+        hw_data->get_num_accels = get_num_accels;
+        hw_data->get_num_aes = get_num_aes;
+        hw_data->get_etr_bar_id = get_etr_bar_id;
+        hw_data->get_misc_bar_id = get_misc_bar_id;
+        hw_data->get_sku = get_sku;
+        hw_data->fw_name = ADF_DH895XCC_FW;
+}
+
+void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
+{
+        hw_data->dev_class->instances--;
+}
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
new file mode 100644
index 000000000000..c5ce236aa979
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
@@ -0,0 +1,86 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef ADF_DH895x_HW_DATA_H_
+#define ADF_DH895x_HW_DATA_H_
+
+/* PCIe configuration space */
+#define ADF_DH895XCC_RX_RINGS_OFFSET 8
+#define ADF_DH895XCC_TX_RINGS_MASK 0xFF
+#define ADF_DH895XCC_FUSECTL_OFFSET 0x40
+#define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
+#define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20
+#define ADF_DH895XCC_FUSECTL_SKU_1 0x0
+#define ADF_DH895XCC_FUSECTL_SKU_2 0x1
+#define ADF_DH895XCC_FUSECTL_SKU_3 0x2
+#define ADF_DH895XCC_FUSECTL_SKU_4 0x3
+#define ADF_DH895XCC_MAX_ACCELERATORS 6
+#define ADF_DH895XCC_MAX_ACCELENGINES 12
+#define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 18
+#define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
+#define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
+#define ADF_DH895XCC_LEGFUSE_OFFSET 0x4C
+#define ADF_DH895XCC_ETR_MAX_BANKS 32
+#define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
+#define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
+#define ADF_DH895XCC_SMIA0_MASK 0xFFFF
+#define ADF_DH895XCC_SMIA1_MASK 0x1
+/* Error detection and correction */
+#define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
+#define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
+#define ADF_DH895XCC_ENABLE_AE_ECC_ERR (1 << 28)
+#define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (1 << 24 | 1 << 12)
+#define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18)
+#define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10)
+#define ADF_DH895XCC_ERRSSMSH_EN (1 << 3)
+
+/* Admin Messages Registers */
+#define ADF_DH895XCC_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
+#define ADF_DH895XCC_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
+#define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970
+#define ADF_DH895XCC_MAILBOX_STRIDE 0x1000
+#define ADF_DH895XCC_FW "qat_895xcc.bin"
+#endif
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_drv.c b/drivers/crypto/qat/qat_dh895xcc/adf_drv.c
new file mode 100644
index 000000000000..1da2f78b2058
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_drv.c
@@ -0,0 +1,448 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <linux/io.h>
+#include <adf_accel_devices.h>
+#include <adf_common_drv.h>
+#include <adf_cfg.h>
+#include <adf_transport_access_macros.h>
+#include "adf_dh895xcc_hw_data.h"
+#include "adf_drv.h"
+
+static const char adf_driver_name[] = ADF_DH895XCC_DEVICE_NAME;
+
+#define ADF_SYSTEM_DEVICE(device_id) \
+        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
+
+static const struct pci_device_id adf_pci_tbl[] = {
+        ADF_SYSTEM_DEVICE(ADF_DH895XCC_PCI_DEVICE_ID),
+        {0,}
+};
+MODULE_DEVICE_TABLE(pci, adf_pci_tbl);
+
+static int adf_probe(struct pci_dev *dev, const struct pci_device_id *ent);
+static void adf_remove(struct pci_dev *dev);
+
+static struct pci_driver adf_driver = {
+        .id_table = adf_pci_tbl,
+        .name = adf_driver_name,
+        .probe = adf_probe,
+        .remove = adf_remove
+};
+
+static void adf_cleanup_accel(struct adf_accel_dev *accel_dev)
+{
+        struct adf_accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev;
+        int i;
+
+        adf_exit_admin_comms(accel_dev);
+        adf_exit_arb(accel_dev);
+        adf_cleanup_etr_data(accel_dev);
+
+        for (i = 0; i < ADF_PCI_MAX_BARS; i++) {
+                struct adf_bar *bar = &accel_pci_dev->pci_bars[i];
+
+                if (bar->virt_addr)
+                        pci_iounmap(accel_pci_dev->pci_dev, bar->virt_addr);
+        }
+
+        if (accel_dev->hw_device) {
+                switch (accel_dev->hw_device->pci_dev_id) {
+                case ADF_DH895XCC_PCI_DEVICE_ID:
+                        adf_clean_hw_data_dh895xcc(accel_dev->hw_device);
+                        break;
+                default:
+                        break;
+                }
+                kfree(accel_dev->hw_device);
+        }
+        adf_cfg_dev_remove(accel_dev);
+        debugfs_remove(accel_dev->debugfs_dir);
+        adf_devmgr_rm_dev(accel_dev);
+        pci_release_regions(accel_pci_dev->pci_dev);
+        pci_disable_device(accel_pci_dev->pci_dev);
+        kfree(accel_dev);
+}
+
+static uint8_t adf_get_dev_node_id(struct pci_dev *pdev)
+{
+        unsigned int bus_per_cpu = 0;
+        struct cpuinfo_x86 *c = &cpu_data(num_online_cpus() - 1);
+
+        if (!c->phys_proc_id)
+                return 0;
+
+        bus_per_cpu = 256 / (c->phys_proc_id + 1);
+
+        if (bus_per_cpu != 0)
+                return pdev->bus->number / bus_per_cpu;
+        return 0;
+}
+
+static int qat_dev_start(struct adf_accel_dev *accel_dev)
+{
+        int cpus = num_online_cpus();
+        int banks = GET_MAX_BANKS(accel_dev);
+        int instances = min(cpus, banks);
+        char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
+        int i;
+        unsigned long val;
+
+        if (adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC))
+                goto err;
+        if (adf_cfg_section_add(accel_dev, "Accelerator0"))
+                goto err;
+        for (i = 0; i < instances; i++) {
+                val = i;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_BANK_NUM, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,
+                         i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);
+                val = 128;
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 512;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 0;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 2;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 4;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_TX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 8;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 10;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = 12;
+                snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_RX, i);
+                if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+
+                val = ADF_COALESCING_DEF_TIME;
+                snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
+                if (adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
+                                                key, (void *)&val, ADF_DEC))
+                        goto err;
+        }
+
+        val = i;
+        if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
+                                        ADF_NUM_CY, (void *)&val, ADF_DEC))
+                goto err;
+
+        set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
+        return adf_dev_start(accel_dev);
+err:
+        dev_err(&GET_DEV(accel_dev), "Failed to start QAT accel dev\n");
+        return -EINVAL;
+}
+
+static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+        struct adf_accel_dev *accel_dev;
+        struct adf_accel_pci *accel_pci_dev;
+        struct adf_hw_device_data *hw_data;
+        void __iomem *pmisc_bar_addr = NULL;
+        char name[ADF_DEVICE_NAME_LENGTH];
+        unsigned int i, bar_nr;
+        uint8_t node;
+        int ret;
+
+        switch (ent->device) {
+        case ADF_DH895XCC_PCI_DEVICE_ID:
+                break;
+        default:
+                dev_err(&pdev->dev, "Invalid device 0x%x.\n", ent->device);
+                return -ENODEV;
+        }
+
+        node = adf_get_dev_node_id(pdev);
+        accel_dev = kzalloc_node(sizeof(*accel_dev), GFP_KERNEL, node);
+        if (!accel_dev)
+                return -ENOMEM;
+
+        accel_dev->numa_node = node;
+        INIT_LIST_HEAD(&accel_dev->crypto_list);
+
+        /* Add accel device to accel table.
+         * This should be called before adf_cleanup_accel is called */
+        if (adf_devmgr_add_dev(accel_dev)) {
+                dev_err(&pdev->dev, "Failed to add new accelerator device.\n");
+                kfree(accel_dev);
+                return -EFAULT;
+        }
+
+        accel_dev->owner = THIS_MODULE;
+        /* Allocate and configure device configuration structure */
+        hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, node);
+        if (!hw_data) {
+                ret = -ENOMEM;
+                goto out_err;
+        }
+
+        accel_dev->hw_device = hw_data;
+        switch (ent->device) {
+        case ADF_DH895XCC_PCI_DEVICE_ID:
+                adf_init_hw_data_dh895xcc(accel_dev->hw_device);
+                break;
+        default:
+                return -ENODEV;
+        }
+        accel_pci_dev = &accel_dev->accel_pci_dev;
+        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
+        pci_read_config_dword(pdev, ADF_DH895XCC_FUSECTL_OFFSET,
+                              &hw_data->fuses);
+
+        /* Get Accelerators and Accelerators Engines masks */
+        hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses);
+        hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses);
+        accel_pci_dev->sku = hw_data->get_sku(hw_data);
+        accel_pci_dev->pci_dev = pdev;
+        /* If the device has no acceleration engines then ignore it. */
+        if (!hw_data->accel_mask || !hw_data->ae_mask ||
+            ((~hw_data->ae_mask) & 0x01)) {
+                dev_err(&pdev->dev, "No acceleration units found");
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        /* Create dev top level debugfs entry */
+        snprintf(name, sizeof(name), "%s%s_dev%d", ADF_DEVICE_NAME_PREFIX,
+                 hw_data->dev_class->name, hw_data->instance_id);
+        accel_dev->debugfs_dir = debugfs_create_dir(name, NULL);
+        if (!accel_dev->debugfs_dir) {
+                dev_err(&pdev->dev, "Could not create debugfs dir\n");
+                ret = -EINVAL;
+                goto out_err;
+        }
+
+        /* Create device configuration table */
+        ret = adf_cfg_dev_add(accel_dev);
+        if (ret)
+                goto out_err;
+
+        /* enable PCI device */
+        if (pci_enable_device(pdev)) {
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        /* set dma identifier */
+        if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
+                if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
+                        dev_err(&pdev->dev, "No usable DMA configuration\n");
+                        ret = -EFAULT;
+                        goto out_err;
+                } else {
+                        pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+                }
+
+        } else {
+                pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
+        }
+
+        if (pci_request_regions(pdev, adf_driver_name)) {
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        /* Read accelerator capabilities mask */
+        pci_read_config_dword(pdev, ADF_DH895XCC_LEGFUSE_OFFSET,
+                              &hw_data->accel_capabilities_mask);
+
+        /* Find and map all the device's BARS */
+        for (i = 0; i < ADF_PCI_MAX_BARS; i++) {
+                struct adf_bar *bar = &accel_pci_dev->pci_bars[i];
+
+                bar_nr = i * 2;
+                bar->base_addr = pci_resource_start(pdev, bar_nr);
+                if (!bar->base_addr)
+                        break;
+                bar->size = pci_resource_len(pdev, bar_nr);
+                bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
+                if (!bar->virt_addr) {
+                        dev_err(&pdev->dev, "Failed to map BAR %d\n", i);
+                        ret = -EFAULT;
+                        goto out_err;
+                }
+                if (i == ADF_DH895XCC_PMISC_BAR)
+                        pmisc_bar_addr = bar->virt_addr;
+        }
+        pci_set_master(pdev);
+
+        if (adf_enable_aer(accel_dev, &adf_driver)) {
+                dev_err(&pdev->dev, "Failed to enable aer\n");
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        if (adf_init_etr_data(accel_dev)) {
+                dev_err(&pdev->dev, "Failed initialize etr\n");
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        if (adf_init_admin_comms(accel_dev)) {
+                dev_err(&pdev->dev, "Failed initialize admin comms\n");
+                ret = -EFAULT;
+                goto out_err;
+        }
+
+        if (adf_init_arb(accel_dev)) {
+                dev_err(&pdev->dev, "Failed initialize hw arbiter\n");
+                ret = -EFAULT;
+                goto out_err;
+        }
+        if (pci_save_state(pdev)) {
+                dev_err(&pdev->dev, "Failed to save pci state\n");
+                ret = -ENOMEM;
+                goto out_err;
+        }
+
+        /* Enable bundle and misc interrupts */
+        ADF_CSR_WR(pmisc_bar_addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET,
+                   ADF_DH895XCC_SMIA0_MASK);
+        ADF_CSR_WR(pmisc_bar_addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET,
+                   ADF_DH895XCC_SMIA1_MASK);
+
+        ret = qat_dev_start(accel_dev);
+        if (ret) {
+                adf_dev_stop(accel_dev);
+                goto out_err;
+        }
+
+        return 0;
+out_err:
+        adf_cleanup_accel(accel_dev);
+        return ret;
+}
+
+static void __exit adf_remove(struct pci_dev *pdev)
+{
+        struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
+
+        if (!accel_dev) {
+                pr_err("QAT: Driver removal failed\n");
+                return;
+        }
+        if (adf_dev_stop(accel_dev))
+                dev_err(&GET_DEV(accel_dev), "Failed to stop QAT accel dev\n");
+        adf_disable_aer(accel_dev);
+        adf_cleanup_accel(accel_dev);
+}
+
+static int __init adfdrv_init(void)
+{
+        request_module("intel_qat");
+        if (qat_admin_register())
+                return -EFAULT;
+
+        if (pci_register_driver(&adf_driver)) {
+                pr_err("QAT: Driver initialization failed\n");
+                return -EFAULT;
+        }
+        return 0;
+}
+
+static void __exit adfdrv_release(void)
+{
+        pci_unregister_driver(&adf_driver);
+        qat_admin_unregister();
+}
+
+module_init(adfdrv_init);
+module_exit(adfdrv_release);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_AUTHOR("Intel");
+MODULE_DESCRIPTION("Intel(R) QuickAssist Technology");
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_drv.h b/drivers/crypto/qat/qat_dh895xcc/adf_drv.h
new file mode 100644
index 000000000000..a2fbb6ce75cd
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_drv.h
@@ -0,0 +1,67 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef ADF_DH895x_DRV_H_
+#define ADF_DH895x_DRV_H_
+#include <adf_accel_devices.h>
+#include <adf_transport.h>
+
+void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
+void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
+int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
+void adf_isr_resource_free(struct adf_accel_dev *accel_dev);
+void adf_update_ring_arb_enable(struct adf_etr_ring_data *ring);
+void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
+                             uint32_t const **arb_map_config);
+int adf_init_admin_comms(struct adf_accel_dev *accel_dev);
+void adf_exit_admin_comms(struct adf_accel_dev *accel_dev);
+int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev,
+                           uint32_t ae, void *in, void *out);
+int qat_admin_register(void);
+int qat_admin_unregister(void);
+int adf_init_arb(struct adf_accel_dev *accel_dev);
+void adf_exit_arb(struct adf_accel_dev *accel_dev);
+#endif
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_hw_arbiter.c b/drivers/crypto/qat/qat_dh895xcc/adf_hw_arbiter.c
new file mode 100644
index 000000000000..36ffa70211c9
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_hw_arbiter.c
@@ -0,0 +1,159 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <adf_accel_devices.h>
+#include <adf_transport_internal.h>
+#include "adf_drv.h"
+
+#define ADF_ARB_NUM 4
+#define ADF_ARB_REQ_RING_NUM 8
+#define ADF_ARB_REG_SIZE 0x4
+#define ADF_ARB_WTR_SIZE 0x20
+#define ADF_ARB_OFFSET 0x30000
+#define ADF_ARB_REG_SLOT 0x1000
+#define ADF_ARB_WTR_OFFSET 0x010
+#define ADF_ARB_RO_EN_OFFSET 0x090
+#define ADF_ARB_WQCFG_OFFSET 0x100
+#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
+#define ADF_ARB_WRK_2_SER_MAP 10
+#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
+
+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
+        ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
+        (ADF_ARB_REG_SLOT * index), value);
+
+#define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
+        ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
+        ADF_ARB_RO_EN_OFFSET) + (ADF_ARB_REG_SIZE * index), value);
+
+#define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
+        ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
+        ADF_ARB_WTR_OFFSET) + (ADF_ARB_WTR_SIZE * arb) + \
+        (ADF_ARB_REG_SIZE * index), value);
+
+#define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
+        ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
+        (ADF_ARB_REG_SIZE * index), value);
+
+#define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
+        ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
+        ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
+        (ADF_ARB_REG_SIZE * index), value);
+
+#define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
+        ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
+        ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value);
+
+int adf_init_arb(struct adf_accel_dev *accel_dev)
+{
+        void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
+        uint32_t arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
+        uint32_t arb, i;
+        const uint32_t *thd_2_arb_cfg;
+
+        /* Service arb configured for 32 bytes responses and
+         * ring flow control check enabled. */
+        for (arb = 0; arb < ADF_ARB_NUM; arb++)
+                WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
+
+        /* Setup service weighting */
+        for (arb = 0; arb < ADF_ARB_NUM; arb++)
+                for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
+                        WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF);
+
+        /* Setup ring response ordering */
+        for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
+                WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF);
+
+        /* Setup worker queue registers */
+        for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
+                WRITE_CSR_ARB_WQCFG(csr, i, i);
+
+        /* Map worker threads to service arbiters */
+        adf_get_arbiter_mapping(accel_dev, &thd_2_arb_cfg);
+
+        if (!thd_2_arb_cfg)
+                return -EFAULT;
+
+        for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
+                WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
+
+        return 0;
+}
+
+void adf_update_ring_arb_enable(struct adf_etr_ring_data *ring)
+{
+        WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
+                                   ring->bank->bank_number,
+                                   ring->bank->ring_mask & 0xFF);
+}
+
+void adf_exit_arb(struct adf_accel_dev *accel_dev)
+{
+        void __iomem *csr;
+        unsigned int i;
+
+        if (!accel_dev->transport)
+                return;
+
+        csr = accel_dev->transport->banks[0].csr_addr;
+
+        /* Reset arbiter configuration */
+        for (i = 0; i < ADF_ARB_NUM; i++)
+                WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
+
+        /* Shutdown work queue */
+        for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
+                WRITE_CSR_ARB_WQCFG(csr, i, 0);
+
+        /* Unmap worker threads to service arbiters */
+        for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
+                WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
+
+        /* Disable arbitration on all rings */
+        for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
+                WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
+}
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_isr.c b/drivers/crypto/qat/qat_dh895xcc/adf_isr.c
new file mode 100644
index 000000000000..77e2d3a573f4
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_isr.c
@@ -0,0 +1,266 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <adf_accel_devices.h>
+#include <adf_common_drv.h>
+#include <adf_cfg.h>
+#include <adf_cfg_strings.h>
+#include <adf_cfg_common.h>
+#include <adf_transport_access_macros.h>
+#include <adf_transport_internal.h>
+#include "adf_drv.h"
+
+static int adf_enable_msix(struct adf_accel_dev *accel_dev)
+{
+        struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        uint32_t msix_num_entries = hw_data->num_banks + 1;
+        int i;
+
+        for (i = 0; i < msix_num_entries; i++)
+                pci_dev_info->msix_entries.entries[i].entry = i;
+
+        if (pci_enable_msix(pci_dev_info->pci_dev,
+                            pci_dev_info->msix_entries.entries,
+                            msix_num_entries)) {
+                pr_err("QAT: Failed to enable MSIX IRQ\n");
+                return -EFAULT;
+        }
+        return 0;
+}
+
+static void adf_disable_msix(struct adf_accel_pci *pci_dev_info)
+{
+        pci_disable_msix(pci_dev_info->pci_dev);
+}
+
+static irqreturn_t adf_msix_isr_bundle(int irq, void *bank_ptr)
+{
+        struct adf_etr_bank_data *bank = bank_ptr;
+
+        WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0);
+        tasklet_hi_schedule(&bank->resp_hanlder);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t adf_msix_isr_ae(int irq, void *dev_ptr)
+{
+        struct adf_accel_dev *accel_dev = dev_ptr;
+
+        pr_info("QAT: qat_dev%d spurious AE interrupt\n", accel_dev->accel_id);
+        return IRQ_HANDLED;
+}
+
+static int adf_request_irqs(struct adf_accel_dev *accel_dev)
+{
+        struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
+        struct adf_etr_data *etr_data = accel_dev->transport;
+        int ret, i;
+        char *name;
+
+        /* Request msix irq for all banks */
+        for (i = 0; i < hw_data->num_banks; i++) {
+                struct adf_etr_bank_data *bank = &etr_data->banks[i];
+                unsigned int cpu, cpus = num_online_cpus();
+
+                name = *(pci_dev_info->msix_entries.names + i);
+                snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
+                         "qat%d-bundle%d", accel_dev->accel_id, i);
+                ret = request_irq(msixe[i].vector,
+                                  adf_msix_isr_bundle, 0, name, bank);
+                if (ret) {
+                        pr_err("QAT: failed to enable irq %d for %s\n",
+                               msixe[i].vector, name);
+                        return ret;
+                }
+
+                cpu = ((accel_dev->accel_id * hw_data->num_banks) + i) % cpus;
+                irq_set_affinity_hint(msixe[i].vector, get_cpu_mask(cpu));
+        }
+
+        /* Request msix irq for AE */
+        name = *(pci_dev_info->msix_entries.names + i);
+        snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
+                 "qat%d-ae-cluster", accel_dev->accel_id);
+        ret = request_irq(msixe[i].vector, adf_msix_isr_ae, 0, name, accel_dev);
+        if (ret) {
+                pr_err("QAT: failed to enable irq %d, for %s\n",
+                       msixe[i].vector, name);
+                return ret;
+        }
+        return ret;
+}
+
+static void adf_free_irqs(struct adf_accel_dev *accel_dev)
+{
+        struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
+        struct adf_etr_data *etr_data = accel_dev->transport;
+        int i;
+
+        for (i = 0; i < hw_data->num_banks; i++) {
+                irq_set_affinity_hint(msixe[i].vector, NULL);
+                free_irq(msixe[i].vector, &etr_data->banks[i]);
+        }
+        irq_set_affinity_hint(msixe[i].vector, NULL);
+        free_irq(msixe[i].vector, accel_dev);
+}
+
+static int adf_isr_alloc_msix_entry_table(struct adf_accel_dev *accel_dev)
+{
+        int i;
+        char **names;
+        struct msix_entry *entries;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        uint32_t msix_num_entries = hw_data->num_banks + 1;
+
+        entries = kzalloc_node(msix_num_entries * sizeof(*entries),
+                               GFP_KERNEL, accel_dev->numa_node);
+        if (!entries)
+                return -ENOMEM;
+
+        names = kzalloc(msix_num_entries * sizeof(char *), GFP_KERNEL);
+        if (!names) {
+                kfree(entries);
+                return -ENOMEM;
+        }
+        for (i = 0; i < msix_num_entries; i++) {
+                *(names + i) = kzalloc(ADF_MAX_MSIX_VECTOR_NAME, GFP_KERNEL);
+                if (!(*(names + i)))
+                        goto err;
+        }
+        accel_dev->accel_pci_dev.msix_entries.entries = entries;
+        accel_dev->accel_pci_dev.msix_entries.names = names;
+        return 0;
+err:
+        for (i = 0; i < msix_num_entries; i++) {
+                if (*(names + i))
+                        kfree(*(names + i));
+        }
+        kfree(entries);
+        kfree(names);
+        return -ENOMEM;
+}
+
+static void adf_isr_free_msix_entry_table(struct adf_accel_dev *accel_dev)
+{
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        uint32_t msix_num_entries = hw_data->num_banks + 1;
+        char **names = accel_dev->accel_pci_dev.msix_entries.names;
+        int i;
+
+        kfree(accel_dev->accel_pci_dev.msix_entries.entries);
+        for (i = 0; i < msix_num_entries; i++) {
+                if (*(names + i))
+                        kfree(*(names + i));
+        }
+        kfree(names);
+}
+
+static int adf_setup_bh(struct adf_accel_dev *accel_dev)
+{
+        struct adf_etr_data *priv_data = accel_dev->transport;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        int i;
+
+        for (i = 0; i < hw_data->num_banks; i++)
+                tasklet_init(&priv_data->banks[i].resp_hanlder,
+                             adf_response_handler,
+                             (unsigned long)&priv_data->banks[i]);
+        return 0;
+}
+
+static void adf_cleanup_bh(struct adf_accel_dev *accel_dev)
+{
+        struct adf_etr_data *priv_data = accel_dev->transport;
+        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
+        int i;
+
+        for (i = 0; i < hw_data->num_banks; i++) {
+                tasklet_disable(&priv_data->banks[i].resp_hanlder);
+                tasklet_kill(&priv_data->banks[i].resp_hanlder);
+        }
+}
+
+void adf_isr_resource_free(struct adf_accel_dev *accel_dev)
+{
+        adf_free_irqs(accel_dev);
+        adf_cleanup_bh(accel_dev);
+        adf_disable_msix(&accel_dev->accel_pci_dev);
+        adf_isr_free_msix_entry_table(accel_dev);
+}
+
+int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev)
+{
+        int ret;
+
+        ret = adf_isr_alloc_msix_entry_table(accel_dev);
+        if (ret)
+                return ret;
+        if (adf_enable_msix(accel_dev))
+                goto err_out;
+
+        if (adf_setup_bh(accel_dev))
+                goto err_out;
+
+        if (adf_request_irqs(accel_dev))
+                goto err_out;
+
+        return 0;
+err_out:
+        adf_isr_resource_free(accel_dev);
+        return -EFAULT;
+}
diff --git a/drivers/crypto/qat/qat_dh895xcc/qat_admin.c b/drivers/crypto/qat/qat_dh895xcc/qat_admin.c
new file mode 100644
index 000000000000..55b7a8e48bad
--- /dev/null
+++ b/drivers/crypto/qat/qat_dh895xcc/qat_admin.c
@@ -0,0 +1,107 @@
+/*
+  This file is provided under a dual BSD/GPLv2 license.  When using or
+  redistributing this file, you may do so under either license.
+
+  GPL LICENSE SUMMARY
+  Copyright(c) 2014 Intel Corporation.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but
+  WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  General Public License for more details.
+
+  Contact Information:
+  qat-linux@intel.com
+
+  BSD LICENSE
+  Copyright(c) 2014 Intel Corporation.
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of Intel Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#include <icp_qat_fw_init_admin.h>
+#include <adf_accel_devices.h>
+#include <adf_common_drv.h>
+#include "adf_drv.h"
+
+static struct service_hndl qat_admin;
+
+static int qat_send_admin_cmd(struct adf_accel_dev *accel_dev, int cmd)
+{
+        struct adf_hw_device_data *hw_device = accel_dev->hw_device;
+        struct icp_qat_fw_init_admin_req req;
+        struct icp_qat_fw_init_admin_resp resp;
+        int i;
+
+        memset(&req, 0, sizeof(struct icp_qat_fw_init_admin_req));
+        req.init_admin_cmd_id = cmd;
+        for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
+                memset(&resp, 0, sizeof(struct icp_qat_fw_init_admin_resp));
+                if (adf_put_admin_msg_sync(accel_dev, i, &req, &resp) ||
+                    resp.init_resp_hdr.status)
+                        return -EFAULT;
+        }
+        return 0;
+}
+
+static int qat_admin_start(struct adf_accel_dev *accel_dev)
+{
+        return qat_send_admin_cmd(accel_dev, ICP_QAT_FW_INIT_ME);
+}
+
+static int qat_admin_event_handler(struct adf_accel_dev *accel_dev,
+                                   enum adf_event event)
+{
+        int ret;
+
+        switch (event) {
+        case ADF_EVENT_START:
+                ret = qat_admin_start(accel_dev);
+                break;
+        case ADF_EVENT_STOP:
+        case ADF_EVENT_INIT:
+        case ADF_EVENT_SHUTDOWN:
+        default:
+                ret = 0;
+        }
+        return ret;
+}
+
+int qat_admin_register(void)
+{
+        memset(&qat_admin, 0, sizeof(struct service_hndl));
+        qat_admin.event_hld = qat_admin_event_handler;
+        qat_admin.name = "qat_admin";
+        qat_admin.admin = 1;
+        return adf_service_register(&qat_admin);
+}
+
+int qat_admin_unregister(void)
+{
+        return adf_service_unregister(&qat_admin);
+}