diff options
author | Pascal van Leeuwen <pvanleeuwen@insidesecure.com> | 2019-08-19 10:40:26 -0400 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2019-08-30 04:05:28 -0400 |
commit | f6cc45c854da0c964d1541712bb3326c72020a1c (patch) | |
tree | 17d34f77cd452ea42959f91c16422b3b318cafdc /drivers/crypto/inside-secure/safexcel.h | |
parent | 625f269a5a7a3643771320387e474bd0a61d9654 (diff) |
crypto: inside-secure - add support for using the EIP197 without vendor firmware
Until now, the inside-secure driver required a set of firmware images
supplied by the silicon vendor, typically under NDA, to be present in
/lib/firmware/inside-secure in order to be able to function.
This patch removes the dependence on this official vendor firmware by
falling back to generic "mini" FW - developed specifically for this
driver - that can be provided under GPL 2.0 through linux-firmwares.
Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/inside-secure/safexcel.h')
-rw-r--r-- | drivers/crypto/inside-secure/safexcel.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h index 2db2a9636eb7..33e5f663c249 100644 --- a/drivers/crypto/inside-secure/safexcel.h +++ b/drivers/crypto/inside-secure/safexcel.h | |||
@@ -136,8 +136,10 @@ | |||
136 | #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) | 136 | #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) |
137 | #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) | 137 | #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) |
138 | #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n))) | 138 | #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n))) |
139 | #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n))) | ||
139 | #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n))) | 140 | #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n))) |
140 | #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) | 141 | #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) |
142 | #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n))) | ||
141 | #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) | 143 | #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) |
142 | #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) | 144 | #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) |
143 | #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) | 145 | #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) |
@@ -228,6 +230,11 @@ | |||
228 | #define EIP197_DxE_THR_CTRL_EN BIT(30) | 230 | #define EIP197_DxE_THR_CTRL_EN BIT(30) |
229 | #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) | 231 | #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) |
230 | 232 | ||
233 | /* EIP197_PE_ICE_PUE/FPP_CTRL */ | ||
234 | #define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16) | ||
235 | #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0 | ||
236 | #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3) | ||
237 | |||
231 | /* EIP197_HIA_AIC_G_ENABLED_STAT */ | 238 | /* EIP197_HIA_AIC_G_ENABLED_STAT */ |
232 | #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) | 239 | #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) |
233 | #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) | 240 | #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) |
@@ -503,6 +510,11 @@ struct safexcel_command_desc { | |||
503 | * Internal structures & functions | 510 | * Internal structures & functions |
504 | */ | 511 | */ |
505 | 512 | ||
513 | #define EIP197_FW_TERMINAL_NOPS 2 | ||
514 | #define EIP197_FW_START_POLLCNT 16 | ||
515 | #define EIP197_FW_PUE_READY 0x14 | ||
516 | #define EIP197_FW_FPP_READY 0x18 | ||
517 | |||
506 | enum eip197_fw { | 518 | enum eip197_fw { |
507 | FW_IFPP = 0, | 519 | FW_IFPP = 0, |
508 | FW_IPUE, | 520 | FW_IPUE, |