Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull initial ACPI support for arm64 from Will Deacon:
 "This series introduces preliminary ACPI 5.1 support to the arm64
  kernel using the "hardware reduced" profile.  We don't support any
  peripherals yet, so it's fairly limited in scope:

   - MEMORY init (UEFI)

   - ACPI discovery (RSDP via UEFI)

   - CPU init (FADT)

   - GIC init (MADT)

   - SMP boot (MADT + PSCI)

   - ACPI Kconfig options (dependent on EXPERT)

  ACPI for arm64 has been in development for a while now and hardware
  has been available that can boot with either FDT or ACPI tables.  This
  has been made possible by both changes to the ACPI spec to cater for
  ARM-based machines (known as "hardware-reduced" in ACPI parlance) but
  also a Linaro-driven effort to get this supported on top of the Linux
  kernel.  This pull request is the result of that work.

  These changes allow us to initialise the CPUs, interrupt controller,
  and timers via ACPI tables, with memory information and cmdline coming
  from EFI.  We don't support a hybrid ACPI/FDT scheme.  Of course,
  there is still plenty of work to do (a serial console would be nice!)
  but I expect that to happen on a per-driver basis after this core
  series has been merged.

  Anyway, the diff stat here is fairly horrible, but splitting this up
  and merging it via all the different subsystems would have been
  extremely painful.  Instead, we've got all the relevant Acks in place
  and I've not seen anything other than trivial (Kconfig) conflicts in
  -next (for completeness, I've included my resolution below).  Nearly
  half of the insertions fall under Documentation/.

  So, we'll see how this goes.  Right now, it all depends on EXPERT and
  I fully expect people to use FDT by default for the immediate future"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (31 commits)
  ARM64 / ACPI: make acpi_map_gic_cpu_interface() as void function
  ARM64 / ACPI: Ignore the return error value of acpi_map_gic_cpu_interface()
  ARM64 / ACPI: fix usage of acpi_map_gic_cpu_interface
  ARM64: kernel: acpi: honour acpi=force command line parameter
  ARM64: kernel: acpi: refactor ACPI tables init and checks
  ARM64: kernel: psci: let ACPI probe PSCI version
  ARM64: kernel: psci: factor out probe function
  ACPI: move arm64 GSI IRQ model to generic GSI IRQ layer
  ARM64 / ACPI: Don't unflatten device tree if acpi=force is passed
  ARM64 / ACPI: additions of ACPI documentation for arm64
  Documentation: ACPI for ARM64
  ARM64 / ACPI: Enable ARM64 in Kconfig
  XEN / ACPI: Make XEN ACPI depend on X86
  ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64
  clocksource / arch_timer: Parse GTDT to initialize arch timer
  irqchip: Add GICv2 specific ACPI boot support
  ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi
  ACPI / processor: Make it possible to get CPU hardware ID via GICC
  ACPI / processor: Introduce phys_cpuid_t for CPU hardware ID
  ARM64 / ACPI: Parse MADT for SMP initialization
  ...

1 files changed, 105 insertions, 27 deletions

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 266469691e58..0aa135ddbf80 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/sched_clock.h>
+#include <linux/acpi.h>
 
 #include <asm/arch_timer.h>
 #include <asm/virt.h>
@@ -371,8 +372,12 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
         if (arch_timer_rate)
                 return;
 
-        /* Try to determine the frequency from the device tree or CNTFRQ */
-        if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
+        /*
+         * Try to determine the frequency from the device tree or CNTFRQ,
+         * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
+         */
+        if (!acpi_disabled ||
+            of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
                 if (cntbase)
                         arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
                 else
@@ -691,28 +696,8 @@ static void __init arch_timer_common_init(void)
         arch_timer_arch_init();
 }
 
-static void __init arch_timer_init(struct device_node *np)
+static void __init arch_timer_init(void)
 {
-        int i;
-
-        if (arch_timers_present & ARCH_CP15_TIMER) {
-                pr_warn("arch_timer: multiple nodes in dt, skipping\n");
-                return;
-        }
-
-        arch_timers_present |= ARCH_CP15_TIMER;
-        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
-                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-        arch_timer_detect_rate(NULL, np);
-
-        /*
-         * If we cannot rely on firmware initializing the timer registers then
-         * we should use the physical timers instead.
-         */
-        if (IS_ENABLED(CONFIG_ARM) &&
-            of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
-                        arch_timer_use_virtual = false;
-
         /*
          * If HYP mode is available, we know that the physical timer
          * has been configured to be accessible from PL1. Use it, so
@@ -731,13 +716,39 @@ static void __init arch_timer_init(struct device_node *np)
                 }
         }
 
-        arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-
         arch_timer_register();
         arch_timer_common_init();
 }
-CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
-CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
+
+static void __init arch_timer_of_init(struct device_node *np)
+{
+        int i;
+
+        if (arch_timers_present & ARCH_CP15_TIMER) {
+                pr_warn("arch_timer: multiple nodes in dt, skipping\n");
+                return;
+        }
+
+        arch_timers_present |= ARCH_CP15_TIMER;
+        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+        arch_timer_detect_rate(NULL, np);
+
+        arch_timer_c3stop = !of_property_read_bool(np, "always-on");
+
+        /*
+         * If we cannot rely on firmware initializing the timer registers then
+         * we should use the physical timers instead.
+         */
+        if (IS_ENABLED(CONFIG_ARM) &&
+            of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
+                        arch_timer_use_virtual = false;
+
+        arch_timer_init();
+}
+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
+CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
 
 static void __init arch_timer_mem_init(struct device_node *np)
 {
@@ -804,3 +815,70 @@ static void __init arch_timer_mem_init(struct device_node *np)
 }
 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
                        arch_timer_mem_init);
+
+#ifdef CONFIG_ACPI
+static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
+{
+        int trigger, polarity;
+
+        if (!interrupt)
+                return 0;
+
+        trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
+                        : ACPI_LEVEL_SENSITIVE;
+
+        polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
+                        : ACPI_ACTIVE_HIGH;
+
+        return acpi_register_gsi(NULL, interrupt, trigger, polarity);
+}
+
+/* Initialize per-processor generic timer */
+static int __init arch_timer_acpi_init(struct acpi_table_header *table)
+{
+        struct acpi_table_gtdt *gtdt;
+
+        if (arch_timers_present & ARCH_CP15_TIMER) {
+                pr_warn("arch_timer: already initialized, skipping\n");
+                return -EINVAL;
+        }
+
+        gtdt = container_of(table, struct acpi_table_gtdt, header);
+
+        arch_timers_present |= ARCH_CP15_TIMER;
+
+        arch_timer_ppi[PHYS_SECURE_PPI] =
+                map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
+                gtdt->secure_el1_flags);
+
+        arch_timer_ppi[PHYS_NONSECURE_PPI] =
+                map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
+                gtdt->non_secure_el1_flags);
+
+        arch_timer_ppi[VIRT_PPI] =
+                map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
+                gtdt->virtual_timer_flags);
+
+        arch_timer_ppi[HYP_PPI] =
+                map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
+                gtdt->non_secure_el2_flags);
+
+        /* Get the frequency from CNTFRQ */
+        arch_timer_detect_rate(NULL, NULL);
+
+        /* Always-on capability */
+        arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
+
+        arch_timer_init();
+        return 0;
+}
+
+/* Initialize all the generic timers presented in GTDT */
+void __init acpi_generic_timer_init(void)
+{
+        if (acpi_disabled)
+                return;
+
+        acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
+}
+#endif