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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-03-20 06:27:18 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-03-20 06:27:18 -0400
commit4958134df54c2c84e9c22ea042761d439164d26e (patch)
tree503177afab11f7d25b12a84ce25b481d305c51ba /drivers/clocksource/arc_timer.c
parentc4f528795d1add8b63652673f7262729f679c6c1 (diff)
parentc698ca5278934c0ae32297a8725ced2e27585d7f (diff)
Merge 4.16-rc6 into tty-next
We want the serial/tty fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clocksource/arc_timer.c')
-rw-r--r--drivers/clocksource/arc_timer.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 4927355f9cbe..471b428d8034 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
251 int irq_reenable = clockevent_state_periodic(evt); 251 int irq_reenable = clockevent_state_periodic(evt);
252 252
253 /* 253 /*
254 * Any write to CTRL reg ACks the interrupt, we rewrite the 254 * 1. ACK the interrupt
255 * Count when [N]ot [H]alted bit. 255 * - For ARC700, any write to CTRL reg ACKs it, so just rewrite
256 * And re-arm it if perioid by [I]nterrupt [E]nable bit 256 * Count when [N]ot [H]alted bit.
257 * - For HS3x, it is a bit subtle. On taken count-down interrupt,
258 * IP bit [3] is set, which needs to be cleared for ACK'ing.
259 * The write below can only update the other two bits, hence
260 * explicitly clears IP bit
261 * 2. Re-arm interrupt if periodic by writing to IE bit [0]
257 */ 262 */
258 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); 263 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
259 264