Merge branch 'linus' into sched/core, to resolve conflict

Conflicts:
	arch/sparc/include/asm/topology_64.h

Signed-off-by: Ingo Molnar <mingo@kernel.org>

6 files changed, 63 insertions, 27 deletions

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 44ea107cfc67..30335d3b99af 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1128,13 +1128,6 @@ static int si5351_dt_parse(struct i2c_client *client,
         if (!pdata)
                 return -ENOMEM;
 
-        pdata->clk_xtal = of_clk_get(np, 0);
-        if (!IS_ERR(pdata->clk_xtal))
-                clk_put(pdata->clk_xtal);
-        pdata->clk_clkin = of_clk_get(np, 1);
-        if (!IS_ERR(pdata->clk_clkin))
-                clk_put(pdata->clk_clkin);
-
         /*
          * property silabs,pll-source : <num src>, [<..>]
          * allow to selectively set pll source
@@ -1328,8 +1321,22 @@ static int si5351_i2c_probe(struct i2c_client *client,
         i2c_set_clientdata(client, drvdata);
         drvdata->client = client;
         drvdata->variant = variant;
-        drvdata->pxtal = pdata->clk_xtal;
-        drvdata->pclkin = pdata->clk_clkin;
+        drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
+        drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
+
+        if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
+            PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
+                return -EPROBE_DEFER;
+
+        /*
+         * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
+         *   VARIANT_C can have CLKIN instead.
+         */
+        if (IS_ERR(drvdata->pxtal) &&
+            (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
+                dev_err(&client->dev, "missing parent clock\n");
+                return -EINVAL;
+        }
 
         drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
         if (IS_ERR(drvdata->regmap)) {
@@ -1393,6 +1400,11 @@ static int si5351_i2c_probe(struct i2c_client *client,
                 }
         }
 
+        if (!IS_ERR(drvdata->pxtal))
+                clk_prepare_enable(drvdata->pxtal);
+        if (!IS_ERR(drvdata->pclkin))
+                clk_prepare_enable(drvdata->pclkin);
+
         /* register xtal input clock gate */
         memset(&init, 0, sizeof(init));
         init.name = si5351_input_names[0];
@@ -1407,7 +1419,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
         clk = devm_clk_register(&client->dev, &drvdata->xtal);
         if (IS_ERR(clk)) {
                 dev_err(&client->dev, "unable to register %s\n", init.name);
-                return PTR_ERR(clk);
+                ret = PTR_ERR(clk);
+                goto err_clk;
         }
 
         /* register clkin input clock gate */
@@ -1425,7 +1438,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
                 if (IS_ERR(clk)) {
                         dev_err(&client->dev, "unable to register %s\n",
                                 init.name);
-                        return PTR_ERR(clk);
+                        ret = PTR_ERR(clk);
+                        goto err_clk;
                 }
         }
 
@@ -1447,7 +1461,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
         clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw);
         if (IS_ERR(clk)) {
                 dev_err(&client->dev, "unable to register %s\n", init.name);
-                return -EINVAL;
+                ret = PTR_ERR(clk);
+                goto err_clk;
         }
 
         /* register PLLB or VXCO (Si5351B) */
@@ -1471,7 +1486,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
         clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw);
         if (IS_ERR(clk)) {
                 dev_err(&client->dev, "unable to register %s\n", init.name);
-                return -EINVAL;
+                ret = PTR_ERR(clk);
+                goto err_clk;
         }
 
         /* register clk multisync and clk out divider */
@@ -1492,8 +1508,10 @@ static int si5351_i2c_probe(struct i2c_client *client,
                 num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL);
 
         if (WARN_ON(!drvdata->msynth || !drvdata->clkout ||
-                    !drvdata->onecell.clks))
-                return -ENOMEM;
+                    !drvdata->onecell.clks)) {
+                ret = -ENOMEM;
+                goto err_clk;
+        }
 
         for (n = 0; n < num_clocks; n++) {
                 drvdata->msynth[n].num = n;
@@ -1511,7 +1529,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
                 if (IS_ERR(clk)) {
                         dev_err(&client->dev, "unable to register %s\n",
                                 init.name);
-                        return -EINVAL;
+                        ret = PTR_ERR(clk);
+                        goto err_clk;
                 }
         }
 
@@ -1538,7 +1557,8 @@ static int si5351_i2c_probe(struct i2c_client *client,
                 if (IS_ERR(clk)) {
                         dev_err(&client->dev, "unable to register %s\n",
                                 init.name);
-                        return -EINVAL;
+                        ret = PTR_ERR(clk);
+                        goto err_clk;
                 }
                 drvdata->onecell.clks[n] = clk;
 
@@ -1557,10 +1577,17 @@ static int si5351_i2c_probe(struct i2c_client *client,
                                   &drvdata->onecell);
         if (ret) {
                 dev_err(&client->dev, "unable to add clk provider\n");
-                return ret;
+                goto err_clk;
         }
 
         return 0;
+
+err_clk:
+        if (!IS_ERR(drvdata->pxtal))
+                clk_disable_unprepare(drvdata->pxtal);
+        if (!IS_ERR(drvdata->pclkin))
+                clk_disable_unprepare(drvdata->pclkin);
+        return ret;
 }
 
 static const struct i2c_device_id si5351_i2c_ids[] = {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 459ce9da13e0..5b0f41868b42 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1475,8 +1475,10 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *clk,
          */
         if (clk->prepare_count) {
                 clk_core_prepare(parent);
+                flags = clk_enable_lock();
                 clk_core_enable(parent);
                 clk_core_enable(clk);
+                clk_enable_unlock(flags);
         }
 
         /* update the clk tree topology */
@@ -1491,13 +1493,17 @@ static void __clk_set_parent_after(struct clk_core *core,
                                    struct clk_core *parent,
                                    struct clk_core *old_parent)
 {
+        unsigned long flags;
+
         /*
          * Finish the migration of prepare state and undo the changes done
          * for preventing a race with clk_enable().
          */
         if (core->prepare_count) {
+                flags = clk_enable_lock();
                 clk_core_disable(core);
                 clk_core_disable(old_parent);
+                clk_enable_unlock(flags);
                 clk_core_unprepare(old_parent);
         }
 }
@@ -1525,8 +1531,10 @@ static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
                 clk_enable_unlock(flags);
 
                 if (clk->prepare_count) {
+                        flags = clk_enable_lock();
                         clk_core_disable(clk);
                         clk_core_disable(parent);
+                        clk_enable_unlock(flags);
                         clk_core_unprepare(parent);
                 }
                 return ret;
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index d3458474eb3a..c66f7bc2ae87 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -71,8 +71,8 @@ static const char *gcc_xo_gpll0_bimc[] = {
 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
         { P_XO, 0 },
         { P_GPLL0_AUX, 3 },
-        { P_GPLL2_AUX, 2 },
         { P_GPLL1, 1 },
+        { P_GPLL2_AUX, 2 },
 };
 
 static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = {
@@ -1115,7 +1115,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
         F(100000000, P_GPLL0, 8, 0, 0),
         F(160000000, P_GPLL0, 5, 0, 0),
-        F(228570000, P_GPLL0, 5, 0, 0),
+        F(228570000, P_GPLL0, 3.5, 0, 0),
         { }
 };
 
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 17e9af7fe81f..a17683b2cf27 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)    += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)    += clk-exynos5410.o
 obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
-obj-$(CONFIG_ARCH_EXYNOS5433)   += clk-exynos5433.o
+obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos5433.o
 obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-audss.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..bea4a173eef5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
+        { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
 };
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 387e3e39e635..9e04ae2bb4d7 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -748,7 +748,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
         PLL_35XX_RATE(825000000U,  275, 4,  1),
         PLL_35XX_RATE(800000000U,  400, 6,  1),
         PLL_35XX_RATE(733000000U,  733, 12, 1),
-        PLL_35XX_RATE(700000000U,  360, 6,  1),
+        PLL_35XX_RATE(700000000U,  175, 3,  1),
         PLL_35XX_RATE(667000000U,  222, 4,  1),
         PLL_35XX_RATE(633000000U,  211, 4,  1),
         PLL_35XX_RATE(600000000U,  500, 5,  2),
@@ -760,14 +760,14 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
         PLL_35XX_RATE(444000000U,  370, 5,  2),
         PLL_35XX_RATE(420000000U,  350, 5,  2),
         PLL_35XX_RATE(400000000U,  400, 6,  2),
-        PLL_35XX_RATE(350000000U,  360, 6,  2),
+        PLL_35XX_RATE(350000000U,  350, 6,  2),
         PLL_35XX_RATE(333000000U,  222, 4,  2),
         PLL_35XX_RATE(300000000U,  500, 5,  3),
         PLL_35XX_RATE(266000000U,  532, 6,  3),
         PLL_35XX_RATE(200000000U,  400, 6,  3),
         PLL_35XX_RATE(166000000U,  332, 6,  3),
         PLL_35XX_RATE(160000000U,  320, 6,  3),
-        PLL_35XX_RATE(133000000U,  552, 6,  4),
+        PLL_35XX_RATE(133000000U,  532, 6,  4),
         PLL_35XX_RATE(100000000U,  400, 6,  4),
         { /* sentinel */ }
 };
@@ -1490,7 +1490,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
 
         /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
         GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
-                        ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
+                        ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
 
         /* ENABLE_PCLK_MIF_SECURE_RTC */
         GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
@@ -3665,7 +3665,7 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
                         ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
         GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
                         ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
-        GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
+        GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
                         ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
 };
 
@@ -3927,7 +3927,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
 #define ENABLE_PCLK_MSCL                                0x0900
 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0         0x0904
 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1         0x0908
-#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x000c
+#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG               0x090c
 #define ENABLE_SCLK_MSCL                                0x0a00
 #define ENABLE_IP_MSCL0                                 0x0b00
 #define ENABLE_IP_MSCL1                                 0x0b04