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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-08 15:54:24 -0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-08 15:54:24 -0400 |
| commit | e4abe2b9ab3ac79537d99dfceff7302739a586bc (patch) | |
| tree | ed6034e05fff8f19c24b4fc4828bb8d87e0d5235 /drivers/clk | |
| parent | dc7066c54107255f5f9a11bf3f82417c9b1aef51 (diff) | |
| parent | 6654674cb7b5953ac04fc9d7f5f511676ae97e29 (diff) | |
Merge tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes
Clock Fixes for the Allwinner SoCs, 4.8 Edition
The usual bunch of fixes to the our clock drivers, mostly targetted to the
brand new sunxi-ng drivers.
* tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi-ng: Fix wrong reset register offsets
clk: sunxi-ng: nk: Make ccu_nk_find_best static
clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
clk: sunxi: Fix return value check in sun8i_a23_mbus_setup()
clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 16 | ||||
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_nk.c | 6 | ||||
| -rw-r--r-- | drivers/clk/sunxi/clk-a10-pll2.c | 4 | ||||
| -rw-r--r-- | drivers/clk/sunxi/clk-sun8i-mbus.c | 2 |
4 files changed, 14 insertions, 14 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 9af359544110..267f99523fbe 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c | |||
| @@ -783,14 +783,14 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = { | |||
| 783 | [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, | 783 | [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, |
| 784 | [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, | 784 | [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, |
| 785 | 785 | ||
| 786 | [RST_BUS_I2C0] = { 0x2d4, BIT(0) }, | 786 | [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, |
| 787 | [RST_BUS_I2C1] = { 0x2d4, BIT(1) }, | 787 | [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, |
| 788 | [RST_BUS_I2C2] = { 0x2d4, BIT(2) }, | 788 | [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, |
| 789 | [RST_BUS_UART0] = { 0x2d4, BIT(16) }, | 789 | [RST_BUS_UART0] = { 0x2d8, BIT(16) }, |
| 790 | [RST_BUS_UART1] = { 0x2d4, BIT(17) }, | 790 | [RST_BUS_UART1] = { 0x2d8, BIT(17) }, |
| 791 | [RST_BUS_UART2] = { 0x2d4, BIT(18) }, | 791 | [RST_BUS_UART2] = { 0x2d8, BIT(18) }, |
| 792 | [RST_BUS_UART3] = { 0x2d4, BIT(19) }, | 792 | [RST_BUS_UART3] = { 0x2d8, BIT(19) }, |
| 793 | [RST_BUS_SCR] = { 0x2d4, BIT(20) }, | 793 | [RST_BUS_SCR] = { 0x2d8, BIT(20) }, |
| 794 | }; | 794 | }; |
| 795 | 795 | ||
| 796 | static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { | 796 | static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { |
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c index 4470ffc8cf0d..d6fafb397489 100644 --- a/drivers/clk/sunxi-ng/ccu_nk.c +++ b/drivers/clk/sunxi-ng/ccu_nk.c | |||
| @@ -14,9 +14,9 @@ | |||
| 14 | #include "ccu_gate.h" | 14 | #include "ccu_gate.h" |
| 15 | #include "ccu_nk.h" | 15 | #include "ccu_nk.h" |
| 16 | 16 | ||
| 17 | void ccu_nk_find_best(unsigned long parent, unsigned long rate, | 17 | static void ccu_nk_find_best(unsigned long parent, unsigned long rate, |
| 18 | unsigned int max_n, unsigned int max_k, | 18 | unsigned int max_n, unsigned int max_k, |
| 19 | unsigned int *n, unsigned int *k) | 19 | unsigned int *n, unsigned int *k) |
| 20 | { | 20 | { |
| 21 | unsigned long best_rate = 0; | 21 | unsigned long best_rate = 0; |
| 22 | unsigned int best_k = 0, best_n = 0; | 22 | unsigned int best_k = 0, best_n = 0; |
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c index 0ee1f363e4be..d8eab90ae661 100644 --- a/drivers/clk/sunxi/clk-a10-pll2.c +++ b/drivers/clk/sunxi/clk-a10-pll2.c | |||
| @@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, | |||
| 73 | SUN4I_PLL2_PRE_DIV_WIDTH, | 73 | SUN4I_PLL2_PRE_DIV_WIDTH, |
| 74 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | 74 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
| 75 | &sun4i_a10_pll2_lock); | 75 | &sun4i_a10_pll2_lock); |
| 76 | if (!prediv_clk) { | 76 | if (IS_ERR(prediv_clk)) { |
| 77 | pr_err("Couldn't register the prediv clock\n"); | 77 | pr_err("Couldn't register the prediv clock\n"); |
| 78 | goto err_free_array; | 78 | goto err_free_array; |
| 79 | } | 79 | } |
| @@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, | |||
| 106 | &mult->hw, &clk_multiplier_ops, | 106 | &mult->hw, &clk_multiplier_ops, |
| 107 | &gate->hw, &clk_gate_ops, | 107 | &gate->hw, &clk_gate_ops, |
| 108 | CLK_SET_RATE_PARENT); | 108 | CLK_SET_RATE_PARENT); |
| 109 | if (!base_clk) { | 109 | if (IS_ERR(base_clk)) { |
| 110 | pr_err("Couldn't register the base multiplier clock\n"); | 110 | pr_err("Couldn't register the base multiplier clock\n"); |
| 111 | goto err_free_multiplier; | 111 | goto err_free_multiplier; |
| 112 | } | 112 | } |
diff --git a/drivers/clk/sunxi/clk-sun8i-mbus.c b/drivers/clk/sunxi/clk-sun8i-mbus.c index 411d3033a96e..b200ebf159ee 100644 --- a/drivers/clk/sunxi/clk-sun8i-mbus.c +++ b/drivers/clk/sunxi/clk-sun8i-mbus.c | |||
| @@ -48,7 +48,7 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node) | |||
| 48 | return; | 48 | return; |
| 49 | 49 | ||
| 50 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); | 50 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
| 51 | if (!reg) { | 51 | if (IS_ERR(reg)) { |
| 52 | pr_err("Could not get registers for sun8i-mbus-clk\n"); | 52 | pr_err("Could not get registers for sun8i-mbus-clk\n"); |
| 53 | goto err_free_parents; | 53 | goto err_free_parents; |
| 54 | } | 54 | } |