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authorXing Zheng <zhengxing@rock-chips.com>2016-03-08 21:43:31 -0500
committerHeiko Stuebner <heiko@sntech.de>2016-03-26 19:53:20 -0400
commit9387bfd19b457085189d918ef117ffd63c4d67a0 (patch)
treee56d741224bf5eecb58f4c748f57b987c9be5117 /drivers/clk
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Because there are some frac clock mux nodes don't have a gate node on the RK3399. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 39c198bbcbee..f3da205073ee 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -428,6 +428,22 @@ struct rockchip_clk_branch {
428 .child = ch, \ 428 .child = ch, \
429 } 429 }
430 430
431#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
432 { \
433 .id = _id, \
434 .branch_type = branch_fraction_divider, \
435 .name = cname, \
436 .parent_names = (const char *[]){ pname }, \
437 .num_parents = 1, \
438 .flags = f, \
439 .muxdiv_offset = mo, \
440 .div_shift = 16, \
441 .div_width = 16, \
442 .div_flags = df, \
443 .gate_offset = -1, \
444 .child = ch, \
445 }
446
431#define MUX(_id, cname, pnames, f, o, s, w, mf) \ 447#define MUX(_id, cname, pnames, f, o, s, w, mf) \
432 { \ 448 { \
433 .id = _id, \ 449 .id = _id, \