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authorChanwoo Choi <cw00.choi@samsung.com>2016-04-15 02:32:53 -0400
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-04-15 12:13:45 -0400
commit81fed6e342c04a4ecb0650c914d24bd57c6c168f (patch)
tree6b0d48e7ef66a2a9cb655dba3c18596cbf181cdc /drivers/clk
parent72b67b3fcb5f500e73dfd42dce3a4749ba84e4bf (diff)
clk: samsung: exynos542x: Add the clock id for ACLK
This patch adds the clock id for ACLK clock which is source clock of AMBA AXI bus. This clock should be handled in the bus frequency scaling driver. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c77
1 files changed, 47 insertions, 30 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index be03ed0fcb6b..92382cef9f90 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
554}; 554};
555 555
556static struct samsung_div_clock exynos5800_div_clks[] __initdata = { 556static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
557 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), 557 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
558 558 "mout_aclk400_wcore", DIV_TOP0, 16, 3),
559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
560 DIV_TOP8, 16, 3), 560 DIV_TOP8, 16, 3),
561 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 561 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
@@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
607}; 607};
608 608
609static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 609static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
610 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", 610 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
611 DIV_TOP0, 16, 3), 611 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
612}; 612};
613 613
614static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 614static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
@@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
785 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 785 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
786 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 786 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
787 787
788 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), 788 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
789 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 789 DIV_TOP0, 0, 3),
790 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 790 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
791 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 791 DIV_TOP0, 4, 3),
792 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), 792 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
793 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 793 DIV_TOP0, 8, 3),
794 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 794 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
795 795 DIV_TOP0, 12, 3),
796 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 796 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
797 DIV_TOP1, 0, 3), 797 DIV_TOP0, 20, 3),
798 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", 798 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
799 DIV_TOP1, 4, 3), 799 DIV_TOP0, 24, 3),
800 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 800 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
801 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", 801 DIV_TOP0, 28, 3),
802 DIV_TOP1, 16, 3), 802 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
803 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 803 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
804 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 804 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
805 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 805 "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
806 806 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
807 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 807 DIV_TOP1, 8, 6),
808 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 808 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
809 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 809 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
810 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 810 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
811 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), 811 DIV_TOP1, 20, 3),
812 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 812 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
813 DIV_TOP1, 24, 3),
814 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
815 DIV_TOP1, 28, 3),
816
817 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
818 DIV_TOP2, 8, 3),
819 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
820 DIV_TOP2, 12, 3),
821 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
822 16, 3),
823 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
824 DIV_TOP2, 20, 3),
825 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
826 "mout_aclk300_disp1", DIV_TOP2, 24, 3),
827 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
828 DIV_TOP2, 28, 3),
813 829
814 /* DISP1 Block */ 830 /* DISP1 Block */
815 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 831 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
@@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
817 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 833 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
818 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 834 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
819 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 835 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
820 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), 836 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
837 "mout_aclk400_disp1", DIV_TOP2, 4, 3),
821 838
822 /* Audio Block */ 839 /* Audio Block */
823 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 840 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 14:31:05 -0400