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authorStephen Boyd <sboyd@codeaurora.org>2016-03-29 19:37:54 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-03-29 19:37:54 -0400
commit5759d6cdd48587968256859912b1c967a57eb6e1 (patch)
treef45b94d1f2c62ec3765b191bf41e9aee74face88 /drivers/clk
parent2aac7ddf9a410e3418c9cc69618f304550466793 (diff)
parentd3d6f15fd376e3dbba851724057b112558c70b79 (diff)
Merge tag 'bcm2835-clk-next-2016-03-17' of git://github.com/anholt/linux into clk-next
This pull request against clk/clk-next brings in fixes for fractional clocks on 2835, add the PCM clock that used to be driven directly by the bcm2835-i2s driver (that driver has been broken since this driver was introduced), and adds many other new clocks. * tag 'bcm2835-clk-next-2016-03-17' of git://github.com/anholt/linux: clk: bcm2835: add missing osc and per clocks clk: bcm2835: add missing PLL clock dividers clk: bcm2835: enable management of PCM clock clk: bcm2835: reorganize bcm2835_clock_array assignment clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver clk: bcm2835: expose raw clock-registers via debugfs clk: bcm2835: clean up coding style issues clk: bcm2835: correctly enable fractional clock support clk: bcm2835: divider value has to be 1 or more clk: bcm2835: add locking to pll*_on/off methods clk: bcm2835: pll_off should only update CM_PLL_ANARST
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c1203
1 files changed, 714 insertions, 489 deletions
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index c74ed3fd496d..4c0f1b504e2f 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -12,9 +12,6 @@
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 15 */
19 16
20/** 17/**
@@ -40,6 +37,7 @@
40#include <linux/clk-provider.h> 37#include <linux/clk-provider.h>
41#include <linux/clkdev.h> 38#include <linux/clkdev.h>
42#include <linux/clk/bcm2835.h> 39#include <linux/clk/bcm2835.h>
40#include <linux/debugfs.h>
43#include <linux/module.h> 41#include <linux/module.h>
44#include <linux/of.h> 42#include <linux/of.h>
45#include <linux/platform_device.h> 43#include <linux/platform_device.h>
@@ -51,6 +49,7 @@
51#define CM_GNRICCTL 0x000 49#define CM_GNRICCTL 0x000
52#define CM_GNRICDIV 0x004 50#define CM_GNRICDIV 0x004
53# define CM_DIV_FRAC_BITS 12 51# define CM_DIV_FRAC_BITS 12
52# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
54 53
55#define CM_VPUCTL 0x008 54#define CM_VPUCTL 0x008
56#define CM_VPUDIV 0x00c 55#define CM_VPUDIV 0x00c
@@ -118,6 +117,8 @@
118#define CM_SDCCTL 0x1a8 117#define CM_SDCCTL 0x1a8
119#define CM_SDCDIV 0x1ac 118#define CM_SDCDIV 0x1ac
120#define CM_ARMCTL 0x1b0 119#define CM_ARMCTL 0x1b0
120#define CM_AVEOCTL 0x1b8
121#define CM_AVEODIV 0x1bc
121#define CM_EMMCCTL 0x1c0 122#define CM_EMMCCTL 0x1c0
122#define CM_EMMCDIV 0x1c4 123#define CM_EMMCDIV 0x1c4
123 124
@@ -128,6 +129,7 @@
128# define CM_GATE BIT(CM_GATE_BIT) 129# define CM_GATE BIT(CM_GATE_BIT)
129# define CM_BUSY BIT(7) 130# define CM_BUSY BIT(7)
130# define CM_BUSYD BIT(8) 131# define CM_BUSYD BIT(8)
132# define CM_FRAC BIT(9)
131# define CM_SRC_SHIFT 0 133# define CM_SRC_SHIFT 0
132# define CM_SRC_BITS 4 134# define CM_SRC_BITS 4
133# define CM_SRC_MASK 0xf 135# define CM_SRC_MASK 0xf
@@ -297,11 +299,11 @@
297struct bcm2835_cprman { 299struct bcm2835_cprman {
298 struct device *dev; 300 struct device *dev;
299 void __iomem *regs; 301 void __iomem *regs;
300 spinlock_t regs_lock; 302 spinlock_t regs_lock; /* spinlock for all clocks */
301 const char *osc_name; 303 const char *osc_name;
302 304
303 struct clk_onecell_data onecell; 305 struct clk_onecell_data onecell;
304 struct clk *clks[BCM2835_CLOCK_COUNT]; 306 struct clk *clks[];
305}; 307};
306 308
307static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 309static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
@@ -314,6 +316,27 @@ static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
314 return readl(cprman->regs + reg); 316 return readl(cprman->regs + reg);
315} 317}
316 318
319static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
320 struct debugfs_reg32 *regs, size_t nregs,
321 struct dentry *dentry)
322{
323 struct dentry *regdump;
324 struct debugfs_regset32 *regset;
325
326 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
327 if (!regset)
328 return -ENOMEM;
329
330 regset->regs = regs;
331 regset->nregs = nregs;
332 regset->base = cprman->regs + base;
333
334 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
335 regset);
336
337 return regdump ? 0 : -ENOMEM;
338}
339
317/* 340/*
318 * These are fixed clocks. They're probably not all root clocks and it may 341 * These are fixed clocks. They're probably not all root clocks and it may
319 * be possible to turn them on and off but until this is mapped out better 342 * be possible to turn them on and off but until this is mapped out better
@@ -394,115 +417,10 @@ static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
394 .fb_prediv_mask = BIT(11), 417 .fb_prediv_mask = BIT(11),
395}; 418};
396 419
397/*
398 * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
399 * Port 2) transmitter clock.
400 *
401 * It is in the PX LDO power domain, which is on when the AUDIO domain
402 * is on.
403 */
404static const struct bcm2835_pll_data bcm2835_plla_data = {
405 .name = "plla",
406 .cm_ctrl_reg = CM_PLLA,
407 .a2w_ctrl_reg = A2W_PLLA_CTRL,
408 .frac_reg = A2W_PLLA_FRAC,
409 .ana_reg_base = A2W_PLLA_ANA0,
410 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
411 .lock_mask = CM_LOCK_FLOCKA,
412
413 .ana = &bcm2835_ana_default,
414
415 .min_rate = 600000000u,
416 .max_rate = 2400000000u,
417 .max_fb_rate = BCM2835_MAX_FB_RATE,
418};
419
420/* PLLB is used for the ARM's clock. */
421static const struct bcm2835_pll_data bcm2835_pllb_data = {
422 .name = "pllb",
423 .cm_ctrl_reg = CM_PLLB,
424 .a2w_ctrl_reg = A2W_PLLB_CTRL,
425 .frac_reg = A2W_PLLB_FRAC,
426 .ana_reg_base = A2W_PLLB_ANA0,
427 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
428 .lock_mask = CM_LOCK_FLOCKB,
429
430 .ana = &bcm2835_ana_default,
431
432 .min_rate = 600000000u,
433 .max_rate = 3000000000u,
434 .max_fb_rate = BCM2835_MAX_FB_RATE,
435};
436
437/*
438 * PLLC is the core PLL, used to drive the core VPU clock.
439 *
440 * It is in the PX LDO power domain, which is on when the AUDIO domain
441 * is on.
442*/
443static const struct bcm2835_pll_data bcm2835_pllc_data = {
444 .name = "pllc",
445 .cm_ctrl_reg = CM_PLLC,
446 .a2w_ctrl_reg = A2W_PLLC_CTRL,
447 .frac_reg = A2W_PLLC_FRAC,
448 .ana_reg_base = A2W_PLLC_ANA0,
449 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
450 .lock_mask = CM_LOCK_FLOCKC,
451
452 .ana = &bcm2835_ana_default,
453
454 .min_rate = 600000000u,
455 .max_rate = 3000000000u,
456 .max_fb_rate = BCM2835_MAX_FB_RATE,
457};
458
459/*
460 * PLLD is the display PLL, used to drive DSI display panels.
461 *
462 * It is in the PX LDO power domain, which is on when the AUDIO domain
463 * is on.
464 */
465static const struct bcm2835_pll_data bcm2835_plld_data = {
466 .name = "plld",
467 .cm_ctrl_reg = CM_PLLD,
468 .a2w_ctrl_reg = A2W_PLLD_CTRL,
469 .frac_reg = A2W_PLLD_FRAC,
470 .ana_reg_base = A2W_PLLD_ANA0,
471 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
472 .lock_mask = CM_LOCK_FLOCKD,
473
474 .ana = &bcm2835_ana_default,
475
476 .min_rate = 600000000u,
477 .max_rate = 2400000000u,
478 .max_fb_rate = BCM2835_MAX_FB_RATE,
479};
480
481/*
482 * PLLH is used to supply the pixel clock or the AUX clock for the TV
483 * encoder.
484 *
485 * It is in the HDMI power domain.
486 */
487static const struct bcm2835_pll_data bcm2835_pllh_data = {
488 "pllh",
489 .cm_ctrl_reg = CM_PLLH,
490 .a2w_ctrl_reg = A2W_PLLH_CTRL,
491 .frac_reg = A2W_PLLH_FRAC,
492 .ana_reg_base = A2W_PLLH_ANA0,
493 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
494 .lock_mask = CM_LOCK_FLOCKH,
495
496 .ana = &bcm2835_ana_pllh,
497
498 .min_rate = 600000000u,
499 .max_rate = 3000000000u,
500 .max_fb_rate = BCM2835_MAX_FB_RATE,
501};
502
503struct bcm2835_pll_divider_data { 420struct bcm2835_pll_divider_data {
504 const char *name; 421 const char *name;
505 const struct bcm2835_pll_data *source_pll; 422 const char *source_pll;
423
506 u32 cm_reg; 424 u32 cm_reg;
507 u32 a2w_reg; 425 u32 a2w_reg;
508 426
@@ -511,124 +429,6 @@ struct bcm2835_pll_divider_data {
511 u32 fixed_divider; 429 u32 fixed_divider;
512}; 430};
513 431
514static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
515 .name = "plla_core",
516 .source_pll = &bcm2835_plla_data,
517 .cm_reg = CM_PLLA,
518 .a2w_reg = A2W_PLLA_CORE,
519 .load_mask = CM_PLLA_LOADCORE,
520 .hold_mask = CM_PLLA_HOLDCORE,
521 .fixed_divider = 1,
522};
523
524static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
525 .name = "plla_per",
526 .source_pll = &bcm2835_plla_data,
527 .cm_reg = CM_PLLA,
528 .a2w_reg = A2W_PLLA_PER,
529 .load_mask = CM_PLLA_LOADPER,
530 .hold_mask = CM_PLLA_HOLDPER,
531 .fixed_divider = 1,
532};
533
534static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
535 .name = "pllb_arm",
536 .source_pll = &bcm2835_pllb_data,
537 .cm_reg = CM_PLLB,
538 .a2w_reg = A2W_PLLB_ARM,
539 .load_mask = CM_PLLB_LOADARM,
540 .hold_mask = CM_PLLB_HOLDARM,
541 .fixed_divider = 1,
542};
543
544static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
545 .name = "pllc_core0",
546 .source_pll = &bcm2835_pllc_data,
547 .cm_reg = CM_PLLC,
548 .a2w_reg = A2W_PLLC_CORE0,
549 .load_mask = CM_PLLC_LOADCORE0,
550 .hold_mask = CM_PLLC_HOLDCORE0,
551 .fixed_divider = 1,
552};
553
554static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
555 .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
556 .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
557 .load_mask = CM_PLLC_LOADCORE1,
558 .hold_mask = CM_PLLC_HOLDCORE1,
559 .fixed_divider = 1,
560};
561
562static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
563 .name = "pllc_core2",
564 .source_pll = &bcm2835_pllc_data,
565 .cm_reg = CM_PLLC,
566 .a2w_reg = A2W_PLLC_CORE2,
567 .load_mask = CM_PLLC_LOADCORE2,
568 .hold_mask = CM_PLLC_HOLDCORE2,
569 .fixed_divider = 1,
570};
571
572static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
573 .name = "pllc_per",
574 .source_pll = &bcm2835_pllc_data,
575 .cm_reg = CM_PLLC,
576 .a2w_reg = A2W_PLLC_PER,
577 .load_mask = CM_PLLC_LOADPER,
578 .hold_mask = CM_PLLC_HOLDPER,
579 .fixed_divider = 1,
580};
581
582static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
583 .name = "plld_core",
584 .source_pll = &bcm2835_plld_data,
585 .cm_reg = CM_PLLD,
586 .a2w_reg = A2W_PLLD_CORE,
587 .load_mask = CM_PLLD_LOADCORE,
588 .hold_mask = CM_PLLD_HOLDCORE,
589 .fixed_divider = 1,
590};
591
592static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
593 .name = "plld_per",
594 .source_pll = &bcm2835_plld_data,
595 .cm_reg = CM_PLLD,
596 .a2w_reg = A2W_PLLD_PER,
597 .load_mask = CM_PLLD_LOADPER,
598 .hold_mask = CM_PLLD_HOLDPER,
599 .fixed_divider = 1,
600};
601
602static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
603 .name = "pllh_rcal",
604 .source_pll = &bcm2835_pllh_data,
605 .cm_reg = CM_PLLH,
606 .a2w_reg = A2W_PLLH_RCAL,
607 .load_mask = CM_PLLH_LOADRCAL,
608 .hold_mask = 0,
609 .fixed_divider = 10,
610};
611
612static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
613 .name = "pllh_aux",
614 .source_pll = &bcm2835_pllh_data,
615 .cm_reg = CM_PLLH,
616 .a2w_reg = A2W_PLLH_AUX,
617 .load_mask = CM_PLLH_LOADAUX,
618 .hold_mask = 0,
619 .fixed_divider = 10,
620};
621
622static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
623 .name = "pllh_pix",
624 .source_pll = &bcm2835_pllh_data,
625 .cm_reg = CM_PLLH,
626 .a2w_reg = A2W_PLLH_PIX,
627 .load_mask = CM_PLLH_LOADPIX,
628 .hold_mask = 0,
629 .fixed_divider = 10,
630};
631
632struct bcm2835_clock_data { 432struct bcm2835_clock_data {
633 const char *name; 433 const char *name;
634 434
@@ -644,187 +444,14 @@ struct bcm2835_clock_data {
644 u32 frac_bits; 444 u32 frac_bits;
645 445
646 bool is_vpu_clock; 446 bool is_vpu_clock;
447 bool is_mash_clock;
647}; 448};
648 449
649static const char *const bcm2835_clock_per_parents[] = { 450struct bcm2835_gate_data {
650 "gnd", 451 const char *name;
651 "xosc", 452 const char *parent;
652 "testdebug0",
653 "testdebug1",
654 "plla_per",
655 "pllc_per",
656 "plld_per",
657 "pllh_aux",
658};
659
660static const char *const bcm2835_clock_vpu_parents[] = {
661 "gnd",
662 "xosc",
663 "testdebug0",
664 "testdebug1",
665 "plla_core",
666 "pllc_core0",
667 "plld_core",
668 "pllh_aux",
669 "pllc_core1",
670 "pllc_core2",
671};
672
673static const char *const bcm2835_clock_osc_parents[] = {
674 "gnd",
675 "xosc",
676 "testdebug0",
677 "testdebug1"
678};
679
680/*
681 * Used for a 1Mhz clock for the system clocksource, and also used by
682 * the watchdog timer and the camera pulse generator.
683 */
684static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
685 .name = "timer",
686 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
687 .parents = bcm2835_clock_osc_parents,
688 .ctl_reg = CM_TIMERCTL,
689 .div_reg = CM_TIMERDIV,
690 .int_bits = 6,
691 .frac_bits = 12,
692};
693
694/* One Time Programmable Memory clock. Maximum 10Mhz. */
695static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
696 .name = "otp",
697 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
698 .parents = bcm2835_clock_osc_parents,
699 .ctl_reg = CM_OTPCTL,
700 .div_reg = CM_OTPDIV,
701 .int_bits = 4,
702 .frac_bits = 0,
703};
704
705/*
706 * VPU clock. This doesn't have an enable bit, since it drives the
707 * bus for everything else, and is special so it doesn't need to be
708 * gated for rate changes. It is also known as "clk_audio" in various
709 * hardware documentation.
710 */
711static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
712 .name = "vpu",
713 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
714 .parents = bcm2835_clock_vpu_parents,
715 .ctl_reg = CM_VPUCTL,
716 .div_reg = CM_VPUDIV,
717 .int_bits = 12,
718 .frac_bits = 8,
719 .is_vpu_clock = true,
720};
721
722static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
723 .name = "v3d",
724 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
725 .parents = bcm2835_clock_vpu_parents,
726 .ctl_reg = CM_V3DCTL,
727 .div_reg = CM_V3DDIV,
728 .int_bits = 4,
729 .frac_bits = 8,
730};
731
732static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
733 .name = "isp",
734 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
735 .parents = bcm2835_clock_vpu_parents,
736 .ctl_reg = CM_ISPCTL,
737 .div_reg = CM_ISPDIV,
738 .int_bits = 4,
739 .frac_bits = 8,
740};
741
742static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
743 .name = "h264",
744 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
745 .parents = bcm2835_clock_vpu_parents,
746 .ctl_reg = CM_H264CTL,
747 .div_reg = CM_H264DIV,
748 .int_bits = 4,
749 .frac_bits = 8,
750};
751
752/* TV encoder clock. Only operating frequency is 108Mhz. */
753static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
754 .name = "vec",
755 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
756 .parents = bcm2835_clock_per_parents,
757 .ctl_reg = CM_VECCTL,
758 .div_reg = CM_VECDIV,
759 .int_bits = 4,
760 .frac_bits = 0,
761};
762
763static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
764 .name = "uart",
765 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
766 .parents = bcm2835_clock_per_parents,
767 .ctl_reg = CM_UARTCTL,
768 .div_reg = CM_UARTDIV,
769 .int_bits = 10,
770 .frac_bits = 12,
771};
772
773/* HDMI state machine */
774static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
775 .name = "hsm",
776 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
777 .parents = bcm2835_clock_per_parents,
778 .ctl_reg = CM_HSMCTL,
779 .div_reg = CM_HSMDIV,
780 .int_bits = 4,
781 .frac_bits = 8,
782};
783
784/*
785 * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
786 * the SDRAM controller can't be used.
787 */
788static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
789 .name = "sdram",
790 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
791 .parents = bcm2835_clock_vpu_parents,
792 .ctl_reg = CM_SDCCTL,
793 .div_reg = CM_SDCDIV,
794 .int_bits = 6,
795 .frac_bits = 0,
796};
797
798/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
799static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
800 .name = "tsens",
801 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
802 .parents = bcm2835_clock_osc_parents,
803 .ctl_reg = CM_TSENSCTL,
804 .div_reg = CM_TSENSDIV,
805 .int_bits = 5,
806 .frac_bits = 0,
807};
808
809/* Arasan EMMC clock */
810static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
811 .name = "emmc",
812 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
813 .parents = bcm2835_clock_per_parents,
814 .ctl_reg = CM_EMMCCTL,
815 .div_reg = CM_EMMCDIV,
816 .int_bits = 4,
817 .frac_bits = 8,
818};
819 453
820static const struct bcm2835_clock_data bcm2835_clock_pwm_data = { 454 u32 ctl_reg;
821 .name = "pwm",
822 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
823 .parents = bcm2835_clock_per_parents,
824 .ctl_reg = CM_PWMCTL,
825 .div_reg = CM_PWMDIV,
826 .int_bits = 12,
827 .frac_bits = 12,
828}; 455};
829 456
830struct bcm2835_pll { 457struct bcm2835_pll {
@@ -910,8 +537,14 @@ static void bcm2835_pll_off(struct clk_hw *hw)
910 struct bcm2835_cprman *cprman = pll->cprman; 537 struct bcm2835_cprman *cprman = pll->cprman;
911 const struct bcm2835_pll_data *data = pll->data; 538 const struct bcm2835_pll_data *data = pll->data;
912 539
913 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); 540 spin_lock(&cprman->regs_lock);
914 cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); 541 cprman_write(cprman, data->cm_ctrl_reg,
542 cprman_read(cprman, data->cm_ctrl_reg) |
543 CM_PLL_ANARST);
544 cprman_write(cprman, data->a2w_ctrl_reg,
545 cprman_read(cprman, data->a2w_ctrl_reg) |
546 A2W_PLL_CTRL_PWRDN);
547 spin_unlock(&cprman->regs_lock);
915} 548}
916 549
917static int bcm2835_pll_on(struct clk_hw *hw) 550static int bcm2835_pll_on(struct clk_hw *hw)
@@ -1030,6 +663,36 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
1030 return 0; 663 return 0;
1031} 664}
1032 665
666static int bcm2835_pll_debug_init(struct clk_hw *hw,
667 struct dentry *dentry)
668{
669 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
670 struct bcm2835_cprman *cprman = pll->cprman;
671 const struct bcm2835_pll_data *data = pll->data;
672 struct debugfs_reg32 *regs;
673
674 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
675 if (!regs)
676 return -ENOMEM;
677
678 regs[0].name = "cm_ctrl";
679 regs[0].offset = data->cm_ctrl_reg;
680 regs[1].name = "a2w_ctrl";
681 regs[1].offset = data->a2w_ctrl_reg;
682 regs[2].name = "frac";
683 regs[2].offset = data->frac_reg;
684 regs[3].name = "ana0";
685 regs[3].offset = data->ana_reg_base + 0 * 4;
686 regs[4].name = "ana1";
687 regs[4].offset = data->ana_reg_base + 1 * 4;
688 regs[5].name = "ana2";
689 regs[5].offset = data->ana_reg_base + 2 * 4;
690 regs[6].name = "ana3";
691 regs[6].offset = data->ana_reg_base + 3 * 4;
692
693 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
694}
695
1033static const struct clk_ops bcm2835_pll_clk_ops = { 696static const struct clk_ops bcm2835_pll_clk_ops = {
1034 .is_prepared = bcm2835_pll_is_on, 697 .is_prepared = bcm2835_pll_is_on,
1035 .prepare = bcm2835_pll_on, 698 .prepare = bcm2835_pll_on,
@@ -1037,6 +700,7 @@ static const struct clk_ops bcm2835_pll_clk_ops = {
1037 .recalc_rate = bcm2835_pll_get_rate, 700 .recalc_rate = bcm2835_pll_get_rate,
1038 .set_rate = bcm2835_pll_set_rate, 701 .set_rate = bcm2835_pll_set_rate,
1039 .round_rate = bcm2835_pll_round_rate, 702 .round_rate = bcm2835_pll_round_rate,
703 .debug_init = bcm2835_pll_debug_init,
1040}; 704};
1041 705
1042struct bcm2835_pll_divider { 706struct bcm2835_pll_divider {
@@ -1079,10 +743,12 @@ static void bcm2835_pll_divider_off(struct clk_hw *hw)
1079 struct bcm2835_cprman *cprman = divider->cprman; 743 struct bcm2835_cprman *cprman = divider->cprman;
1080 const struct bcm2835_pll_divider_data *data = divider->data; 744 const struct bcm2835_pll_divider_data *data = divider->data;
1081 745
746 spin_lock(&cprman->regs_lock);
1082 cprman_write(cprman, data->cm_reg, 747 cprman_write(cprman, data->cm_reg,
1083 (cprman_read(cprman, data->cm_reg) & 748 (cprman_read(cprman, data->cm_reg) &
1084 ~data->load_mask) | data->hold_mask); 749 ~data->load_mask) | data->hold_mask);
1085 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE); 750 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
751 spin_unlock(&cprman->regs_lock);
1086} 752}
1087 753
1088static int bcm2835_pll_divider_on(struct clk_hw *hw) 754static int bcm2835_pll_divider_on(struct clk_hw *hw)
@@ -1091,12 +757,14 @@ static int bcm2835_pll_divider_on(struct clk_hw *hw)
1091 struct bcm2835_cprman *cprman = divider->cprman; 757 struct bcm2835_cprman *cprman = divider->cprman;
1092 const struct bcm2835_pll_divider_data *data = divider->data; 758 const struct bcm2835_pll_divider_data *data = divider->data;
1093 759
760 spin_lock(&cprman->regs_lock);
1094 cprman_write(cprman, data->a2w_reg, 761 cprman_write(cprman, data->a2w_reg,
1095 cprman_read(cprman, data->a2w_reg) & 762 cprman_read(cprman, data->a2w_reg) &
1096 ~A2W_PLL_CHANNEL_DISABLE); 763 ~A2W_PLL_CHANNEL_DISABLE);
1097 764
1098 cprman_write(cprman, data->cm_reg, 765 cprman_write(cprman, data->cm_reg,
1099 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 766 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
767 spin_unlock(&cprman->regs_lock);
1100 768
1101 return 0; 769 return 0;
1102} 770}
@@ -1124,6 +792,26 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
1124 return 0; 792 return 0;
1125} 793}
1126 794
795static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
796 struct dentry *dentry)
797{
798 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
799 struct bcm2835_cprman *cprman = divider->cprman;
800 const struct bcm2835_pll_divider_data *data = divider->data;
801 struct debugfs_reg32 *regs;
802
803 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
804 if (!regs)
805 return -ENOMEM;
806
807 regs[0].name = "cm";
808 regs[0].offset = data->cm_reg;
809 regs[1].name = "a2w";
810 regs[1].offset = data->a2w_reg;
811
812 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
813}
814
1127static const struct clk_ops bcm2835_pll_divider_clk_ops = { 815static const struct clk_ops bcm2835_pll_divider_clk_ops = {
1128 .is_prepared = bcm2835_pll_divider_is_on, 816 .is_prepared = bcm2835_pll_divider_is_on,
1129 .prepare = bcm2835_pll_divider_on, 817 .prepare = bcm2835_pll_divider_on,
@@ -1131,6 +819,7 @@ static const struct clk_ops bcm2835_pll_divider_clk_ops = {
1131 .recalc_rate = bcm2835_pll_divider_get_rate, 819 .recalc_rate = bcm2835_pll_divider_get_rate,
1132 .set_rate = bcm2835_pll_divider_set_rate, 820 .set_rate = bcm2835_pll_divider_set_rate,
1133 .round_rate = bcm2835_pll_divider_round_rate, 821 .round_rate = bcm2835_pll_divider_round_rate,
822 .debug_init = bcm2835_pll_divider_debug_init,
1134}; 823};
1135 824
1136/* 825/*
@@ -1170,7 +859,7 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
1170 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 859 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
1171 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 860 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
1172 u64 rem; 861 u64 rem;
1173 u32 div; 862 u32 div, mindiv, maxdiv;
1174 863
1175 rem = do_div(temp, rate); 864 rem = do_div(temp, rate);
1176 div = temp; 865 div = temp;
@@ -1180,10 +869,23 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
1180 div += unused_frac_mask + 1; 869 div += unused_frac_mask + 1;
1181 div &= ~unused_frac_mask; 870 div &= ~unused_frac_mask;
1182 871
1183 /* Clamp to the limits. */ 872 /* different clamping limits apply for a mash clock */
1184 div = max(div, unused_frac_mask + 1); 873 if (data->is_mash_clock) {
1185 div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 874 /* clamp to min divider of 2 */
1186 CM_DIV_FRAC_BITS - data->frac_bits)); 875 mindiv = 2 << CM_DIV_FRAC_BITS;
876 /* clamp to the highest possible integer divider */
877 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
878 } else {
879 /* clamp to min divider of 1 */
880 mindiv = 1 << CM_DIV_FRAC_BITS;
881 /* clamp to the highest possible fractional divider */
882 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
883 CM_DIV_FRAC_BITS - data->frac_bits);
884 }
885
886 /* apply the clamping limits */
887 div = max_t(u32, div, mindiv);
888 div = min_t(u32, div, maxdiv);
1187 889
1188 return div; 890 return div;
1189} 891}
@@ -1277,14 +979,31 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
1277 struct bcm2835_cprman *cprman = clock->cprman; 979 struct bcm2835_cprman *cprman = clock->cprman;
1278 const struct bcm2835_clock_data *data = clock->data; 980 const struct bcm2835_clock_data *data = clock->data;
1279 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 981 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
982 u32 ctl;
983
984 spin_lock(&cprman->regs_lock);
985
986 /*
987 * Setting up frac support
988 *
989 * In principle it is recommended to stop/start the clock first,
990 * but as we set CLK_SET_RATE_GATE during registration of the
991 * clock this requirement should be take care of by the
992 * clk-framework.
993 */
994 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
995 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
996 cprman_write(cprman, data->ctl_reg, ctl);
1280 997
1281 cprman_write(cprman, data->div_reg, div); 998 cprman_write(cprman, data->div_reg, div);
1282 999
1000 spin_unlock(&cprman->regs_lock);
1001
1283 return 0; 1002 return 0;
1284} 1003}
1285 1004
1286static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1005static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1287 struct clk_rate_request *req) 1006 struct clk_rate_request *req)
1288{ 1007{
1289 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1008 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1290 struct clk_hw *parent, *best_parent = NULL; 1009 struct clk_hw *parent, *best_parent = NULL;
@@ -1342,6 +1061,30 @@ static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1342 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1061 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1343} 1062}
1344 1063
1064static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1065 {
1066 .name = "ctl",
1067 .offset = 0,
1068 },
1069 {
1070 .name = "div",
1071 .offset = 4,
1072 },
1073};
1074
1075static int bcm2835_clock_debug_init(struct clk_hw *hw,
1076 struct dentry *dentry)
1077{
1078 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1079 struct bcm2835_cprman *cprman = clock->cprman;
1080 const struct bcm2835_clock_data *data = clock->data;
1081
1082 return bcm2835_debugfs_regset(
1083 cprman, data->ctl_reg,
1084 bcm2835_debugfs_clock_reg32,
1085 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1086 dentry);
1087}
1345 1088
1346static const struct clk_ops bcm2835_clock_clk_ops = { 1089static const struct clk_ops bcm2835_clock_clk_ops = {
1347 .is_prepared = bcm2835_clock_is_on, 1090 .is_prepared = bcm2835_clock_is_on,
@@ -1352,6 +1095,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = {
1352 .determine_rate = bcm2835_clock_determine_rate, 1095 .determine_rate = bcm2835_clock_determine_rate,
1353 .set_parent = bcm2835_clock_set_parent, 1096 .set_parent = bcm2835_clock_set_parent,
1354 .get_parent = bcm2835_clock_get_parent, 1097 .get_parent = bcm2835_clock_get_parent,
1098 .debug_init = bcm2835_clock_debug_init,
1355}; 1099};
1356 1100
1357static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1101static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
@@ -1370,6 +1114,7 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1370 .determine_rate = bcm2835_clock_determine_rate, 1114 .determine_rate = bcm2835_clock_determine_rate,
1371 .set_parent = bcm2835_clock_set_parent, 1115 .set_parent = bcm2835_clock_set_parent,
1372 .get_parent = bcm2835_clock_get_parent, 1116 .get_parent = bcm2835_clock_get_parent,
1117 .debug_init = bcm2835_clock_debug_init,
1373}; 1118};
1374 1119
1375static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1120static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
@@ -1418,7 +1163,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1418 1163
1419 memset(&init, 0, sizeof(init)); 1164 memset(&init, 0, sizeof(init));
1420 1165
1421 init.parent_names = &data->source_pll->name; 1166 init.parent_names = &data->source_pll;
1422 init.num_parents = 1; 1167 init.num_parents = 1;
1423 init.name = divider_name; 1168 init.name = divider_name;
1424 init.ops = &bcm2835_pll_divider_clk_ops; 1169 init.ops = &bcm2835_pll_divider_clk_ops;
@@ -1501,14 +1246,559 @@ static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1501 return devm_clk_register(cprman->dev, &clock->hw); 1246 return devm_clk_register(cprman->dev, &clock->hw);
1502} 1247}
1503 1248
1249static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1250 const struct bcm2835_gate_data *data)
1251{
1252 return clk_register_gate(cprman->dev, data->name, data->parent,
1253 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1254 cprman->regs + data->ctl_reg,
1255 CM_GATE_BIT, 0, &cprman->regs_lock);
1256}
1257
1258typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1259 const void *data);
1260struct bcm2835_clk_desc {
1261 bcm2835_clk_register clk_register;
1262 const void *data;
1263};
1264
1265/* assignment helper macros for different clock types */
1266#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1267 .data = __VA_ARGS__ }
1268#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1269 &(struct bcm2835_pll_data) \
1270 {__VA_ARGS__})
1271#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1272 &(struct bcm2835_pll_divider_data) \
1273 {__VA_ARGS__})
1274#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1275 &(struct bcm2835_clock_data) \
1276 {__VA_ARGS__})
1277#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1278 &(struct bcm2835_gate_data) \
1279 {__VA_ARGS__})
1280
1281/* parent mux arrays plus helper macros */
1282
1283/* main oscillator parent mux */
1284static const char *const bcm2835_clock_osc_parents[] = {
1285 "gnd",
1286 "xosc",
1287 "testdebug0",
1288 "testdebug1"
1289};
1290
1291#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1292 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1293 .parents = bcm2835_clock_osc_parents, \
1294 __VA_ARGS__)
1295
1296/* main peripherial parent mux */
1297static const char *const bcm2835_clock_per_parents[] = {
1298 "gnd",
1299 "xosc",
1300 "testdebug0",
1301 "testdebug1",
1302 "plla_per",
1303 "pllc_per",
1304 "plld_per",
1305 "pllh_aux",
1306};
1307
1308#define REGISTER_PER_CLK(...) REGISTER_CLK( \
1309 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1310 .parents = bcm2835_clock_per_parents, \
1311 __VA_ARGS__)
1312
1313/* main vpu parent mux */
1314static const char *const bcm2835_clock_vpu_parents[] = {
1315 "gnd",
1316 "xosc",
1317 "testdebug0",
1318 "testdebug1",
1319 "plla_core",
1320 "pllc_core0",
1321 "plld_core",
1322 "pllh_aux",
1323 "pllc_core1",
1324 "pllc_core2",
1325};
1326
1327#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1328 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1329 .parents = bcm2835_clock_vpu_parents, \
1330 __VA_ARGS__)
1331
1332/*
1333 * the real definition of all the pll, pll_dividers and clocks
1334 * these make use of the above REGISTER_* macros
1335 */
1336static const struct bcm2835_clk_desc clk_desc_array[] = {
1337 /* the PLL + PLL dividers */
1338
1339 /*
1340 * PLLA is the auxiliary PLL, used to drive the CCP2
1341 * (Compact Camera Port 2) transmitter clock.
1342 *
1343 * It is in the PX LDO power domain, which is on when the
1344 * AUDIO domain is on.
1345 */
1346 [BCM2835_PLLA] = REGISTER_PLL(
1347 .name = "plla",
1348 .cm_ctrl_reg = CM_PLLA,
1349 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1350 .frac_reg = A2W_PLLA_FRAC,
1351 .ana_reg_base = A2W_PLLA_ANA0,
1352 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1353 .lock_mask = CM_LOCK_FLOCKA,
1354
1355 .ana = &bcm2835_ana_default,
1356
1357 .min_rate = 600000000u,
1358 .max_rate = 2400000000u,
1359 .max_fb_rate = BCM2835_MAX_FB_RATE),
1360 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1361 .name = "plla_core",
1362 .source_pll = "plla",
1363 .cm_reg = CM_PLLA,
1364 .a2w_reg = A2W_PLLA_CORE,
1365 .load_mask = CM_PLLA_LOADCORE,
1366 .hold_mask = CM_PLLA_HOLDCORE,
1367 .fixed_divider = 1),
1368 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1369 .name = "plla_per",
1370 .source_pll = "plla",
1371 .cm_reg = CM_PLLA,
1372 .a2w_reg = A2W_PLLA_PER,
1373 .load_mask = CM_PLLA_LOADPER,
1374 .hold_mask = CM_PLLA_HOLDPER,
1375 .fixed_divider = 1),
1376 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1377 .name = "plla_dsi0",
1378 .source_pll = "plla",
1379 .cm_reg = CM_PLLA,
1380 .a2w_reg = A2W_PLLA_DSI0,
1381 .load_mask = CM_PLLA_LOADDSI0,
1382 .hold_mask = CM_PLLA_HOLDDSI0,
1383 .fixed_divider = 1),
1384 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1385 .name = "plla_ccp2",
1386 .source_pll = "plla",
1387 .cm_reg = CM_PLLA,
1388 .a2w_reg = A2W_PLLA_CCP2,
1389 .load_mask = CM_PLLA_LOADCCP2,
1390 .hold_mask = CM_PLLA_HOLDCCP2,
1391 .fixed_divider = 1),
1392
1393 /* PLLB is used for the ARM's clock. */
1394 [BCM2835_PLLB] = REGISTER_PLL(
1395 .name = "pllb",
1396 .cm_ctrl_reg = CM_PLLB,
1397 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1398 .frac_reg = A2W_PLLB_FRAC,
1399 .ana_reg_base = A2W_PLLB_ANA0,
1400 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1401 .lock_mask = CM_LOCK_FLOCKB,
1402
1403 .ana = &bcm2835_ana_default,
1404
1405 .min_rate = 600000000u,
1406 .max_rate = 3000000000u,
1407 .max_fb_rate = BCM2835_MAX_FB_RATE),
1408 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1409 .name = "pllb_arm",
1410 .source_pll = "pllb",
1411 .cm_reg = CM_PLLB,
1412 .a2w_reg = A2W_PLLB_ARM,
1413 .load_mask = CM_PLLB_LOADARM,
1414 .hold_mask = CM_PLLB_HOLDARM,
1415 .fixed_divider = 1),
1416
1417 /*
1418 * PLLC is the core PLL, used to drive the core VPU clock.
1419 *
1420 * It is in the PX LDO power domain, which is on when the
1421 * AUDIO domain is on.
1422 */
1423 [BCM2835_PLLC] = REGISTER_PLL(
1424 .name = "pllc",
1425 .cm_ctrl_reg = CM_PLLC,
1426 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1427 .frac_reg = A2W_PLLC_FRAC,
1428 .ana_reg_base = A2W_PLLC_ANA0,
1429 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1430 .lock_mask = CM_LOCK_FLOCKC,
1431
1432 .ana = &bcm2835_ana_default,
1433
1434 .min_rate = 600000000u,
1435 .max_rate = 3000000000u,
1436 .max_fb_rate = BCM2835_MAX_FB_RATE),
1437 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1438 .name = "pllc_core0",
1439 .source_pll = "pllc",
1440 .cm_reg = CM_PLLC,
1441 .a2w_reg = A2W_PLLC_CORE0,
1442 .load_mask = CM_PLLC_LOADCORE0,
1443 .hold_mask = CM_PLLC_HOLDCORE0,
1444 .fixed_divider = 1),
1445 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1446 .name = "pllc_core1",
1447 .source_pll = "pllc",
1448 .cm_reg = CM_PLLC,
1449 .a2w_reg = A2W_PLLC_CORE1,
1450 .load_mask = CM_PLLC_LOADCORE1,
1451 .hold_mask = CM_PLLC_HOLDCORE1,
1452 .fixed_divider = 1),
1453 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1454 .name = "pllc_core2",
1455 .source_pll = "pllc",
1456 .cm_reg = CM_PLLC,
1457 .a2w_reg = A2W_PLLC_CORE2,
1458 .load_mask = CM_PLLC_LOADCORE2,
1459 .hold_mask = CM_PLLC_HOLDCORE2,
1460 .fixed_divider = 1),
1461 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1462 .name = "pllc_per",
1463 .source_pll = "pllc",
1464 .cm_reg = CM_PLLC,
1465 .a2w_reg = A2W_PLLC_PER,
1466 .load_mask = CM_PLLC_LOADPER,
1467 .hold_mask = CM_PLLC_HOLDPER,
1468 .fixed_divider = 1),
1469
1470 /*
1471 * PLLD is the display PLL, used to drive DSI display panels.
1472 *
1473 * It is in the PX LDO power domain, which is on when the
1474 * AUDIO domain is on.
1475 */
1476 [BCM2835_PLLD] = REGISTER_PLL(
1477 .name = "plld",
1478 .cm_ctrl_reg = CM_PLLD,
1479 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1480 .frac_reg = A2W_PLLD_FRAC,
1481 .ana_reg_base = A2W_PLLD_ANA0,
1482 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1483 .lock_mask = CM_LOCK_FLOCKD,
1484
1485 .ana = &bcm2835_ana_default,
1486
1487 .min_rate = 600000000u,
1488 .max_rate = 2400000000u,
1489 .max_fb_rate = BCM2835_MAX_FB_RATE),
1490 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1491 .name = "plld_core",
1492 .source_pll = "plld",
1493 .cm_reg = CM_PLLD,
1494 .a2w_reg = A2W_PLLD_CORE,
1495 .load_mask = CM_PLLD_LOADCORE,
1496 .hold_mask = CM_PLLD_HOLDCORE,
1497 .fixed_divider = 1),
1498 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1499 .name = "plld_per",
1500 .source_pll = "plld",
1501 .cm_reg = CM_PLLD,
1502 .a2w_reg = A2W_PLLD_PER,
1503 .load_mask = CM_PLLD_LOADPER,
1504 .hold_mask = CM_PLLD_HOLDPER,
1505 .fixed_divider = 1),
1506 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1507 .name = "plld_dsi0",
1508 .source_pll = "plld",
1509 .cm_reg = CM_PLLD,
1510 .a2w_reg = A2W_PLLD_DSI0,
1511 .load_mask = CM_PLLD_LOADDSI0,
1512 .hold_mask = CM_PLLD_HOLDDSI0,
1513 .fixed_divider = 1),
1514 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1515 .name = "plld_dsi1",
1516 .source_pll = "plld",
1517 .cm_reg = CM_PLLD,
1518 .a2w_reg = A2W_PLLD_DSI1,
1519 .load_mask = CM_PLLD_LOADDSI1,
1520 .hold_mask = CM_PLLD_HOLDDSI1,
1521 .fixed_divider = 1),
1522
1523 /*
1524 * PLLH is used to supply the pixel clock or the AUX clock for the
1525 * TV encoder.
1526 *
1527 * It is in the HDMI power domain.
1528 */
1529 [BCM2835_PLLH] = REGISTER_PLL(
1530 "pllh",
1531 .cm_ctrl_reg = CM_PLLH,
1532 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1533 .frac_reg = A2W_PLLH_FRAC,
1534 .ana_reg_base = A2W_PLLH_ANA0,
1535 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1536 .lock_mask = CM_LOCK_FLOCKH,
1537
1538 .ana = &bcm2835_ana_pllh,
1539
1540 .min_rate = 600000000u,
1541 .max_rate = 3000000000u,
1542 .max_fb_rate = BCM2835_MAX_FB_RATE),
1543 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1544 .name = "pllh_rcal",
1545 .source_pll = "pllh",
1546 .cm_reg = CM_PLLH,
1547 .a2w_reg = A2W_PLLH_RCAL,
1548 .load_mask = CM_PLLH_LOADRCAL,
1549 .hold_mask = 0,
1550 .fixed_divider = 10),
1551 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1552 .name = "pllh_aux",
1553 .source_pll = "pllh",
1554 .cm_reg = CM_PLLH,
1555 .a2w_reg = A2W_PLLH_AUX,
1556 .load_mask = CM_PLLH_LOADAUX,
1557 .hold_mask = 0,
1558 .fixed_divider = 10),
1559 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1560 .name = "pllh_pix",
1561 .source_pll = "pllh",
1562 .cm_reg = CM_PLLH,
1563 .a2w_reg = A2W_PLLH_PIX,
1564 .load_mask = CM_PLLH_LOADPIX,
1565 .hold_mask = 0,
1566 .fixed_divider = 10),
1567
1568 /* the clocks */
1569
1570 /* clocks with oscillator parent mux */
1571
1572 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1573 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1574 .name = "otp",
1575 .ctl_reg = CM_OTPCTL,
1576 .div_reg = CM_OTPDIV,
1577 .int_bits = 4,
1578 .frac_bits = 0),
1579 /*
1580 * Used for a 1Mhz clock for the system clocksource, and also used
1581 * bythe watchdog timer and the camera pulse generator.
1582 */
1583 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1584 .name = "timer",
1585 .ctl_reg = CM_TIMERCTL,
1586 .div_reg = CM_TIMERDIV,
1587 .int_bits = 6,
1588 .frac_bits = 12),
1589 /*
1590 * Clock for the temperature sensor.
1591 * Generally run at 2Mhz, max 5Mhz.
1592 */
1593 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1594 .name = "tsens",
1595 .ctl_reg = CM_TSENSCTL,
1596 .div_reg = CM_TSENSDIV,
1597 .int_bits = 5,
1598 .frac_bits = 0),
1599 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1600 .name = "tec",
1601 .ctl_reg = CM_TECCTL,
1602 .div_reg = CM_TECDIV,
1603 .int_bits = 6,
1604 .frac_bits = 0),
1605
1606 /* clocks with vpu parent mux */
1607 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1608 .name = "h264",
1609 .ctl_reg = CM_H264CTL,
1610 .div_reg = CM_H264DIV,
1611 .int_bits = 4,
1612 .frac_bits = 8),
1613 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1614 .name = "isp",
1615 .ctl_reg = CM_ISPCTL,
1616 .div_reg = CM_ISPDIV,
1617 .int_bits = 4,
1618 .frac_bits = 8),
1619
1620 /*
1621 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1622 * in the SDRAM controller can't be used.
1623 */
1624 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1625 .name = "sdram",
1626 .ctl_reg = CM_SDCCTL,
1627 .div_reg = CM_SDCDIV,
1628 .int_bits = 6,
1629 .frac_bits = 0),
1630 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1631 .name = "v3d",
1632 .ctl_reg = CM_V3DCTL,
1633 .div_reg = CM_V3DDIV,
1634 .int_bits = 4,
1635 .frac_bits = 8),
1636 /*
1637 * VPU clock. This doesn't have an enable bit, since it drives
1638 * the bus for everything else, and is special so it doesn't need
1639 * to be gated for rate changes. It is also known as "clk_audio"
1640 * in various hardware documentation.
1641 */
1642 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1643 .name = "vpu",
1644 .ctl_reg = CM_VPUCTL,
1645 .div_reg = CM_VPUDIV,
1646 .int_bits = 12,
1647 .frac_bits = 8,
1648 .is_vpu_clock = true),
1649
1650 /* clocks with per parent mux */
1651 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1652 .name = "aveo",
1653 .ctl_reg = CM_AVEOCTL,
1654 .div_reg = CM_AVEODIV,
1655 .int_bits = 4,
1656 .frac_bits = 0),
1657 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1658 .name = "cam0",
1659 .ctl_reg = CM_CAM0CTL,
1660 .div_reg = CM_CAM0DIV,
1661 .int_bits = 4,
1662 .frac_bits = 8),
1663 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1664 .name = "cam1",
1665 .ctl_reg = CM_CAM1CTL,
1666 .div_reg = CM_CAM1DIV,
1667 .int_bits = 4,
1668 .frac_bits = 8),
1669 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1670 .name = "dft",
1671 .ctl_reg = CM_DFTCTL,
1672 .div_reg = CM_DFTDIV,
1673 .int_bits = 5,
1674 .frac_bits = 0),
1675 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
1676 .name = "dpi",
1677 .ctl_reg = CM_DPICTL,
1678 .div_reg = CM_DPIDIV,
1679 .int_bits = 4,
1680 .frac_bits = 8),
1681
1682 /* Arasan EMMC clock */
1683 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
1684 .name = "emmc",
1685 .ctl_reg = CM_EMMCCTL,
1686 .div_reg = CM_EMMCDIV,
1687 .int_bits = 4,
1688 .frac_bits = 8),
1689
1690 /* General purpose (GPIO) clocks */
1691 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
1692 .name = "gp0",
1693 .ctl_reg = CM_GP0CTL,
1694 .div_reg = CM_GP0DIV,
1695 .int_bits = 12,
1696 .frac_bits = 12,
1697 .is_mash_clock = true),
1698 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
1699 .name = "gp1",
1700 .ctl_reg = CM_GP1CTL,
1701 .div_reg = CM_GP1DIV,
1702 .int_bits = 12,
1703 .frac_bits = 12,
1704 .is_mash_clock = true),
1705 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
1706 .name = "gp2",
1707 .ctl_reg = CM_GP2CTL,
1708 .div_reg = CM_GP2DIV,
1709 .int_bits = 12,
1710 .frac_bits = 12),
1711
1712 /* HDMI state machine */
1713 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
1714 .name = "hsm",
1715 .ctl_reg = CM_HSMCTL,
1716 .div_reg = CM_HSMDIV,
1717 .int_bits = 4,
1718 .frac_bits = 8),
1719 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK(
1720 .name = "pcm",
1721 .ctl_reg = CM_PCMCTL,
1722 .div_reg = CM_PCMDIV,
1723 .int_bits = 12,
1724 .frac_bits = 12,
1725 .is_mash_clock = true),
1726 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
1727 .name = "pwm",
1728 .ctl_reg = CM_PWMCTL,
1729 .div_reg = CM_PWMDIV,
1730 .int_bits = 12,
1731 .frac_bits = 12,
1732 .is_mash_clock = true),
1733 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
1734 .name = "slim",
1735 .ctl_reg = CM_SLIMCTL,
1736 .div_reg = CM_SLIMDIV,
1737 .int_bits = 12,
1738 .frac_bits = 12,
1739 .is_mash_clock = true),
1740 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
1741 .name = "smi",
1742 .ctl_reg = CM_SMICTL,
1743 .div_reg = CM_SMIDIV,
1744 .int_bits = 4,
1745 .frac_bits = 8),
1746 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
1747 .name = "uart",
1748 .ctl_reg = CM_UARTCTL,
1749 .div_reg = CM_UARTDIV,
1750 .int_bits = 10,
1751 .frac_bits = 12),
1752
1753 /* TV encoder clock. Only operating frequency is 108Mhz. */
1754 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
1755 .name = "vec",
1756 .ctl_reg = CM_VECCTL,
1757 .div_reg = CM_VECDIV,
1758 .int_bits = 4,
1759 .frac_bits = 0),
1760
1761 /* dsi clocks */
1762 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
1763 .name = "dsi0e",
1764 .ctl_reg = CM_DSI0ECTL,
1765 .div_reg = CM_DSI0EDIV,
1766 .int_bits = 4,
1767 .frac_bits = 8),
1768 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
1769 .name = "dsi1e",
1770 .ctl_reg = CM_DSI1ECTL,
1771 .div_reg = CM_DSI1EDIV,
1772 .int_bits = 4,
1773 .frac_bits = 8),
1774
1775 /* the gates */
1776
1777 /*
1778 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1779 * you have the debug bit set in the power manager, which we
1780 * don't bother exposing) are individual gates off of the
1781 * non-stop vpu clock.
1782 */
1783 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
1784 .name = "peri_image",
1785 .parent = "vpu",
1786 .ctl_reg = CM_PERIICTL),
1787};
1788
1504static int bcm2835_clk_probe(struct platform_device *pdev) 1789static int bcm2835_clk_probe(struct platform_device *pdev)
1505{ 1790{
1506 struct device *dev = &pdev->dev; 1791 struct device *dev = &pdev->dev;
1507 struct clk **clks; 1792 struct clk **clks;
1508 struct bcm2835_cprman *cprman; 1793 struct bcm2835_cprman *cprman;
1509 struct resource *res; 1794 struct resource *res;
1795 const struct bcm2835_clk_desc *desc;
1796 const size_t asize = ARRAY_SIZE(clk_desc_array);
1797 size_t i;
1510 1798
1511 cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL); 1799 cprman = devm_kzalloc(dev,
1800 sizeof(*cprman) + asize * sizeof(*clks),
1801 GFP_KERNEL);
1512 if (!cprman) 1802 if (!cprman)
1513 return -ENOMEM; 1803 return -ENOMEM;
1514 1804
@@ -1525,80 +1815,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
1525 1815
1526 platform_set_drvdata(pdev, cprman); 1816 platform_set_drvdata(pdev, cprman);
1527 1817
1528 cprman->onecell.clk_num = BCM2835_CLOCK_COUNT; 1818 cprman->onecell.clk_num = asize;
1529 cprman->onecell.clks = cprman->clks; 1819 cprman->onecell.clks = cprman->clks;
1530 clks = cprman->clks; 1820 clks = cprman->clks;
1531 1821
1532 clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data); 1822 for (i = 0; i < asize; i++) {
1533 clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data); 1823 desc = &clk_desc_array[i];
1534 clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data); 1824 if (desc->clk_register && desc->data)
1535 clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data); 1825 clks[i] = desc->clk_register(cprman, desc->data);
1536 clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data); 1826 }
1537
1538 clks[BCM2835_PLLA_CORE] =
1539 bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
1540 clks[BCM2835_PLLA_PER] =
1541 bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
1542 clks[BCM2835_PLLC_CORE0] =
1543 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
1544 clks[BCM2835_PLLC_CORE1] =
1545 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
1546 clks[BCM2835_PLLC_CORE2] =
1547 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
1548 clks[BCM2835_PLLC_PER] =
1549 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
1550 clks[BCM2835_PLLD_CORE] =
1551 bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
1552 clks[BCM2835_PLLD_PER] =
1553 bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
1554 clks[BCM2835_PLLH_RCAL] =
1555 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
1556 clks[BCM2835_PLLH_AUX] =
1557 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
1558 clks[BCM2835_PLLH_PIX] =
1559 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
1560
1561 clks[BCM2835_CLOCK_TIMER] =
1562 bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
1563 clks[BCM2835_CLOCK_OTP] =
1564 bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
1565 clks[BCM2835_CLOCK_TSENS] =
1566 bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
1567 clks[BCM2835_CLOCK_VPU] =
1568 bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
1569 clks[BCM2835_CLOCK_V3D] =
1570 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1571 clks[BCM2835_CLOCK_ISP] =
1572 bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
1573 clks[BCM2835_CLOCK_H264] =
1574 bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
1575 clks[BCM2835_CLOCK_V3D] =
1576 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1577 clks[BCM2835_CLOCK_SDRAM] =
1578 bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
1579 clks[BCM2835_CLOCK_UART] =
1580 bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
1581 clks[BCM2835_CLOCK_VEC] =
1582 bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
1583 clks[BCM2835_CLOCK_HSM] =
1584 bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
1585 clks[BCM2835_CLOCK_EMMC] =
1586 bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
1587
1588 /*
1589 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1590 * you have the debug bit set in the power manager, which we
1591 * don't bother exposing) are individual gates off of the
1592 * non-stop vpu clock.
1593 */
1594 clks[BCM2835_CLOCK_PERI_IMAGE] =
1595 clk_register_gate(dev, "peri_image", "vpu",
1596 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1597 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1598 0, &cprman->regs_lock);
1599
1600 clks[BCM2835_CLOCK_PWM] =
1601 bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
1602 1827
1603 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, 1828 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1604 &cprman->onecell); 1829 &cprman->onecell);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 23:03:34 -0400