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authorArnd Bergmann <arnd@arndb.de>2016-09-19 11:49:07 -0400
committerArnd Bergmann <arnd@arndb.de>2016-09-19 11:49:07 -0400
commit53570cbc189257d2e95c79e6baa9e12b0a3b3cdf (patch)
tree2f7a1a02ac46c6ecd9df793979c71456bbbbd04c /drivers/clk
parentbac6dd36e355d5b1f089ed507b6579938e4c07c1 (diff)
parentdfdd7d4af6ebee027be7bf2636b2314937948da6 (diff)
Merge tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late
Pull "Amlogic driver updates for v4.9, 2nd round" from Kevin Hilman: - media: update IR support for newer SoCs - firmware: add secure monitor driver - net: new stmmac glue driver - usb: udd DWC2 support for meson-gxbb - clocks: expose more clock IDs for use by DT - DT binding updates * tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (21 commits) clk: gxbb: expose i2c clocks clk: gxbb: expose USB clocks clk: gxbb: expose spifc clock clk: gxbb: expose MPLL2 clock for use by DT Documentation: dt-bindings: Add documentation for the Meson USB2 PHYs usb: dwc2: add support for Meson8b and GXBB SoCs net: stmmac: update the module description of the dwmac-meson driver net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC stmmac: introduce get_stmmac_bsp_priv() helper net: dt-bindings: Document the new Meson8b and GXBB DWMAC bindings clk: meson-gxbb: Export PWM related clocks for DT meson: clk: Add support for clock gates gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b clk: meson: Copy meson8b CLKID defines to private header file meson: clk: Rename register names according to Amlogic datasheet meson: clk: Move register definitions to meson8b.h clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention nvmem: amlogic: Add Amlogic Meson EFUSE driver firmware: Amlogic: Add secure monitor driver media: rc: meson-ir: Add support for newer versions of the IR decoder ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/meson/Makefile2
-rw-r--r--drivers/clk/meson/clkc.h2
-rw-r--r--drivers/clk/meson/gxbb.c171
-rw-r--r--drivers/clk/meson/gxbb.h31
-rw-r--r--drivers/clk/meson/meson8b.c (renamed from drivers/clk/meson/meson8b-clkc.c)293
-rw-r--r--drivers/clk/meson/meson8b.h151
6 files changed, 523 insertions, 127 deletions
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d4cd4a35d74e..349583405b7c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,5 +3,5 @@
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 53326c32e853..9bb70e7a7d6a 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -98,7 +98,7 @@ struct meson_clk_mpll {
98}; 98};
99 99
100#define MESON_GATE(_name, _reg, _bit) \ 100#define MESON_GATE(_name, _reg, _bit) \
101struct clk_gate gxbb_##_name = { \ 101struct clk_gate _name = { \
102 .reg = (void __iomem *) _reg, \ 102 .reg = (void __iomem *) _reg, \
103 .bit_idx = (_bit), \ 103 .bit_idx = (_bit), \
104 .lock = &clk_lock, \ 104 .lock = &clk_lock, \
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a4c6684b3019..b3bd813a0772 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -565,90 +565,93 @@ static struct clk_gate gxbb_clk81 = {
565}; 565};
566 566
567/* Everything Else (EE) domain gates */ 567/* Everything Else (EE) domain gates */
568static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); 568static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
569static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); 569static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
570static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); 570static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
571static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); 571static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
572static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); 572static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
573static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); 573static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
574static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); 574static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
575static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); 575static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
576static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); 576static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
577static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); 577static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
578static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); 578static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
579static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); 579static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
580static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); 580static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
581static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); 581static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
582static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); 582static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
583static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); 583static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
584static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); 584static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
585static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); 585static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
586static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); 586static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
587 587static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
588static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); 588static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
589static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); 589static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
590static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); 590
591static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); 591static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
592static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); 592static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
593static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); 593static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
594static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); 594static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
595static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); 595static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
596static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); 596static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
597static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); 597static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
598static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); 598static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
599static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); 599static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
600static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); 600static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
601static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); 601static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
602static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); 602static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
603static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); 603static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
604static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); 604static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
605static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); 605static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
606static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); 606static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
607static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); 607static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
608static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); 608static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
609static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); 609static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
610static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); 610static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
611static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); 611static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
612static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); 612static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
613 613static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
614static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); 614static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
615static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 615static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
616static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 616
617static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); 617static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
618static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 618static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
619static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 619static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
620static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); 620static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
621static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); 621static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
622static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); 622static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
623static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); 623static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
624static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); 624static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
625static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 625static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
626static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); 626static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
627 627static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
628static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); 628static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
629static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); 629static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
630static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); 630
631static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); 631static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
632static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); 632static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
633static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); 633static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
634static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); 634static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
635static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); 635static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
636static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); 636static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
637static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); 637static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
638static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); 638static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
639static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); 639static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
640static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); 640static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
641static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); 641static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
642static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); 642static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
643static MESON_GATE(edp, HHI_GCLK_OTHER, 31); 643static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
644static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
645static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
646static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
644 647
645/* Always On (AO) domain gates */ 648/* Always On (AO) domain gates */
646 649
647static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); 650static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
648static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); 651static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
649static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); 652static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
650static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); 653static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
651static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); 654static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
652 655
653/* Array of all clocks provided by this provider */ 656/* Array of all clocks provided by this provider */
654 657
@@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
748 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 751 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
749 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 752 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
750 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 753 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
754 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
755 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
756 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
751 }, 757 },
752 .num = NR_CLKS, 758 .num = NR_CLKS,
753}; 759};
@@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
847 &gxbb_ao_ahb_bus, 853 &gxbb_ao_ahb_bus,
848 &gxbb_ao_iface, 854 &gxbb_ao_iface,
849 &gxbb_ao_i2c, 855 &gxbb_ao_i2c,
856 &gxbb_emmc_a,
857 &gxbb_emmc_b,
858 &gxbb_emmc_c,
850}; 859};
851 860
852static int gxbb_clkc_probe(struct platform_device *pdev) 861static int gxbb_clkc_probe(struct platform_device *pdev)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index a2adf3448b59..0252939ba58f 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -170,11 +170,11 @@
170 */ 170 */
171#define CLKID_SYS_PLL 0 171#define CLKID_SYS_PLL 0
172/* CLKID_CPUCLK */ 172/* CLKID_CPUCLK */
173#define CLKID_HDMI_PLL 2 173/* CLKID_HDMI_PLL */
174#define CLKID_FIXED_PLL 3 174#define CLKID_FIXED_PLL 3
175#define CLKID_FCLK_DIV2 4 175/* CLKID_FCLK_DIV2 */
176#define CLKID_FCLK_DIV3 5 176/* CLKID_FCLK_DIV3 */
177#define CLKID_FCLK_DIV4 6 177/* CLKID_FCLK_DIV4 */
178#define CLKID_FCLK_DIV5 7 178#define CLKID_FCLK_DIV5 7
179#define CLKID_FCLK_DIV7 8 179#define CLKID_FCLK_DIV7 8
180#define CLKID_GP0_PLL 9 180#define CLKID_GP0_PLL 9
@@ -183,14 +183,14 @@
183/* CLKID_CLK81 */ 183/* CLKID_CLK81 */
184#define CLKID_MPLL0 13 184#define CLKID_MPLL0 13
185#define CLKID_MPLL1 14 185#define CLKID_MPLL1 14
186#define CLKID_MPLL2 15 186/* CLKID_MPLL2 */
187#define CLKID_DDR 16 187#define CLKID_DDR 16
188#define CLKID_DOS 17 188#define CLKID_DOS 17
189#define CLKID_ISA 18 189#define CLKID_ISA 18
190#define CLKID_PL301 19 190#define CLKID_PL301 19
191#define CLKID_PERIPHS 20 191#define CLKID_PERIPHS 20
192#define CLKID_SPICC 21 192#define CLKID_SPICC 21
193#define CLKID_I2C 22 193/* CLKID_I2C */
194#define CLKID_SAR_ADC 23 194#define CLKID_SAR_ADC 23
195#define CLKID_SMART_CARD 24 195#define CLKID_SMART_CARD 24
196#define CLKID_RNG0 25 196#define CLKID_RNG0 25
@@ -202,7 +202,7 @@
202#define CLKID_ABUF 31 202#define CLKID_ABUF 31
203#define CLKID_HIU_IFACE 32 203#define CLKID_HIU_IFACE 32
204#define CLKID_ASSIST_MISC 33 204#define CLKID_ASSIST_MISC 33
205#define CLKID_SPI 34 205/* CLKID_SPI */
206#define CLKID_I2S_SPDIF 35 206#define CLKID_I2S_SPDIF 35
207#define CLKID_ETH 36 207#define CLKID_ETH 36
208#define CLKID_DEMUX 37 208#define CLKID_DEMUX 37
@@ -218,12 +218,12 @@
218#define CLKID_AIU 47 218#define CLKID_AIU 47
219#define CLKID_UART1 48 219#define CLKID_UART1 48
220#define CLKID_G2D 49 220#define CLKID_G2D 49
221#define CLKID_USB0 50 221/* CLKID_USB0 */
222#define CLKID_USB1 51 222/* CLKID_USB1 */
223#define CLKID_RESET 52 223#define CLKID_RESET 52
224#define CLKID_NAND 53 224#define CLKID_NAND 53
225#define CLKID_DOS_PARSER 54 225#define CLKID_DOS_PARSER 54
226#define CLKID_USB 55 226/* CLKID_USB */
227#define CLKID_VDIN1 56 227#define CLKID_VDIN1 56
228#define CLKID_AHB_ARB0 57 228#define CLKID_AHB_ARB0 57
229#define CLKID_EFUSE 58 229#define CLKID_EFUSE 58
@@ -232,8 +232,8 @@
232#define CLKID_AHB_CTRL_BUS 61 232#define CLKID_AHB_CTRL_BUS 61
233#define CLKID_HDMI_INTR_SYNC 62 233#define CLKID_HDMI_INTR_SYNC 62
234#define CLKID_HDMI_PCLK 63 234#define CLKID_HDMI_PCLK 63
235#define CLKID_USB1_DDR_BRIDGE 64 235/* CLKID_USB1_DDR_BRIDGE */
236#define CLKID_USB0_DDR_BRIDGE 65 236/* CLKID_USB0_DDR_BRIDGE */
237#define CLKID_MMC_PCLK 66 237#define CLKID_MMC_PCLK 66
238#define CLKID_DVIN 67 238#define CLKID_DVIN 67
239#define CLKID_UART2 68 239#define CLKID_UART2 68
@@ -261,9 +261,12 @@
261#define CLKID_AO_AHB_SRAM 90 261#define CLKID_AO_AHB_SRAM 90
262#define CLKID_AO_AHB_BUS 91 262#define CLKID_AO_AHB_BUS 91
263#define CLKID_AO_IFACE 92 263#define CLKID_AO_IFACE 92
264#define CLKID_AO_I2C 93 264/* CLKID_AO_I2C */
265/* CLKID_SD_EMMC_A */
266/* CLKID_SD_EMMC_B */
267/* CLKID_SD_EMMC_C */
265 268
266#define NR_CLKS 94 269#define NR_CLKS 97
267 270
268/* include the CLKIDs that have been made part of the stable DT binding */ 271/* include the CLKIDs that have been made part of the stable DT binding */
269#include <dt-bindings/clock/gxbb-clkc.h> 272#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b.c
index 4c9413cdf373..e1d4aa145a03 100644
--- a/drivers/clk/meson/meson8b-clkc.c
+++ b/drivers/clk/meson/meson8b.c
@@ -23,27 +23,11 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/clk-provider.h> 24#include <linux/clk-provider.h>
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <dt-bindings/clock/meson8b-clkc.h>
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/init.h> 27#include <linux/init.h>
29 28
30#include "clkc.h" 29#include "clkc.h"
31 30#include "meson8b.h"
32/*
33 * Clock controller register offsets
34 *
35 * Register offsets from the HardKernel[0] data sheet are listed in comment
36 * blocks below. Those offsets must be multiplied by 4 before adding them to
37 * the base address to get the right value
38 *
39 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
40 */
41#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
42#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
43#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
44#define MESON8B_REG_PLL_FIXED 0x0280
45#define MESON8B_REG_PLL_SYS 0x0300
46#define MESON8B_REG_PLL_VID 0x0320
47 31
48static DEFINE_SPINLOCK(clk_lock); 32static DEFINE_SPINLOCK(clk_lock);
49 33
@@ -128,17 +112,17 @@ static struct clk_fixed_rate meson8b_xtal = {
128 112
129static struct meson_clk_pll meson8b_fixed_pll = { 113static struct meson_clk_pll meson8b_fixed_pll = {
130 .m = { 114 .m = {
131 .reg_off = MESON8B_REG_PLL_FIXED, 115 .reg_off = HHI_MPLL_CNTL,
132 .shift = 0, 116 .shift = 0,
133 .width = 9, 117 .width = 9,
134 }, 118 },
135 .n = { 119 .n = {
136 .reg_off = MESON8B_REG_PLL_FIXED, 120 .reg_off = HHI_MPLL_CNTL,
137 .shift = 9, 121 .shift = 9,
138 .width = 5, 122 .width = 5,
139 }, 123 },
140 .od = { 124 .od = {
141 .reg_off = MESON8B_REG_PLL_FIXED, 125 .reg_off = HHI_MPLL_CNTL,
142 .shift = 16, 126 .shift = 16,
143 .width = 2, 127 .width = 2,
144 }, 128 },
@@ -154,17 +138,17 @@ static struct meson_clk_pll meson8b_fixed_pll = {
154 138
155static struct meson_clk_pll meson8b_vid_pll = { 139static struct meson_clk_pll meson8b_vid_pll = {
156 .m = { 140 .m = {
157 .reg_off = MESON8B_REG_PLL_VID, 141 .reg_off = HHI_VID_PLL_CNTL,
158 .shift = 0, 142 .shift = 0,
159 .width = 9, 143 .width = 9,
160 }, 144 },
161 .n = { 145 .n = {
162 .reg_off = MESON8B_REG_PLL_VID, 146 .reg_off = HHI_VID_PLL_CNTL,
163 .shift = 9, 147 .shift = 9,
164 .width = 5, 148 .width = 5,
165 }, 149 },
166 .od = { 150 .od = {
167 .reg_off = MESON8B_REG_PLL_VID, 151 .reg_off = HHI_VID_PLL_CNTL,
168 .shift = 16, 152 .shift = 16,
169 .width = 2, 153 .width = 2,
170 }, 154 },
@@ -180,17 +164,17 @@ static struct meson_clk_pll meson8b_vid_pll = {
180 164
181static struct meson_clk_pll meson8b_sys_pll = { 165static struct meson_clk_pll meson8b_sys_pll = {
182 .m = { 166 .m = {
183 .reg_off = MESON8B_REG_PLL_SYS, 167 .reg_off = HHI_SYS_PLL_CNTL,
184 .shift = 0, 168 .shift = 0,
185 .width = 9, 169 .width = 9,
186 }, 170 },
187 .n = { 171 .n = {
188 .reg_off = MESON8B_REG_PLL_SYS, 172 .reg_off = HHI_SYS_PLL_CNTL,
189 .shift = 9, 173 .shift = 9,
190 .width = 5, 174 .width = 5,
191 }, 175 },
192 .od = { 176 .od = {
193 .reg_off = MESON8B_REG_PLL_SYS, 177 .reg_off = HHI_SYS_PLL_CNTL,
194 .shift = 16, 178 .shift = 16,
195 .width = 2, 179 .width = 2,
196 }, 180 },
@@ -267,7 +251,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
267 * forthcoming coordinated clock rates feature 251 * forthcoming coordinated clock rates feature
268 */ 252 */
269static struct meson_clk_cpu meson8b_cpu_clk = { 253static struct meson_clk_cpu meson8b_cpu_clk = {
270 .reg_off = MESON8B_REG_SYS_CPU_CNTL1, 254 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
271 .div_table = cpu_div_table, 255 .div_table = cpu_div_table,
272 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, 256 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
273 .hw.init = &(struct clk_init_data){ 257 .hw.init = &(struct clk_init_data){
@@ -281,7 +265,7 @@ static struct meson_clk_cpu meson8b_cpu_clk = {
281static u32 mux_table_clk81[] = { 6, 5, 7 }; 265static u32 mux_table_clk81[] = { 6, 5, 7 };
282 266
283struct clk_mux meson8b_mpeg_clk_sel = { 267struct clk_mux meson8b_mpeg_clk_sel = {
284 .reg = (void *)MESON8B_REG_HHI_MPEG, 268 .reg = (void *)HHI_MPEG_CLK_CNTL,
285 .mask = 0x7, 269 .mask = 0x7,
286 .shift = 12, 270 .shift = 12,
287 .flags = CLK_MUX_READ_ONLY, 271 .flags = CLK_MUX_READ_ONLY,
@@ -303,7 +287,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
303}; 287};
304 288
305struct clk_divider meson8b_mpeg_clk_div = { 289struct clk_divider meson8b_mpeg_clk_div = {
306 .reg = (void *)MESON8B_REG_HHI_MPEG, 290 .reg = (void *)HHI_MPEG_CLK_CNTL,
307 .shift = 0, 291 .shift = 0,
308 .width = 7, 292 .width = 7,
309 .lock = &clk_lock, 293 .lock = &clk_lock,
@@ -317,7 +301,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
317}; 301};
318 302
319struct clk_gate meson8b_clk81 = { 303struct clk_gate meson8b_clk81 = {
320 .reg = (void *)MESON8B_REG_HHI_MPEG, 304 .reg = (void *)HHI_MPEG_CLK_CNTL,
321 .bit_idx = 7, 305 .bit_idx = 7,
322 .lock = &clk_lock, 306 .lock = &clk_lock,
323 .hw.init = &(struct clk_init_data){ 307 .hw.init = &(struct clk_init_data){
@@ -329,6 +313,92 @@ struct clk_gate meson8b_clk81 = {
329 }, 313 },
330}; 314};
331 315
316/* Everything Else (EE) domain gates */
317
318static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
319static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
320static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
321static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
322static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
323static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
324static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
325static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
326static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
327static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
328static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
329static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
330static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
331static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
332static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
333static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
334static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
335static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
336static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
337
338static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
339static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
340static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
341static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
342static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
343static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
344static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
345static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
346static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
347static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
348static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
349static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
350static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
351static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
352static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
353static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
354static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
355static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
356static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
357static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
358static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
359static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
360static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
361static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
362static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
363
364static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
365static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
366static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
367static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
368static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
369static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
370static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
371static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
372static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
373static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
374static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
375static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
376static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
377
378static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
379static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
380static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
381static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
382static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
383static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
384static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
385static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
386static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
387static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
388static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
389static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
390static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
391static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
392static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
393static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
394
395/* Always On (AO) domain gates */
396
397static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
398static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
399static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
400static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
401
332static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 402static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
333 .hws = { 403 .hws = {
334 [CLKID_XTAL] = &meson8b_xtal.hw, 404 [CLKID_XTAL] = &meson8b_xtal.hw,
@@ -344,6 +414,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
344 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 414 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
345 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 415 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
346 [CLKID_CLK81] = &meson8b_clk81.hw, 416 [CLKID_CLK81] = &meson8b_clk81.hw,
417 [CLKID_DDR] = &meson8b_ddr.hw,
418 [CLKID_DOS] = &meson8b_dos.hw,
419 [CLKID_ISA] = &meson8b_isa.hw,
420 [CLKID_PL301] = &meson8b_pl301.hw,
421 [CLKID_PERIPHS] = &meson8b_periphs.hw,
422 [CLKID_SPICC] = &meson8b_spicc.hw,
423 [CLKID_I2C] = &meson8b_i2c.hw,
424 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
425 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
426 [CLKID_RNG0] = &meson8b_rng0.hw,
427 [CLKID_UART0] = &meson8b_uart0.hw,
428 [CLKID_SDHC] = &meson8b_sdhc.hw,
429 [CLKID_STREAM] = &meson8b_stream.hw,
430 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
431 [CLKID_SDIO] = &meson8b_sdio.hw,
432 [CLKID_ABUF] = &meson8b_abuf.hw,
433 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
434 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
435 [CLKID_SPI] = &meson8b_spi.hw,
436 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
437 [CLKID_ETH] = &meson8b_eth.hw,
438 [CLKID_DEMUX] = &meson8b_demux.hw,
439 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
440 [CLKID_IEC958] = &meson8b_iec958.hw,
441 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
442 [CLKID_AMCLK] = &meson8b_amclk.hw,
443 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
444 [CLKID_MIXER] = &meson8b_mixer.hw,
445 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
446 [CLKID_ADC] = &meson8b_adc.hw,
447 [CLKID_BLKMV] = &meson8b_blkmv.hw,
448 [CLKID_AIU] = &meson8b_aiu.hw,
449 [CLKID_UART1] = &meson8b_uart1.hw,
450 [CLKID_G2D] = &meson8b_g2d.hw,
451 [CLKID_USB0] = &meson8b_usb0.hw,
452 [CLKID_USB1] = &meson8b_usb1.hw,
453 [CLKID_RESET] = &meson8b_reset.hw,
454 [CLKID_NAND] = &meson8b_nand.hw,
455 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
456 [CLKID_USB] = &meson8b_usb.hw,
457 [CLKID_VDIN1] = &meson8b_vdin1.hw,
458 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
459 [CLKID_EFUSE] = &meson8b_efuse.hw,
460 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
461 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
462 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
463 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
464 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
465 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
466 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
467 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
468 [CLKID_DVIN] = &meson8b_dvin.hw,
469 [CLKID_UART2] = &meson8b_uart2.hw,
470 [CLKID_SANA] = &meson8b_sana.hw,
471 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
472 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
473 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
474 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
475 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
476 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
477 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
478 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
479 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw,
480 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
481 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
482 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
483 [CLKID_ENC480P] = &meson8b_enc480p.hw,
484 [CLKID_RNG1] = &meson8b_rng1.hw,
485 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
486 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
487 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
488 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
489 [CLKID_EDP] = &meson8b_edp.hw,
490 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
491 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
492 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
493 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
347 }, 494 },
348 .num = CLK_NR_CLKS, 495 .num = CLK_NR_CLKS,
349}; 496};
@@ -354,6 +501,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
354 &meson8b_sys_pll, 501 &meson8b_sys_pll,
355}; 502};
356 503
504static struct clk_gate *meson8b_clk_gates[] = {
505 &meson8b_clk81,
506 &meson8b_ddr,
507 &meson8b_dos,
508 &meson8b_isa,
509 &meson8b_pl301,
510 &meson8b_periphs,
511 &meson8b_spicc,
512 &meson8b_i2c,
513 &meson8b_sar_adc,
514 &meson8b_smart_card,
515 &meson8b_rng0,
516 &meson8b_uart0,
517 &meson8b_sdhc,
518 &meson8b_stream,
519 &meson8b_async_fifo,
520 &meson8b_sdio,
521 &meson8b_abuf,
522 &meson8b_hiu_iface,
523 &meson8b_assist_misc,
524 &meson8b_spi,
525 &meson8b_i2s_spdif,
526 &meson8b_eth,
527 &meson8b_demux,
528 &meson8b_aiu_glue,
529 &meson8b_iec958,
530 &meson8b_i2s_out,
531 &meson8b_amclk,
532 &meson8b_aififo2,
533 &meson8b_mixer,
534 &meson8b_mixer_iface,
535 &meson8b_adc,
536 &meson8b_blkmv,
537 &meson8b_aiu,
538 &meson8b_uart1,
539 &meson8b_g2d,
540 &meson8b_usb0,
541 &meson8b_usb1,
542 &meson8b_reset,
543 &meson8b_nand,
544 &meson8b_dos_parser,
545 &meson8b_usb,
546 &meson8b_vdin1,
547 &meson8b_ahb_arb0,
548 &meson8b_efuse,
549 &meson8b_boot_rom,
550 &meson8b_ahb_data_bus,
551 &meson8b_ahb_ctrl_bus,
552 &meson8b_hdmi_intr_sync,
553 &meson8b_hdmi_pclk,
554 &meson8b_usb1_ddr_bridge,
555 &meson8b_usb0_ddr_bridge,
556 &meson8b_mmc_pclk,
557 &meson8b_dvin,
558 &meson8b_uart2,
559 &meson8b_sana,
560 &meson8b_vpu_intr,
561 &meson8b_sec_ahb_ahb3_bridge,
562 &meson8b_clk81_a9,
563 &meson8b_vclk2_venci0,
564 &meson8b_vclk2_venci1,
565 &meson8b_vclk2_vencp0,
566 &meson8b_vclk2_vencp1,
567 &meson8b_gclk_venci_int,
568 &meson8b_gclk_vencp_int,
569 &meson8b_dac_clk,
570 &meson8b_aoclk_gate,
571 &meson8b_iec958_gate,
572 &meson8b_enc480p,
573 &meson8b_rng1,
574 &meson8b_gclk_vencl_int,
575 &meson8b_vclk2_venclmcc,
576 &meson8b_vclk2_vencl,
577 &meson8b_vclk2_other,
578 &meson8b_edp,
579 &meson8b_ao_media_cpu,
580 &meson8b_ao_ahb_sram,
581 &meson8b_ao_ahb_bus,
582 &meson8b_ao_iface,
583};
584
357static int meson8b_clkc_probe(struct platform_device *pdev) 585static int meson8b_clkc_probe(struct platform_device *pdev)
358{ 586{
359 void __iomem *clk_base; 587 void __iomem *clk_base;
@@ -381,6 +609,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
381 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; 609 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
382 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; 610 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
383 611
612 /* Populate base address for gates */
613 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
614 meson8b_clk_gates[i]->reg = clk_base +
615 (u32)meson8b_clk_gates[i]->reg;
616
384 /* 617 /*
385 * register all clks 618 * register all clks
386 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 619 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
new file mode 100644
index 000000000000..010e9582888d
--- /dev/null
+++ b/drivers/clk/meson/meson8b.h
@@ -0,0 +1,151 @@
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * Copyright (c) 2016 BayLibre, Inc.
6 * Michael Turquette <mturquette@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MESON8B_H
22#define __MESON8B_H
23
24/*
25 * Clock controller register offsets
26 *
27 * Register offsets from the HardKernel[0] data sheet are listed in comment
28 * blocks below. Those offsets must be multiplied by 4 before adding them to
29 * the base address to get the right value
30 *
31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
32 */
33#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
34#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
35#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
36#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
37#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
38#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
39#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
40#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
41#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
42#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
43
44/*
45 * CLKID index values
46 *
47 * These indices are entirely contrived and do not map onto the hardware.
48 * Migrate them out of this header and into the DT header file when they need
49 * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
50 */
51
52/* CLKID_UNUSED */
53/* CLKID_XTAL */
54/* CLKID_PLL_FIXED */
55/* CLKID_PLL_VID */
56/* CLKID_PLL_SYS */
57/* CLKID_FCLK_DIV2 */
58/* CLKID_FCLK_DIV3 */
59/* CLKID_FCLK_DIV4 */
60/* CLKID_FCLK_DIV5 */
61/* CLKID_FCLK_DIV7 */
62/* CLKID_CLK81 */
63/* CLKID_MALI */
64/* CLKID_CPUCLK */
65/* CLKID_ZERO */
66/* CLKID_MPEG_SEL */
67/* CLKID_MPEG_DIV */
68#define CLKID_DDR 16
69#define CLKID_DOS 17
70#define CLKID_ISA 18
71#define CLKID_PL301 19
72#define CLKID_PERIPHS 20
73#define CLKID_SPICC 21
74#define CLKID_I2C 22
75#define CLKID_SAR_ADC 23
76#define CLKID_SMART_CARD 24
77#define CLKID_RNG0 25
78#define CLKID_UART0 26
79#define CLKID_SDHC 27
80#define CLKID_STREAM 28
81#define CLKID_ASYNC_FIFO 29
82#define CLKID_SDIO 30
83#define CLKID_ABUF 31
84#define CLKID_HIU_IFACE 32
85#define CLKID_ASSIST_MISC 33
86#define CLKID_SPI 34
87#define CLKID_I2S_SPDIF 35
88#define CLKID_ETH 36
89#define CLKID_DEMUX 37
90#define CLKID_AIU_GLUE 38
91#define CLKID_IEC958 39
92#define CLKID_I2S_OUT 40
93#define CLKID_AMCLK 41
94#define CLKID_AIFIFO2 42
95#define CLKID_MIXER 43
96#define CLKID_MIXER_IFACE 44
97#define CLKID_ADC 45
98#define CLKID_BLKMV 46
99#define CLKID_AIU 47
100#define CLKID_UART1 48
101#define CLKID_G2D 49
102#define CLKID_USB0 50
103#define CLKID_USB1 51
104#define CLKID_RESET 52
105#define CLKID_NAND 53
106#define CLKID_DOS_PARSER 54
107#define CLKID_USB 55
108#define CLKID_VDIN1 56
109#define CLKID_AHB_ARB0 57
110#define CLKID_EFUSE 58
111#define CLKID_BOOT_ROM 59
112#define CLKID_AHB_DATA_BUS 60
113#define CLKID_AHB_CTRL_BUS 61
114#define CLKID_HDMI_INTR_SYNC 62
115#define CLKID_HDMI_PCLK 63
116#define CLKID_USB1_DDR_BRIDGE 64
117#define CLKID_USB0_DDR_BRIDGE 65
118#define CLKID_MMC_PCLK 66
119#define CLKID_DVIN 67
120#define CLKID_UART2 68
121#define CLKID_SANA 69
122#define CLKID_VPU_INTR 70
123#define CLKID_SEC_AHB_AHB3_BRIDGE 71
124#define CLKID_CLK81_A9 72
125#define CLKID_VCLK2_VENCI0 73
126#define CLKID_VCLK2_VENCI1 74
127#define CLKID_VCLK2_VENCP0 75
128#define CLKID_VCLK2_VENCP1 76
129#define CLKID_GCLK_VENCI_INT 77
130#define CLKID_GCLK_VENCP_INT 78
131#define CLKID_DAC_CLK 79
132#define CLKID_AOCLK_GATE 80
133#define CLKID_IEC958_GATE 81
134#define CLKID_ENC480P 82
135#define CLKID_RNG1 83
136#define CLKID_GCLK_VENCL_INT 84
137#define CLKID_VCLK2_VENCLMCC 85
138#define CLKID_VCLK2_VENCL 86
139#define CLKID_VCLK2_OTHER 87
140#define CLKID_EDP 88
141#define CLKID_AO_MEDIA_CPU 89
142#define CLKID_AO_AHB_SRAM 90
143#define CLKID_AO_AHB_BUS 91
144#define CLKID_AO_IFACE 92
145
146#define CLK_NR_CLKS 93
147
148/* include the CLKIDs that have been made part of the stable DT binding */
149#include <dt-bindings/clock/meson8b-clkc.h>
150
151#endif /* __MESON8B_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 21:03:12 -0500