Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "This is a rather large set of patches for device drivers that for one
  reason or another the subsystem maintainer preferred to get merged
  through the arm-soc tree.  There are both new drivers as well as
  existing drivers that are getting converted from platform-specific
  code into standalone drivers using the appropriate subsystem specific
  interfaces.

  In particular, we can now have pinctrl, clk, clksource and irqchip
  drivers in one file per driver, without the need to call into platform
  specific interface, or to get called from platform specific code, as
  long as all information about the hardware is provided through a
  device tree.

  Most of the drivers we touch this time are for clocksource.  Since now
  most of them are part of drivers/clocksource, I expect that we won't
  have to touch these again from arm-soc and can let the clocksource
  maintainers take care of these in the future.

  Another larger part of this series is specific to the exynos platform,
  which is seeing some significant effort in upstreaming and
  modernization of its device drivers this time around, which
  unfortunately is also the cause for the churn and a lot of the merge
  conflicts.

  There is one new subsystem that gets merged as part of this series:
  the reset controller interface, which is a very simple interface for
  taking devices on the SoC out of reset or back into reset.  Patches to
  use this interface on i.MX follow later in this merge window, and we
  are going to have other platforms (at least tegra and sirf) get
  converted in 3.11.  This will let us get rid of platform specific
  callbacks in a number of platform independent device drivers."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
  irqchip: s3c24xx: add missing __init annotations
  ARM: dts: Disable the RTC by default on exynos5
  clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
  ARM: exynos: restore mach/regs-clock.h for exynos5
  clocksource: exynos_mct: fix build error on non-DT
  pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
  irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
  reset: NULL deref on allocation failure
  reset: Add reset controller API
  dt: describe base reset signal binding
  ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
  ARM: EXYNOS: Enable PMUs for exynos4
  irqchip: exynos-combiner: Correct combined IRQs for exynos4
  irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: tegra: fix enum tegra114_clk to match binding
  ...

1 files changed, 99 insertions, 85 deletions

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf194009e20f..8292a00c3de9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
 #define PLLE_BASE 0xe8
 #define PLLE_MISC 0xec
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLL_MISC_LOCK_ENABLE 18
 #define PLLDU_MISC_LOCK_ENABLE 22
@@ -236,7 +236,7 @@ enum tegra20_clk {
         dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
         pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
-        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
+        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
         uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
         osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
         pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
 static struct clk_onecell_data clk_data;
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 12000000, 600000000, 600, 12, 0, 8 },
+        { 13000000, 600000000, 600, 13, 0, 8 },
+        { 19200000, 600000000, 500, 16, 0, 6 },
+        { 26000000, 600000000, 600, 26, 0, 8 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 666000000, 666, 12, 0, 8},
+        { 13000000, 666000000, 666, 13, 0, 8},
+        { 19200000, 666000000, 555, 16, 0, 8},
+        { 26000000, 666000000, 666, 26, 0, 8},
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
+        { 12000000, 216000000, 432, 12, 1, 8},
+        { 13000000, 216000000, 432, 13, 1, 8},
+        { 19200000, 216000000, 90,   4, 1, 1},
+        { 26000000, 216000000, 432, 26, 1, 8},
+        { 12000000, 432000000, 432, 12, 0, 8},
+        { 13000000, 432000000, 432, 13, 0, 8},
+        { 19200000, 432000000, 90,   4, 0, 1},
+        { 26000000, 432000000, 432, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
+        { 28800000, 56448000, 49, 25, 0, 1},
+        { 28800000, 73728000, 64, 25, 0, 1},
+        { 28800000, 24000000,  5,  6, 0, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 216000000, 216, 12, 0, 4},
+        { 13000000, 216000000, 216, 13, 0, 4},
+        { 19200000, 216000000, 135, 12, 0, 3},
+        { 26000000, 216000000, 216, 26, 0, 4},
 
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 594000000, 594, 12, 0, 8},
+        { 13000000, 594000000, 594, 13, 0, 8},
+        { 19200000, 594000000, 495, 16, 0, 8},
+        { 26000000, 594000000, 594, 26, 0, 8},
 
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
+        { 12000000, 480000000, 960, 12, 0, 0},
+        { 13000000, 480000000, 960, 13, 0, 0},
+        { 19200000, 480000000, 200, 4,  0, 0},
+        { 26000000, 480000000, 960, 26, 0, 0},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
         /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
+        { 12000000, 912000000,  912,  12, 0, 12},
+        { 13000000, 912000000,  912,  13, 0, 12},
+        { 19200000, 912000000,  760,  16, 0, 8},
+        { 26000000, 912000000,  912,  26, 0, 12},
 
         /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
+        { 12000000, 816000000,  816,  12, 0, 12},
+        { 13000000, 816000000,  816,  13, 0, 12},
+        { 19200000, 816000000,  680,  16, 0, 8},
+        { 26000000, 816000000,  816,  26, 0, 12},
 
         /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
+        { 12000000, 760000000,  760,  12, 0, 12},
+        { 13000000, 760000000,  760,  13, 0, 12},
+        { 19200000, 760000000,  950,  24, 0, 8},
+        { 26000000, 760000000,  760,  26, 0, 12},
 
         /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
+        { 12000000, 750000000,  750,  12, 0, 12},
+        { 13000000, 750000000,  750,  13, 0, 12},
+        { 19200000, 750000000,  625,  16, 0, 8},
+        { 26000000, 750000000,  750,  26, 0, 12},
 
         /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
+        { 12000000, 608000000,  608,  12, 0, 12},
+        { 13000000, 608000000,  608,  13, 0, 12},
+        { 19200000, 608000000,  380,  12, 0, 8},
+        { 26000000, 608000000,  608,  26, 0, 12},
 
         /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
+        { 12000000, 456000000,  456,  12, 0, 12},
+        { 13000000, 456000000,  456,  13, 0, 12},
+        { 19200000, 456000000,  380,  16, 0, 8},
+        { 26000000, 456000000,  456,  26, 0, 12},
 
         /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
+        { 12000000, 312000000,  312,  12, 0, 12},
+        { 13000000, 312000000,  312,  13, 0, 12},
+        { 19200000, 312000000,  260,  16, 0, 8},
+        { 26000000, 312000000,  312,  26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 12000000, 100000000,  200,  24, 0, 0 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
 
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
 static struct tegra_clk_pll_params pll_u_params = {
         .input_min = 2000000,
         .input_max = 40000000,
@@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1200000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 0,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 0,
 };
@@ -1012,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
                 data = &tegra_periph_clk_list[i];
                 clk = tegra_clk_register_periph(data->name, data->parent_names,
                                 data->num_parents, &data->periph,
-                                clk_base, data->offset);
+                                clk_base, data->offset, data->flags);
                 clk_register_clkdev(clk, data->con_id, data->dev_id);
                 clks[data->clk_id] = clk;
         }
@@ -1247,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
         {host1x, pll_c, 150000000, 0},
         {disp1, pll_p, 600000000, 0},
         {disp2, pll_p, 600000000, 0},
+        {gr2d, pll_c, 300000000, 0},
+        {gr3d, pll_c, 300000000, 0},
         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
 };
 
+static void __init tegra20_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
 /*
  * Some clocks may be used by different drivers depending on the board
  * configuration.  List those here to register them twice in the clock lookup
@@ -1316,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        tegra_init_from_table(init_table, clks, clk_max);
+        tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
 
         tegra_cpu_car_ops = &tegra20_cpu_car_ops;
 }