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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2015-05-28 04:45:51 -0400
committerStephen Boyd <sboyd@codeaurora.org>2015-06-04 17:27:06 -0400
commit4a1caed3d0c2fbf8c9f18909bec69e2aa2638b97 (patch)
tree7540974803b64085cd2709c196a6463c5b9ecd4d /drivers/clk/samsung/clk-s5pv210.c
parent90acb40f1874f7b304b1d8d9b07c72aa83337e31 (diff)
clk: make several parent names const
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/samsung/clk-s5pv210.c')
-rw-r--r--drivers/clk/samsung/clk-s5pv210.c88
1 files changed, 44 insertions, 44 deletions
diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c
index e668e479a697..cf7e8fa7b624 100644
--- a/drivers/clk/samsung/clk-s5pv210.c
+++ b/drivers/clk/samsung/clk-s5pv210.c
@@ -169,44 +169,44 @@ static inline void s5pv210_clk_sleep_init(void) { }
169#endif 169#endif
170 170
171/* Mux parent lists. */ 171/* Mux parent lists. */
172static const char *fin_pll_p[] __initdata = { 172static const char *const fin_pll_p[] __initconst = {
173 "xxti", 173 "xxti",
174 "xusbxti" 174 "xusbxti"
175}; 175};
176 176
177static const char *mout_apll_p[] __initdata = { 177static const char *const mout_apll_p[] __initconst = {
178 "fin_pll", 178 "fin_pll",
179 "fout_apll" 179 "fout_apll"
180}; 180};
181 181
182static const char *mout_mpll_p[] __initdata = { 182static const char *const mout_mpll_p[] __initconst = {
183 "fin_pll", 183 "fin_pll",
184 "fout_mpll" 184 "fout_mpll"
185}; 185};
186 186
187static const char *mout_epll_p[] __initdata = { 187static const char *const mout_epll_p[] __initconst = {
188 "fin_pll", 188 "fin_pll",
189 "fout_epll" 189 "fout_epll"
190}; 190};
191 191
192static const char *mout_vpllsrc_p[] __initdata = { 192static const char *const mout_vpllsrc_p[] __initconst = {
193 "fin_pll", 193 "fin_pll",
194 "sclk_hdmi27m" 194 "sclk_hdmi27m"
195}; 195};
196 196
197static const char *mout_vpll_p[] __initdata = { 197static const char *const mout_vpll_p[] __initconst = {
198 "mout_vpllsrc", 198 "mout_vpllsrc",
199 "fout_vpll" 199 "fout_vpll"
200}; 200};
201 201
202static const char *mout_group1_p[] __initdata = { 202static const char *const mout_group1_p[] __initconst = {
203 "dout_a2m", 203 "dout_a2m",
204 "mout_mpll", 204 "mout_mpll",
205 "mout_epll", 205 "mout_epll",
206 "mout_vpll" 206 "mout_vpll"
207}; 207};
208 208
209static const char *mout_group2_p[] __initdata = { 209static const char *const mout_group2_p[] __initconst = {
210 "xxti", 210 "xxti",
211 "xusbxti", 211 "xusbxti",
212 "sclk_hdmi27m", 212 "sclk_hdmi27m",
@@ -218,7 +218,7 @@ static const char *mout_group2_p[] __initdata = {
218 "mout_vpll", 218 "mout_vpll",
219}; 219};
220 220
221static const char *mout_audio0_p[] __initdata = { 221static const char *const mout_audio0_p[] __initconst = {
222 "xxti", 222 "xxti",
223 "pcmcdclk0", 223 "pcmcdclk0",
224 "sclk_hdmi27m", 224 "sclk_hdmi27m",
@@ -230,7 +230,7 @@ static const char *mout_audio0_p[] __initdata = {
230 "mout_vpll", 230 "mout_vpll",
231}; 231};
232 232
233static const char *mout_audio1_p[] __initdata = { 233static const char *const mout_audio1_p[] __initconst = {
234 "i2scdclk1", 234 "i2scdclk1",
235 "pcmcdclk1", 235 "pcmcdclk1",
236 "sclk_hdmi27m", 236 "sclk_hdmi27m",
@@ -242,7 +242,7 @@ static const char *mout_audio1_p[] __initdata = {
242 "mout_vpll", 242 "mout_vpll",
243}; 243};
244 244
245static const char *mout_audio2_p[] __initdata = { 245static const char *const mout_audio2_p[] __initconst = {
246 "i2scdclk2", 246 "i2scdclk2",
247 "pcmcdclk2", 247 "pcmcdclk2",
248 "sclk_hdmi27m", 248 "sclk_hdmi27m",
@@ -254,63 +254,63 @@ static const char *mout_audio2_p[] __initdata = {
254 "mout_vpll", 254 "mout_vpll",
255}; 255};
256 256
257static const char *mout_spdif_p[] __initdata = { 257static const char *const mout_spdif_p[] __initconst = {
258 "dout_audio0", 258 "dout_audio0",
259 "dout_audio1", 259 "dout_audio1",
260 "dout_audio3", 260 "dout_audio3",
261}; 261};
262 262
263static const char *mout_group3_p[] __initdata = { 263static const char *const mout_group3_p[] __initconst = {
264 "mout_apll", 264 "mout_apll",
265 "mout_mpll" 265 "mout_mpll"
266}; 266};
267 267
268static const char *mout_group4_p[] __initdata = { 268static const char *const mout_group4_p[] __initconst = {
269 "mout_mpll", 269 "mout_mpll",
270 "dout_a2m" 270 "dout_a2m"
271}; 271};
272 272
273static const char *mout_flash_p[] __initdata = { 273static const char *const mout_flash_p[] __initconst = {
274 "dout_hclkd", 274 "dout_hclkd",
275 "dout_hclkp" 275 "dout_hclkp"
276}; 276};
277 277
278static const char *mout_dac_p[] __initdata = { 278static const char *const mout_dac_p[] __initconst = {
279 "mout_vpll", 279 "mout_vpll",
280 "sclk_hdmiphy" 280 "sclk_hdmiphy"
281}; 281};
282 282
283static const char *mout_hdmi_p[] __initdata = { 283static const char *const mout_hdmi_p[] __initconst = {
284 "sclk_hdmiphy", 284 "sclk_hdmiphy",
285 "dout_tblk" 285 "dout_tblk"
286}; 286};
287 287
288static const char *mout_mixer_p[] __initdata = { 288static const char *const mout_mixer_p[] __initconst = {
289 "mout_dac", 289 "mout_dac",
290 "mout_hdmi" 290 "mout_hdmi"
291}; 291};
292 292
293static const char *mout_vpll_6442_p[] __initdata = { 293static const char *const mout_vpll_6442_p[] __initconst = {
294 "fin_pll", 294 "fin_pll",
295 "fout_vpll" 295 "fout_vpll"
296}; 296};
297 297
298static const char *mout_mixer_6442_p[] __initdata = { 298static const char *const mout_mixer_6442_p[] __initconst = {
299 "mout_vpll", 299 "mout_vpll",
300 "dout_mixer" 300 "dout_mixer"
301}; 301};
302 302
303static const char *mout_d0sync_6442_p[] __initdata = { 303static const char *const mout_d0sync_6442_p[] __initconst = {
304 "mout_dsys", 304 "mout_dsys",
305 "div_apll" 305 "div_apll"
306}; 306};
307 307
308static const char *mout_d1sync_6442_p[] __initdata = { 308static const char *const mout_d1sync_6442_p[] __initconst = {
309 "mout_psys", 309 "mout_psys",
310 "div_apll" 310 "div_apll"
311}; 311};
312 312
313static const char *mout_group2_6442_p[] __initdata = { 313static const char *const mout_group2_6442_p[] __initconst = {
314 "fin_pll", 314 "fin_pll",
315 "none", 315 "none",
316 "none", 316 "none",
@@ -322,7 +322,7 @@ static const char *mout_group2_6442_p[] __initdata = {
322 "mout_vpll", 322 "mout_vpll",
323}; 323};
324 324
325static const char *mout_audio0_6442_p[] __initdata = { 325static const char *const mout_audio0_6442_p[] __initconst = {
326 "fin_pll", 326 "fin_pll",
327 "pcmcdclk0", 327 "pcmcdclk0",
328 "none", 328 "none",
@@ -334,7 +334,7 @@ static const char *mout_audio0_6442_p[] __initdata = {
334 "mout_vpll", 334 "mout_vpll",
335}; 335};
336 336
337static const char *mout_audio1_6442_p[] __initdata = { 337static const char *const mout_audio1_6442_p[] __initconst = {
338 "i2scdclk1", 338 "i2scdclk1",
339 "pcmcdclk1", 339 "pcmcdclk1",
340 "none", 340 "none",
@@ -347,7 +347,7 @@ static const char *mout_audio1_6442_p[] __initdata = {
347 "fin_pll", 347 "fin_pll",
348}; 348};
349 349
350static const char *mout_clksel_p[] __initdata = { 350static const char *const mout_clksel_p[] __initconst = {
351 "fout_apll_clkout", 351 "fout_apll_clkout",
352 "fout_mpll_clkout", 352 "fout_mpll_clkout",
353 "fout_epll", 353 "fout_epll",
@@ -370,7 +370,7 @@ static const char *mout_clksel_p[] __initdata = {
370 "div_dclk" 370 "div_dclk"
371}; 371};
372 372
373static const char *mout_clksel_6442_p[] __initdata = { 373static const char *const mout_clksel_6442_p[] __initconst = {
374 "fout_apll_clkout", 374 "fout_apll_clkout",
375 "fout_mpll_clkout", 375 "fout_mpll_clkout",
376 "fout_epll", 376 "fout_epll",
@@ -393,7 +393,7 @@ static const char *mout_clksel_6442_p[] __initdata = {
393 "div_dclk" 393 "div_dclk"
394}; 394};
395 395
396static const char *mout_clkout_p[] __initdata = { 396static const char *const mout_clkout_p[] __initconst = {
397 "dout_clkout", 397 "dout_clkout",
398 "none", 398 "none",
399 "xxti", 399 "xxti",
@@ -401,20 +401,20 @@ static const char *mout_clkout_p[] __initdata = {
401}; 401};
402 402
403/* Common fixed factor clocks. */ 403/* Common fixed factor clocks. */
404static struct samsung_fixed_factor_clock ffactor_clks[] __initdata = { 404static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
405 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), 405 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
406 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), 406 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
407 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), 407 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
408}; 408};
409 409
410/* PLL input mux (fin_pll), which needs to be registered before PLLs. */ 410/* PLL input mux (fin_pll), which needs to be registered before PLLs. */
411static struct samsung_mux_clock early_mux_clks[] __initdata = { 411static const struct samsung_mux_clock early_mux_clks[] __initconst = {
412 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, 412 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
413 CLK_MUX_READ_ONLY, 0), 413 CLK_MUX_READ_ONLY, 0),
414}; 414};
415 415
416/* Common clock muxes. */ 416/* Common clock muxes. */
417static struct samsung_mux_clock mux_clks[] __initdata = { 417static const struct samsung_mux_clock mux_clks[] __initconst = {
418 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), 418 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
419 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), 419 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
420 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), 420 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
@@ -427,7 +427,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
427}; 427};
428 428
429/* S5PV210-specific clock muxes. */ 429/* S5PV210-specific clock muxes. */
430static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = { 430static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
431 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), 431 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
432 432
433 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1), 433 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
@@ -472,7 +472,7 @@ static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = {
472}; 472};
473 473
474/* S5P6442-specific clock muxes. */ 474/* S5P6442-specific clock muxes. */
475static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = { 475static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
476 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1), 476 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
477 477
478 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4), 478 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
@@ -504,7 +504,7 @@ static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = {
504}; 504};
505 505
506/* S5PV210-specific fixed rate clocks generated inside the SoC. */ 506/* S5PV210-specific fixed rate clocks generated inside the SoC. */
507static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = { 507static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
508 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 508 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
509 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 509 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
510 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 510 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
@@ -512,12 +512,12 @@ static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = {
512}; 512};
513 513
514/* S5P6442-specific fixed rate clocks generated inside the SoC. */ 514/* S5P6442-specific fixed rate clocks generated inside the SoC. */
515static struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initdata = { 515static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
516 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000), 516 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000),
517}; 517};
518 518
519/* Common clock dividers. */ 519/* Common clock dividers. */
520static struct samsung_div_clock div_clks[] __initdata = { 520static const struct samsung_div_clock div_clks[] __initconst = {
521 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), 521 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
522 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), 522 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
523 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3), 523 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
@@ -549,7 +549,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
549}; 549};
550 550
551/* S5PV210-specific clock dividers. */ 551/* S5PV210-specific clock dividers. */
552static struct samsung_div_clock s5pv210_div_clks[] __initdata = { 552static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
553 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4), 553 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
554 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4), 554 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
555 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3), 555 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
@@ -578,7 +578,7 @@ static struct samsung_div_clock s5pv210_div_clks[] __initdata = {
578}; 578};
579 579
580/* S5P6442-specific clock dividers. */ 580/* S5P6442-specific clock dividers. */
581static struct samsung_div_clock s5p6442_div_clks[] __initdata = { 581static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
582 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4), 582 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
583 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4), 583 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
584 584
@@ -586,7 +586,7 @@ static struct samsung_div_clock s5p6442_div_clks[] __initdata = {
586}; 586};
587 587
588/* Common clock gates. */ 588/* Common clock gates. */
589static struct samsung_gate_clock gate_clks[] __initdata = { 589static const struct samsung_gate_clock gate_clks[] __initconst = {
590 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0), 590 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
591 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0), 591 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
592 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0), 592 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
@@ -666,7 +666,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
666}; 666};
667 667
668/* S5PV210-specific clock gates. */ 668/* S5PV210-specific clock gates. */
669static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = { 669static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
670 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0), 670 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
671 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0), 671 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
672 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 672 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
@@ -728,7 +728,7 @@ static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = {
728}; 728};
729 729
730/* S5P6442-specific clock gates. */ 730/* S5P6442-specific clock gates. */
731static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = { 731static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
732 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0), 732 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
733 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0), 733 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
734 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 734 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
@@ -748,14 +748,14 @@ static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = {
748 * Clock aliases for legacy clkdev look-up. 748 * Clock aliases for legacy clkdev look-up.
749 * NOTE: Needed only to support legacy board files. 749 * NOTE: Needed only to support legacy board files.
750 */ 750 */
751static struct samsung_clock_alias s5pv210_aliases[] = { 751static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
752 ALIAS(DOUT_APLL, NULL, "armclk"), 752 ALIAS(DOUT_APLL, NULL, "armclk"),
753 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"), 753 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
754 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"), 754 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
755}; 755};
756 756
757/* S5PV210-specific PLLs. */ 757/* S5PV210-specific PLLs. */
758static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = { 758static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
759 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", 759 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
760 APLL_LOCK, APLL_CON0, NULL), 760 APLL_LOCK, APLL_CON0, NULL),
761 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 761 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
@@ -767,7 +767,7 @@ static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = {
767}; 767};
768 768
769/* S5P6442-specific PLLs. */ 769/* S5P6442-specific PLLs. */
770static struct samsung_pll_clock s5p6442_pll_clks[] __initdata = { 770static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
771 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", 771 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
772 APLL_LOCK, APLL_CON0, NULL), 772 APLL_LOCK, APLL_CON0, NULL),
773 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 773 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",