clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7cdb2d61f3e0..f9cbba0eac36 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
         .core_reg = RK2928_CLKSEL_CON(0),
         .div_core_shift = 0,
         .div_core_mask = 0x1f,
+        .mux_core_alt = 1,
+        .mux_core_main = 0,
         .mux_core_shift = 7,
+        .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)                = { "xin24m", "xin24m" };