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authorAnson Huang <anson.huang@nxp.com>2018-11-30 02:23:47 -0500
committerStephen Boyd <sboyd@kernel.org>2018-12-10 14:34:21 -0500
commit0efcc2c0fd2001a83240a8c3d71f67770484917e (patch)
treecc6f33a0d114eb96bcbdab7a937fe874a99bc481 /drivers/clk/imx
parentea662d2f804ad13c3c92c75c7dc1abad30e31c31 (diff)
clk: imx6sl: ensure MMDC CH0 handshake is bypassed
Same as other i.MX6 SoCs, ensure unused MMDC channel's handshake is bypassed, this is to make sure no request signal will be generated when periphe_clk_sel is changed or SRC warm reset is triggered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/clk-imx6sl.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 6fcfbbd907a5..e13d8814cfa4 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -17,6 +17,8 @@
17 17
18#include "clk.h" 18#include "clk.h"
19 19
20#define CCDR 0x4
21#define BM_CCM_CCDR_MMDC_CH0_MASK (1 << 17)
20#define CCSR 0xc 22#define CCSR 0xc
21#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 23#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
22#define CACRR 0x10 24#define CACRR 0x10
@@ -411,6 +413,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
411 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 413 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
412 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 414 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
413 415
416 /* Ensure the MMDC CH0 handshake is bypassed */
417 writel_relaxed(readl_relaxed(base + CCDR) |
418 BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
419
414 imx_check_clocks(clks, ARRAY_SIZE(clks)); 420 imx_check_clocks(clks, ARRAY_SIZE(clks));
415 421
416 clk_data.clks = clks; 422 clk_data.clks = clks;