diff options
author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-07-22 19:20:10 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-08-08 14:29:28 -0400 |
commit | e3afe0e5be7576ac1282ea9fbbc9b352bb379227 (patch) | |
tree | 0b74e8bd5e45b2d50f9fa2033674a00aeac5f6ae /drivers/bcma/driver_chipcommon.c | |
parent | 21e0534ad7415559bb8dee0dc00e39646fed83c9 (diff) |
bcma: add serial console support
This adds support for serial console to bcma, when operating on an SoC.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/bcma/driver_chipcommon.c')
-rw-r--r-- | drivers/bcma/driver_chipcommon.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index acca327db3de..47cce9d69630 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c | |||
@@ -106,3 +106,51 @@ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) | |||
106 | { | 106 | { |
107 | return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); | 107 | return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); |
108 | } | 108 | } |
109 | |||
110 | #ifdef CONFIG_BCMA_DRIVER_MIPS | ||
111 | void bcma_chipco_serial_init(struct bcma_drv_cc *cc) | ||
112 | { | ||
113 | unsigned int irq; | ||
114 | u32 baud_base; | ||
115 | u32 i; | ||
116 | unsigned int ccrev = cc->core->id.rev; | ||
117 | struct bcma_serial_port *ports = cc->serial_ports; | ||
118 | |||
119 | if (ccrev >= 11 && ccrev != 15) { | ||
120 | /* Fixed ALP clock */ | ||
121 | baud_base = bcma_pmu_alp_clock(cc); | ||
122 | if (ccrev >= 21) { | ||
123 | /* Turn off UART clock before switching clocksource. */ | ||
124 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | ||
125 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | ||
126 | & ~BCMA_CC_CORECTL_UARTCLKEN); | ||
127 | } | ||
128 | /* Set the override bit so we don't divide it */ | ||
129 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | ||
130 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | ||
131 | | BCMA_CC_CORECTL_UARTCLK0); | ||
132 | if (ccrev >= 21) { | ||
133 | /* Re-enable the UART clock. */ | ||
134 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | ||
135 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | ||
136 | | BCMA_CC_CORECTL_UARTCLKEN); | ||
137 | } | ||
138 | } else { | ||
139 | pr_err("serial not supported on this device ccrev: 0x%x\n", | ||
140 | ccrev); | ||
141 | return; | ||
142 | } | ||
143 | |||
144 | irq = bcma_core_mips_irq(cc->core); | ||
145 | |||
146 | /* Determine the registers of the UARTs */ | ||
147 | cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); | ||
148 | for (i = 0; i < cc->nr_serial_ports; i++) { | ||
149 | ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + | ||
150 | (i * 256); | ||
151 | ports[i].irq = irq; | ||
152 | ports[i].baud_base = baud_base; | ||
153 | ports[i].reg_shift = 0; | ||
154 | } | ||
155 | } | ||
156 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ | ||