ahci: qoriq: enable snoopable sata read and write

By default the SATA IP on the qoriq SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the
sata axicc register.
In addition, the dma-coherent property must be set on the
SATA controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Signed-off-by: Tejun Heo <tj@kernel.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ed357a184ee4..925c4b6a753b 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -30,17 +30,20 @@
 #define PORT_PHY3       0xB0
 #define PORT_PHY4       0xB4
 #define PORT_PHY5       0xB8
+#define PORT_AXICC      0xBC
 #define PORT_TRANS      0xC8
 
 /* port register default value */
 #define AHCI_PORT_PHY_1_CFG     0xa003fffe
 #define AHCI_PORT_TRANS_CFG     0x08000029
+#define AHCI_PORT_AXICC_CFG     0x3fffffff
 
 /* for ls1021a */
 #define LS1021A_PORT_PHY2       0x28183414
 #define LS1021A_PORT_PHY3       0x0e080e06
 #define LS1021A_PORT_PHY4       0x064a080b
 #define LS1021A_PORT_PHY5       0x2aa86470
+#define LS1021A_AXICC_ADDR      0xC0
 
 #define SATA_ECC_DISABLE        0x00020000
 
@@ -158,16 +161,19 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+                writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
                 break;
 
         case AHCI_LS1043A:
                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+                writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
                 break;
 
         case AHCI_LS2080A:
                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+                writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
                 break;
         }