Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC bug fixes from Arnd Bergmann:
 "Four patches for arm-soc this week:

   - Kevin Hilman is no longer reachable under his previous email
     address.  He submitted the patch earlier, but nobody felt
     responsible to pick it up.

   - One Tegra fix for an incorect register address in device tree.

   - IMX multiplatform support exposes a configuration option that leads
     to unbootable kernels on all other machines and that needs to
     depend on that platform.

   - A nontrivial bug fix for the setup of the mxs video output."

* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  MAINTAINERS: update email address for Kevin Hilman
  ARM: tegra: fix register address of slink controller
  ARM: imx: add dependency check for DEBUG_IMX_UART_PORT
  ARM: video: mxs: Fix mxsfb misconfiguring VDCTRL0

4 files changed, 15 insertions, 14 deletions

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ecfcdba2d17c..9b31f4311ea2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -495,6 +495,7 @@ config DEBUG_IMX_UART_PORT
                                                 DEBUG_IMX53_UART || \
                                                 DEBUG_IMX6Q_UART
         default 1
+        depends on ARCH_MXC
         help
           Choose UART port on which kernel low-level debug messages
           should be output.
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 48d00a099ce3..3d3f64d2111a 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -385,7 +385,7 @@
 
         spi@7000d800 {
                 compatible = "nvidia,tegra20-slink";
-                reg = <0x7000d480 0x200>;
+                reg = <0x7000d800 0x200>;
                 interrupts = <0 83 0x04>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9d87a3ffe998..dbf46c272562 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -372,7 +372,7 @@
 
         spi@7000d800 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
-                reg = <0x7000d480 0x200>;
+                reg = <0x7000d800 0x200>;
                 interrupts = <0 83 0x04>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 3218f1f2c0e0..e7b781d3788f 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -41,8 +41,6 @@ static struct fb_videomode mx23evk_video_modes[] = {
                 .lower_margin   = 4,
                 .hsync_len      = 1,
                 .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
         },
 };
 
@@ -59,8 +57,6 @@ static struct fb_videomode mx28evk_video_modes[] = {
                 .lower_margin   = 10,
                 .hsync_len      = 10,
                 .vsync_len      = 10,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
         },
 };
 
@@ -77,7 +73,6 @@ static struct fb_videomode m28evk_video_modes[] = {
                 .lower_margin   = 45,
                 .hsync_len      = 1,
                 .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
         },
 };
 
@@ -94,9 +89,7 @@ static struct fb_videomode apx4devkit_video_modes[] = {
                 .lower_margin   = 13,
                 .hsync_len      = 48,
                 .vsync_len      = 3,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
-                                  FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
         },
 };
 
@@ -113,9 +106,7 @@ static struct fb_videomode apf28dev_video_modes[] = {
                 .lower_margin = 0x15,
                 .hsync_len = 64,
                 .vsync_len = 4,
-                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
-                                FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                FB_SYNC_DOTCLK_FAILING_ACT,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
         },
 };
 
@@ -132,7 +123,6 @@ static struct fb_videomode cfa10049_video_modes[] = {
                 .lower_margin   = 2,
                 .hsync_len      = 15,
                 .vsync_len      = 15,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT
         },
 };
 
@@ -259,6 +249,8 @@ static void __init imx23_evk_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                MXSFB_SYNC_DOTCLK_FAILING_ACT;
 }
 
 static inline void enable_clk_enet_out(void)
@@ -278,6 +270,8 @@ static void __init imx28_evk_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                MXSFB_SYNC_DOTCLK_FAILING_ACT;
 
         mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
@@ -297,6 +291,7 @@ static void __init m28evk_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
         mxsfb_pdata.default_bpp = 16;
         mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 }
 
 static void __init sc_sps1_init(void)
@@ -322,6 +317,8 @@ static void __init apx4devkit_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                MXSFB_SYNC_DOTCLK_FAILING_ACT;
 }
 
 #define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
@@ -407,6 +404,7 @@ static void __init cfa10049_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 }
 
 static void __init cfa10037_init(void)
@@ -423,6 +421,8 @@ static void __init apf28_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
         mxsfb_pdata.default_bpp = 16;
         mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
+        mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                MXSFB_SYNC_DOTCLK_FAILING_ACT;
 }
 
 static void __init mxs_machine_init(void)