diff options
| author | Michael Holzheu <holzheu@linux.vnet.ibm.com> | 2011-08-03 10:44:21 -0400 |
|---|---|---|
| committer | Heiko Carstens <heiko.carstens@de.ibm.com> | 2011-08-03 10:44:19 -0400 |
| commit | ef1daec8da2c04b0c6e91a34b9cac1aad33c6692 (patch) | |
| tree | 3ce01b3222abccc36ab8b02565c1eed5ebf17442 /arch | |
| parent | e4258d55bff06780cd424c671b576a90acc1592f (diff) | |
[S390] Export store_status() function
For kdump we need a store status function to save the registers for the
current CPU. Therefore this patch exports a function "store_status()".
In addition to that now also floating point registers are saved correctly.
Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/s390/kernel/reipl64.S | 80 |
1 files changed, 60 insertions, 20 deletions
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S index 78eb7cfbd3d1..e690975403f4 100644 --- a/arch/s390/kernel/reipl64.S +++ b/arch/s390/kernel/reipl64.S | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright IBM Corp 2000,2009 | 2 | * Copyright IBM Corp 2000,2011 |
| 3 | * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, | 3 | * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, |
| 4 | * Denis Joseph Barrow, | 4 | * Denis Joseph Barrow, |
| 5 | */ | 5 | */ |
| @@ -8,6 +8,64 @@ | |||
| 8 | #include <asm/asm-offsets.h> | 8 | #include <asm/asm-offsets.h> |
| 9 | 9 | ||
| 10 | # | 10 | # |
| 11 | # store_status | ||
| 12 | # | ||
| 13 | # Prerequisites to run this function: | ||
| 14 | # - Prefix register is set to zero | ||
| 15 | # - Original prefix register is stored in "dump_prefix_page" | ||
| 16 | # - Lowcore protection is off | ||
| 17 | # | ||
| 18 | ENTRY(store_status) | ||
| 19 | /* Save register one and load save area base */ | ||
| 20 | stg %r1,__LC_SAVE_AREA_64(%r0) | ||
| 21 | lghi %r1,SAVE_AREA_BASE | ||
| 22 | /* General purpose registers */ | ||
| 23 | stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 24 | lg %r2,__LC_SAVE_AREA_64(%r0) | ||
| 25 | stg %r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1) | ||
| 26 | /* Control registers */ | ||
| 27 | stctg %c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 28 | /* Access registers */ | ||
| 29 | stam %a0,%a15,__LC_AREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 30 | /* Floating point registers */ | ||
| 31 | std %f0, 0x00 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 32 | std %f1, 0x08 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 33 | std %f2, 0x10 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 34 | std %f3, 0x18 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 35 | std %f4, 0x20 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 36 | std %f5, 0x28 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 37 | std %f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 38 | std %f7, 0x38 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 39 | std %f8, 0x40 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 40 | std %f9, 0x48 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 41 | std %f10,0x50 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 42 | std %f11,0x58 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 43 | std %f12,0x60 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 44 | std %f13,0x68 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 45 | std %f14,0x70 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 46 | std %f15,0x78 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 47 | /* Floating point control register */ | ||
| 48 | stfpc __LC_FP_CREG_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 49 | /* CPU timer */ | ||
| 50 | stpt __LC_CPU_TIMER_SAVE_AREA-SAVE_AREA_BASE(%r1) | ||
| 51 | /* Saved prefix register */ | ||
| 52 | larl %r2,dump_prefix_page | ||
| 53 | mvc __LC_PREFIX_SAVE_AREA-SAVE_AREA_BASE(4,%r1),0(%r2) | ||
| 54 | /* Clock comparator - seven bytes */ | ||
| 55 | larl %r2,.Lclkcmp | ||
| 56 | stckc 0(%r2) | ||
| 57 | mvc __LC_CLOCK_COMP_SAVE_AREA-SAVE_AREA_BASE + 1(7,%r1),1(%r2) | ||
| 58 | /* Program status word */ | ||
| 59 | epsw %r2,%r3 | ||
| 60 | st %r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 0(%r1) | ||
| 61 | st %r3,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 4(%r1) | ||
| 62 | larl %r2,store_status | ||
| 63 | stg %r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 8(%r1) | ||
| 64 | br %r14 | ||
| 65 | .align 8 | ||
| 66 | .Lclkcmp: .quad 0x0000000000000000 | ||
| 67 | |||
| 68 | # | ||
| 11 | # do_reipl_asm | 69 | # do_reipl_asm |
| 12 | # Parameter: r2 = schid of reipl device | 70 | # Parameter: r2 = schid of reipl device |
| 13 | # | 71 | # |
| @@ -15,22 +73,7 @@ | |||
| 15 | ENTRY(do_reipl_asm) | 73 | ENTRY(do_reipl_asm) |
| 16 | basr %r13,0 | 74 | basr %r13,0 |
| 17 | .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13) | 75 | .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13) |
| 18 | .Lpg1: # do store status of all registers | 76 | .Lpg1: brasl %r14,store_status |
| 19 | |||
| 20 | stg %r1,.Lregsave-.Lpg0(%r13) | ||
| 21 | lghi %r1,0x1000 | ||
| 22 | stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1) | ||
| 23 | lg %r0,.Lregsave-.Lpg0(%r13) | ||
| 24 | stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1) | ||
| 25 | stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1) | ||
| 26 | stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1) | ||
| 27 | lg %r10,.Ldump_pfx-.Lpg0(%r13) | ||
| 28 | mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10) | ||
| 29 | stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1) | ||
| 30 | stckc .Lclkcmp-.Lpg0(%r13) | ||
| 31 | mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(7,%r1),.Lclkcmp-.Lpg0(%r13) | ||
| 32 | stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1) | ||
| 33 | stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1) | ||
| 34 | 77 | ||
| 35 | lctlg %c6,%c6,.Lall-.Lpg0(%r13) | 78 | lctlg %c6,%c6,.Lall-.Lpg0(%r13) |
| 36 | lgr %r1,%r2 | 79 | lgr %r1,%r2 |
| @@ -67,10 +110,7 @@ ENTRY(do_reipl_asm) | |||
| 67 | st %r14,.Ldispsw+12-.Lpg0(%r13) | 110 | st %r14,.Ldispsw+12-.Lpg0(%r13) |
| 68 | lpswe .Ldispsw-.Lpg0(%r13) | 111 | lpswe .Ldispsw-.Lpg0(%r13) |
| 69 | .align 8 | 112 | .align 8 |
| 70 | .Lclkcmp: .quad 0x0000000000000000 | ||
| 71 | .Lall: .quad 0x00000000ff000000 | 113 | .Lall: .quad 0x00000000ff000000 |
| 72 | .Ldump_pfx: .quad dump_prefix_page | ||
| 73 | .Lregsave: .quad 0x0000000000000000 | ||
| 74 | .align 16 | 114 | .align 16 |
| 75 | /* | 115 | /* |
| 76 | * These addresses have to be 31 bit otherwise | 116 | * These addresses have to be 31 bit otherwise |
