Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...

351 files changed, 8651 insertions, 18671 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 31b17f3fe2b4..e60718b4b96d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -531,21 +531,6 @@ config ARCH_DOVE
         help
           Support for the Marvell Dove SoC 88AP510
 
-config ARCH_KIRKWOOD
-        bool "Marvell Kirkwood"
-        select ARCH_REQUIRE_GPIOLIB
-        select CPU_FEROCEON
-        select GENERIC_CLOCKEVENTS
-        select MVEBU_MBUS
-        select PCI
-        select PCI_QUIRKS
-        select PINCTRL
-        select PINCTRL_KIRKWOOD
-        select PLAT_ORION_LEGACY
-        help
-          Support for the following Marvell Kirkwood series SoCs:
-          88F6180, 88F6192 and 88F6281.
-
 config ARCH_MV78XX0
         bool "Marvell MV78xx0"
         select ARCH_REQUIRE_GPIOLIB
@@ -762,24 +747,6 @@ config ARCH_S3C64XX
         help
           Samsung S3C64XX series based systems
 
-config ARCH_S5PV210
-        bool "Samsung S5PV210/S5PC110"
-        select ARCH_HAS_HOLES_MEMORYMODEL
-        select ARCH_SPARSEMEM_ENABLE
-        select ATAGS
-        select CLKDEV_LOOKUP
-        select CLKSRC_SAMSUNG_PWM
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select GPIO_SAMSUNG
-        select HAVE_S3C2410_I2C if I2C
-        select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_MEMORY_H
-        select SAMSUNG_ATAGS
-        help
-          Samsung S5PV210/S5PC110 series based systems
-
 config ARCH_DAVINCI
         bool "TI DaVinci"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -918,8 +885,6 @@ source "arch/arm/mach-ixp4xx/Kconfig"
 
 source "arch/arm/mach-keystone/Kconfig"
 
-source "arch/arm/mach-kirkwood/Kconfig"
-
 source "arch/arm/mach-ks8695/Kconfig"
 
 source "arch/arm/mach-msm/Kconfig"
@@ -930,6 +895,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"
 
+source "arch/arm/mach-mediatek/Kconfig"
+
 source "arch/arm/mach-mxs/Kconfig"
 
 source "arch/arm/mach-netx/Kconfig"
@@ -1517,7 +1484,8 @@ config ARM_PSCI
 config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
+        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
+                SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
         default 416 if ARCH_SUNXI
         default 392 if ARCH_U8500
         default 352 if ARCH_VT8500
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b24b5dc720e4..edaf62737bc2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -223,6 +223,14 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on HI3716 UART.
 
+        config DEBUG_HIX5HD2_UART
+                bool "Hisilicon Hix5hd2 Debug UART"
+                depends on ARCH_HIX5HD2
+                select DEBUG_UART_PL01X
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Hix5hd2 UART.
+
         config DEBUG_HIGHBANK_UART
                 bool "Kernel low-level debugging messages via Highbank UART"
                 depends on ARCH_HIGHBANK
@@ -617,6 +625,7 @@ choice
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
+                select DEBUG_S5PV210_UART if ARCH_S5PV210
                 bool "Use Samsung S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -627,6 +636,7 @@ choice
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
+                select DEBUG_S5PV210_UART if ARCH_S5PV210
                 bool "Use Samsung S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -637,6 +647,7 @@ choice
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
+                select DEBUG_S5PV210_UART if ARCH_S5PV210
                 bool "Use Samsung S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -644,8 +655,9 @@ choice
                   by the boot-loader before use.
 
         config DEBUG_S3C_UART3
-                depends on PLAT_SAMSUNG && ARCH_EXYNOS
-                select DEBUG_EXYNOS_UART
+                depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210)
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S5PV210_UART if ARCH_S5PV210
                 bool "Use Samsung S3C UART 3 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -703,6 +715,14 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on Allwinner A1X based platforms on the UART1.
 
+        config DEBUG_SUNXI_R_UART
+                bool "Kernel low-level debugging messages via sunXi R_UART"
+                depends on MACH_SUN6I || MACH_SUN8I
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A31/A23 based platforms on the R_UART.
+
         config TEGRA_DEBUG_UART_AUTO_ODMDATA
                 bool "Kernel low-level debugging messages via Tegra UART via ODMDATA"
                 depends on ARCH_TEGRA
@@ -937,6 +957,9 @@ config DEBUG_S3C2410_UART
 config DEBUG_S3C24XX_UART
         bool
 
+config DEBUG_S5PV210_UART
+        bool
+
 config DEBUG_OMAP2PLUS_UART
         bool
         depends on ARCH_OMAP2PLUS
@@ -998,6 +1021,7 @@ config DEBUG_LL_INCLUDE
         default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
         default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
+        default "debug/s5pv210.S" if DEBUG_S5PV210_UART
         default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
         default "debug/sti.S" if DEBUG_STI_UART
         default "debug/tegra.S" if DEBUG_TEGRA_UART
@@ -1022,7 +1046,7 @@ config DEBUG_UART_8250
         def_bool ARCH_DOVE || ARCH_EBSA110 || \
                 (FOOTBRIDGE && !DEBUG_DC21285_PORT) || \
                 ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \
-                ARCH_IOP33X || ARCH_IXP4XX || ARCH_KIRKWOOD || \
+                ARCH_IOP33X || ARCH_IXP4XX || \
                 ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
 
 config DEBUG_UART_PHYS
@@ -1032,6 +1056,7 @@ config DEBUG_UART_PHYS
         default 0x01c28400 if DEBUG_SUNXI_UART1
         default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1
         default 0x01d0d000 if DEBUG_DAVINCI_DA8XX_UART2
+        default 0x01f02800 if DEBUG_SUNXI_R_UART
         default 0x02530c00 if DEBUG_KEYSTONE_UART0
         default 0x02531000 if DEBUG_KEYSTONE_UART1
         default 0x03010fe0 if ARCH_RPC
@@ -1078,10 +1103,10 @@ config DEBUG_UART_PHYS
         default 0xe0000000 if ARCH_SPEAR13XX
         default 0xf0000be0 if ARCH_EBSA110
         default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
-        default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
+        default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
                                 ARCH_ORION5X
         default 0xf7fc9000 if DEBUG_BERLIN_UART
-        default 0xf8b00000 if DEBUG_HI3716_UART
+        default 0xf8b00000 if DEBUG_HIX5HD2_UART
         default 0xf991e000 if DEBUG_QCOM_UARTDM
         default 0xfcb00000 if DEBUG_HI3620_UART
         default 0xfe800000 if ARCH_IOP32X
@@ -1107,6 +1132,7 @@ config DEBUG_UART_VIRT
         default 0xf1600000 if ARCH_INTEGRATOR
         default 0xf1c28000 if DEBUG_SUNXI_UART0
         default 0xf1c28400 if DEBUG_SUNXI_UART1
+        default 0xf1f02800 if DEBUG_SUNXI_R_UART
         default 0xf2100000 if DEBUG_PXA_UART1
         default 0xf4090000 if ARCH_LPC32XX
         default 0xf4200000 if ARCH_GEMINI
@@ -1133,7 +1159,7 @@ config DEBUG_UART_VIRT
         default 0xfe230000 if DEBUG_PICOXCELL_UART
         default 0xfe300000 if DEBUG_BCM_KONA_UART
         default 0xfe800000 if ARCH_IOP32X
-        default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART
+        default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
         default 0xfeb24000 if DEBUG_RK3X_UART0
         default 0xfeb26000 if DEBUG_RK3X_UART1
         default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
@@ -1143,7 +1169,6 @@ config DEBUG_UART_VIRT
         default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
         default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
         default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
-        default 0xfed12000 if ARCH_KIRKWOOD
         default 0xfed60000 if DEBUG_RK29_UART0
         default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
         default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1e42de45110b..0ce9d0f71f2a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -159,14 +159,13 @@ machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
 machine-$(CONFIG_ARCH_EXYNOS)           += exynos
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
-machine-$(CONFIG_ARCH_HI3xxx)           += hisi
+machine-$(CONFIG_ARCH_HISI)             += hisi
 machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
 machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
 machine-$(CONFIG_ARCH_IOP32X)           += iop32x
 machine-$(CONFIG_ARCH_IOP33X)           += iop33x
 machine-$(CONFIG_ARCH_IXP4XX)           += ixp4xx
 machine-$(CONFIG_ARCH_KEYSTONE)         += keystone
-machine-$(CONFIG_ARCH_KIRKWOOD)         += kirkwood
 machine-$(CONFIG_ARCH_KS8695)           += ks8695
 machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
 machine-$(CONFIG_ARCH_MMP)              += mmp
@@ -175,6 +174,7 @@ machine-$(CONFIG_ARCH_MSM)		+= msm
 machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_MXC)              += imx
+machine-$(CONFIG_ARCH_MEDIATEK)         += mediatek
 machine-$(CONFIG_ARCH_MXS)              += mxs
 machine-$(CONFIG_ARCH_NETX)             += netx
 machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
@@ -213,11 +213,11 @@ machine-$(CONFIG_PLAT_SPEAR)		+= spear
 plat-$(CONFIG_ARCH_EXYNOS)      += samsung
 plat-$(CONFIG_ARCH_OMAP)        += omap
 plat-$(CONFIG_ARCH_S3C64XX)     += samsung
+plat-$(CONFIG_ARCH_S5PV210)     += samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
 plat-$(CONFIG_PLAT_ORION)       += orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
 plat-$(CONFIG_PLAT_S3C24XX)     += samsung
-plat-$(CONFIG_PLAT_S5P)         += samsung
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
@@ -241,7 +241,7 @@ MACHINE  :=
 endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
-platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
+platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
 
 ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9e269e..74f2906211a9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos5440-ssdk5440.dtb \
         exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
         ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@@ -90,8 +91,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
 dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
         k2l-evm.dtb \
         k2e-evm.dtb
-kirkwood := \
-        kirkwood-b3.dtb \
+dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
         kirkwood-cloudbox.dtb \
         kirkwood-db-88f6281.dtb \
         kirkwood-db-88f6282.dtb \
@@ -150,8 +150,6 @@ kirkwood := \
         kirkwood-ts219-6282.dtb \
         kirkwood-ts419-6281.dtb \
         kirkwood-ts419-6282.dtb
-dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
-dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
@@ -321,13 +319,17 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
         s3c6410-smdk6410.dtb
+dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
+        s5pv210-goni.dtb \
+        s5pv210-smdkc110.dtb \
+        s5pv210-smdkv210.dtb \
+        s5pv210-torbreck.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
         r8a7778-bockw-reference.dtb \
         r8a7740-armadillo800eva-reference.dtb \
         r8a7779-marzen.dtb \
-        r8a7779-marzen-reference.dtb \
         r8a7791-koelsch.dtb \
         r8a7790-lager.dtb \
         sh73a0-kzm9g.dtb \
@@ -339,7 +341,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
         r7s72100-genmai.dtb \
         r8a7791-henninger.dtb \
         r8a7791-koelsch.dtb \
-        r8a7790-lager.dtb
+        r8a7790-lager.dtb \
+        r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 4a4e02d0ce9e..3a0a161342ba 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -347,6 +347,15 @@
                         status = "disabled";
                 };
 
+                mailbox: mailbox@480C8000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x480C8000 0x200>;
+                        interrupts = <77>;
+                        ti,hwmods = "mailbox";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <8>;
+                };
+
                 timer1: timer@44e31000 {
                         compatible = "ti,am335x-timer-1ms";
                         reg = <0x44e31000 0x400>;
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 49fa59622254..c9aee0e799bb 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -168,9 +168,6 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <8>;
-                        ti,mbox-names = "wkup_m3";
-                        ti,mbox-data = <0 0 0 0>;
-                        status = "disabled";
                 };
 
                 timer1: timer@44e31000 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 80127638b379..0686b1e9e7f9 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -338,6 +338,123 @@
                         status = "disabled";
                 };
 
+                mailbox1: mailbox@4a0f4000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4a0f4000 0x200>;
+                        ti,hwmods = "mailbox1";
+                        ti,mbox-num-users = <3>;
+                        ti,mbox-num-fifos = <8>;
+                        status = "disabled";
+                };
+
+                mailbox2: mailbox@4883a000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4883a000 0x200>;
+                        ti,hwmods = "mailbox2";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox3: mailbox@4883c000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4883c000 0x200>;
+                        ti,hwmods = "mailbox3";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox4: mailbox@4883e000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4883e000 0x200>;
+                        ti,hwmods = "mailbox4";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox5: mailbox@48840000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48840000 0x200>;
+                        ti,hwmods = "mailbox5";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox6: mailbox@48842000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48842000 0x200>;
+                        ti,hwmods = "mailbox6";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox7: mailbox@48844000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48844000 0x200>;
+                        ti,hwmods = "mailbox7";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox8: mailbox@48846000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48846000 0x200>;
+                        ti,hwmods = "mailbox8";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox9: mailbox@4885e000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4885e000 0x200>;
+                        ti,hwmods = "mailbox9";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox10: mailbox@48860000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48860000 0x200>;
+                        ti,hwmods = "mailbox10";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox11: mailbox@48862000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48862000 0x200>;
+                        ti,hwmods = "mailbox11";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox12: mailbox@48864000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48864000 0x200>;
+                        ti,hwmods = "mailbox12";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
+                mailbox13: mailbox@48802000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x48802000 0x200>;
+                        ti,hwmods = "mailbox13";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <12>;
+                        status = "disabled";
+                };
+
                 timer1: timer@4ae18000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4ae18000 0x80>;
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 83a5b8685bd9..6cbb62e5c6a9 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -33,6 +33,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "hisilicon,hi3620-smp";
 
                 cpu@0 {
                         device_type = "cpu";
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
new file mode 100644
index 000000000000..05b44c272c9a
--- /dev/null
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "hisi-x5hd2.dtsi"
+
+/ {
+        model = "Hisilicon HIX5HD2 Development Board";
+        compatible = "hisilicon,hix5hd2";
+
+        chosen {
+                bootargs = "console=ttyAMA0,115200 earlyprintk";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "hisilicon,hix5hd2-smp";
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&l2>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&l2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>;
+        };
+};
+
+&timer0 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
new file mode 100644
index 000000000000..f85ba2924ff7
--- /dev/null
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hix5hd2-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart0;
+        };
+
+        gic: interrupt-controller@f8a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                /* gic dist base, gic cpu base */
+                reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0 0xf8000000 0x8000000>;
+
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "arm,amba-bus";
+                        ranges;
+
+                        timer0: timer@00002000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x00002000 0x1000>;
+                                /* timer00 & timer01 */
+                                interrupts = <0 24 4>;
+                                clocks = <&clock HIX5HD2_FIXED_24M>;
+                                status = "disabled";
+                        };
+
+                        timer1: timer@00a29000 {
+                                /*
+                                 * Only used in NORMAL state, not available ins
+                                 * SLOW or DOZE state.
+                                 * The rate is fixed in 24MHz.
+                                 */
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x00a29000 0x1000>;
+                                /* timer10 & timer11 */
+                                interrupts = <0 25 4>;
+                                clocks = <&clock HIX5HD2_FIXED_24M>;
+                                status = "disabled";
+                        };
+
+                        timer2: timer@00a2a000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x00a2a000 0x1000>;
+                                /* timer20 & timer21 */
+                                interrupts = <0 26 4>;
+                                clocks = <&clock HIX5HD2_FIXED_24M>;
+                                status = "disabled";
+                        };
+
+                        timer3: timer@00a2b000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x00a2b000 0x1000>;
+                                /* timer30 & timer31 */
+                                interrupts = <0 27 4>;
+                                clocks = <&clock HIX5HD2_FIXED_24M>;
+                                status = "disabled";
+                        };
+
+                        timer4: timer@00a81000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x00a81000 0x1000>;
+                                /* timer30 & timer31 */
+                                interrupts = <0 28 4>;
+                                clocks = <&clock HIX5HD2_FIXED_24M>;
+                                status = "disabled";
+                        };
+
+                        uart0: uart@00b00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x00b00000 0x1000>;
+                                interrupts = <0 49 4>;
+                                clocks = <&clock HIX5HD2_FIXED_83M>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+
+                        uart1: uart@00006000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x00006000 0x1000>;
+                                interrupts = <0 50 4>;
+                                clocks = <&clock HIX5HD2_FIXED_83M>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+
+                        uart2: uart@00b02000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x00b02000 0x1000>;
+                                interrupts = <0 51 4>;
+                                clocks = <&clock HIX5HD2_FIXED_83M>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+
+                        uart3: uart@00b03000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x00b03000 0x1000>;
+                                interrupts = <0 52 4>;
+                                clocks = <&clock HIX5HD2_FIXED_83M>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+
+                        uart4: uart@00b04000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb04000 0x1000>;
+                                interrupts = <0 53 4>;
+                                clocks = <&clock HIX5HD2_FIXED_83M>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                };
+
+                local_timer@00a00600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x00a00600 0x20>;
+                        interrupts = <1 13 0xf01>;
+                };
+
+                l2: l2-cache {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a10000 0x100000>;
+                        interrupts = <0 15 4>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                sysctrl: system-controller@00000000 {
+                        compatible = "hisilicon,sysctrl";
+                        reg = <0x00000000 0x1000>;
+                        reboot-offset = <0x4>;
+                };
+
+                cpuctrl@00a22000 {
+                        compatible = "hisilicon,cpuctrl";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00a22000 0x2000>;
+                        ranges = <0 0x00a22000 0x2000>;
+
+                        clock: clock@0 {
+                                compatible = "hisilicon,hix5hd2-clock";
+                                reg = <0 0x2000>;
+                                #clock-cells = <1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
new file mode 100644
index 000000000000..443b4467de15
--- /dev/null
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <matthias.bgg@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt6589.dtsi"
+
+/ {
+        model = "bq Aquaris5";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
new file mode 100644
index 000000000000..d0297a051549
--- /dev/null
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <matthias.bgg@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "mediatek,mt6589";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x3>;
+                };
+
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+
+                system_clk: dummy13m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                rtc_clk: dummy32k {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                        #clock-cells = <0>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+
+                timer: timer@10008000 {
+                        compatible = "mediatek,mt6577-timer";
+                        reg = <0x10008000 0x80>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&system_clk>, <&rtc_clk>;
+                        clock-names = "system-clk", "rtc-clk";
+                };
+
+                gic: interrupt-controller@10212000 {
+                        compatible = "arm,cortex-a15-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x10211000 0x1000>,
+                              <0x10212000 0x1000>,
+                              <0x10214000 0x2000>,
+                              <0x10216000 0x2000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e83b0468080c..6d21994d824b 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,8 @@
                         interrupts = <26>, <34>;
                         interrupt-names = "dsp", "iva";
                         ti,hwmods = "mailbox";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <6>;
                 };
 
                 timer1: timer@48028000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index c4e8013801ee..aa6a354e236f 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,8 @@
                         reg = <0x48094000 0x200>;
                         interrupts = <26>;
                         ti,hwmods = "mailbox";
+                        ti,mbox-num-users = <4>;
+                        ti,mbox-num-fifos = <6>;
                 };
 
                 timer1: timer@49018000 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index b2891a9a6975..575a49bf968d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -332,6 +332,8 @@
                         ti,hwmods = "mailbox";
                         reg = <0x48094000 0x200>;
                         interrupts = <26>;
+                        ti,mbox-num-users = <2>;
+                        ti,mbox-num-fifos = <2>;
                 };
 
                 mcspi1: spi@48098000 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 7e26d222bfe3..69408b53200d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -649,6 +649,15 @@
                         };
                 };
 
+                mailbox: mailbox@4a0f4000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4a0f4000 0x200>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mailbox";
+                        ti,mbox-num-users = <3>;
+                        ti,mbox-num-fifos = <8>;
+                };
+
                 timer1: timer@4a318000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x4a318000 0x80>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 8eee6fbef7ad..fc8df1739f39 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -640,6 +640,8 @@
                         reg = <0x4a0f4000 0x200>;
                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox";
+                        ti,mbox-num-users = <3>;
+                        ti,mbox-num-fifos = <8>;
                 };
 
                 timer1: timer@4ae18000 {
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index b27c6373ff4d..000000000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-        model = "marzen";
-        compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-        chosen {
-                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x60000000 0x40000000>;
-        };
-
-        fixedregulator3v3: fixedregulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-3.3V";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-boot-on;
-                regulator-always-on;
-        };
-
-        lan0@18000000 {
-                compatible = "smsc,lan9220", "smsc,lan9115";
-                reg = <0x18000000 0x100>;
-                pinctrl-0 = <&lan0_pins>;
-                pinctrl-names = "default";
-
-                phy-mode = "mii";
-                interrupt-parent = <&irqpin0>;
-                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-                smsc,irq-push-pull;
-                reg-io-width = <4>;
-                vddvario-supply = <&fixedregulator3v3>;
-                vdd33a-supply = <&fixedregulator3v3>;
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                led2 {
-                        gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-                };
-                led3 {
-                        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-                };
-                led4 {
-                        gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-                };
-        };
-};
-
-&irqpin0 {
-        status = "okay";
-};
-
-&pfc {
-        pinctrl-0 = <&scif2_pins &scif4_pins>;
-        pinctrl-names = "default";
-
-        lan0_pins: lan0 {
-                intc {
-                        renesas,groups = "intc_irq1_b";
-                        renesas,function = "intc";
-                };
-                lbsc {
-                        renesas,groups = "lbsc_ex_cs0";
-                        renesas,function = "lbsc";
-                };
-        };
-
-        scif2_pins: serial2 {
-                renesas,groups = "scif2_data_c";
-                renesas,function = "scif2";
-        };
-
-        scif4_pins: serial4 {
-                renesas,groups = "scif4_data";
-                renesas,function = "scif4";
-        };
-
-        sdhi0_pins: sd0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-                renesas,function = "sdhi0";
-        };
-
-        hspi0_pins: hspi0 {
-                renesas,groups = "hspi0";
-                renesas,function = "hspi0";
-        };
-};
-
-&sdhi0 {
-        pinctrl-0 = <&sdhi0_pins>;
-        pinctrl-names = "default";
-
-        vmmc-supply = <&fixedregulator3v3>;
-        bus-width = <4>;
-        status = "okay";
-};
-
-&hspi0 {
-        pinctrl-0 = <&hspi0_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2371f2..5745555df943 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,17 +11,131 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "marzen";
         compatible = "renesas,marzen", "renesas,r8a7779";
 
+        aliases {
+                serial2 = &scif2;
+                serial4 = &scif4;
+        };
+
         chosen {
-                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
+                bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
         };
 
         memory {
                 device_type = "memory";
                 reg = <0x60000000 0x40000000>;
         };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        lan0@18000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x18000000 0x100>;
+                pinctrl-0 = <&lan0_pins>;
+                pinctrl-names = "default";
+
+                phy-mode = "mii";
+                interrupt-parent = <&irqpin0>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                smsc,irq-push-pull;
+                reg-io-width = <4>;
+                vddvario-supply = <&fixedregulator3v3>;
+                vdd33a-supply = <&fixedregulator3v3>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led2 {
+                        gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+                };
+                led3 {
+                        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+                };
+                led4 {
+                        gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&irqpin0 {
+        status = "okay";
+};
+
+&extal_clk {
+        clock-frequency = <31250000>;
+};
+
+&pfc {
+        lan0_pins: lan0 {
+                intc {
+                        renesas,groups = "intc_irq1_b";
+                        renesas,function = "intc";
+                };
+                lbsc {
+                        renesas,groups = "lbsc_ex_cs0";
+                        renesas,function = "lbsc";
+                };
+        };
+
+        scif2_pins: serial2 {
+                renesas,groups = "scif2_data_c";
+                renesas,function = "scif2";
+        };
+
+        scif4_pins: serial4 {
+                renesas,groups = "scif4_data";
+                renesas,function = "scif4";
+        };
+
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+                renesas,function = "sdhi0";
+        };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0";
+                renesas,function = "hspi0";
+        };
+};
+
+&scif2 {
+        pinctrl-0 = <&scif2_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&scif4 {
+        pinctrl-0 = <&scif4_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b517c8e6b420..94e2fc836492 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -25,21 +26,25 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <2>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <3>;
+                        clock-frequency = <1000000000>;
                 };
         };
 
@@ -157,6 +162,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc70000 0x1000>;
                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
                 status = "disabled";
         };
 
@@ -166,6 +172,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc71000 0x1000>;
                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
                 status = "disabled";
         };
 
@@ -175,6 +182,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc72000 0x1000>;
                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
                 status = "disabled";
         };
 
@@ -184,6 +192,67 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc73000 0x1000>;
                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
+                status = "disabled";
+        };
+
+        scif0: serial@ffe40000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe40000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif1: serial@ffe41000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe41000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif2: serial@ffe42000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe42000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif3: serial@ffe43000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe43000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif4: serial@ffe44000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe44000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif5: serial@ffe45000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe45000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -201,12 +270,14 @@
                 compatible = "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7779_CLK_SATA>;
         };
 
         sdhi0: sd@ffe4c000 {
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4c000 0x100>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -216,6 +287,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4d000 0x100>;
                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -225,6 +297,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4e000 0x100>;
                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -234,6 +307,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4f000 0x100>;
                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -245,6 +319,7 @@
                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
 
@@ -254,6 +329,7 @@
                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
 
@@ -263,6 +339,150 @@
                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: clocks@ffc80000 {
+                        compatible = "renesas,r8a7779-cpg-clocks";
+                        reg = <0xffc80000 0x30>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "plla", "z", "zs", "s",
+                                             "s1", "p", "b", "out";
+                };
+
+                /* Fixed factor clocks */
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                s3_clk: s3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "s3";
+                };
+                s4_clk: s4_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <16>;
+                        clock-mult = <1>;
+                        clock-output-names = "s4";
+                };
+                g_clk: g_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "g";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: clocks@ffc80030 {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80030 4>;
+                        clocks = <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_HSPI R8A7779_CLK_TMU2
+                                R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
+                                R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
+                                R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+                                R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
+                                R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
+                                R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+                                R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
+                                "hscif0", "scif5", "scif4", "scif3", "scif2",
+                                "scif1", "scif0", "i2c3", "i2c2", "i2c1",
+                                "i2c0";
+                };
+                mstp1_clks: clocks@ffc80034 {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80034 4>, <0xffc80044 4>;
+                        clocks = <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_USB01 R8A7779_CLK_USB2
+                                R8A7779_CLK_DU R8A7779_CLK_VIN2
+                                R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+                                R8A7779_CLK_ETHER R8A7779_CLK_SATA
+                                R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+                        >;
+                        clock-output-names =
+                                "usb01", "usb2",
+                                "du", "vin2",
+                                "vin1", "vin0",
+                                "ether", "sata",
+                                "pcie", "vin3";
+                };
+                mstp3_clks: clocks@ffc8003c {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc8003c 4>;
+                        clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
+                                 <&s4_clk>, <&s4_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+                                R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+                                R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+                        >;
+                        clock-output-names =
+                                "sdhi3", "sdhi2", "sdhi1", "sdhi0",
+                                "mmc1", "mmc0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
new file mode 100644
index 000000000000..aa31b84a707a
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -0,0 +1,392 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Board device tree source for Samsung Aquila board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "s5pv210.dtsi"
+
+/ {
+        model = "Samsung Aquila based on S5PC110";
+        compatible = "samsung,aquila", "samsung,s5pv210";
+
+        aliases {
+                i2c3 = &i2c_pmic;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x30000000 0x05000000
+                        0x40000000 0x18000000>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vtf_reg: fixed-regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "V_TF_2.8V";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpios = <&mp05 4 0>;
+                        enable-active-high;
+                };
+
+                pda_reg: fixed-regulator@1 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VCC_1.8V_PDA";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        reg = <1>;
+                };
+
+                bat_reg: fixed-regulator@2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "V_BAT";
+                        regulator-min-microvolt = <3700000>;
+                        regulator-max-microvolt = <3700000>;
+                        reg = <2>;
+                };
+        };
+
+        i2c_pmic: i2c-pmic {
+                compatible = "i2c-gpio";
+                gpios = <&gpj4 0 0>, /* sda */
+                        <&gpj4 3 0>; /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pmic@66 {
+                        compatible = "national,lp3974";
+                        reg = <0x66>;
+
+                        max8998,pmic-buck1-default-dvs-idx = <0>;
+                        max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
+                                                        <&gph0 4 0>;
+                        max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
+                                                        <1200000>, <1200000>;
+
+                        max8998,pmic-buck2-default-dvs-idx = <0>;
+                        max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
+                        max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
+
+                        regulators {
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VALIVE_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VUSB+MIPI_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VADC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VTF_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VCC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VCC_3.0V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VUSB+VDAC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VCC+VCAM_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VPLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "CAM_IO_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "CAM_ISP_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "CAM_A_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "CAM_CIF_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "CAM_AF_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VMIPI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "CAM_8M_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "VARM_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "VINT_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "VCC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "CAM_CORE_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                vichg_reg: ENVICHG {
+                                        regulator-name = "VICHG";
+                                };
+
+                                safeout1_reg: ESAFEOUT1 {
+                                        regulator-name = "SAFEOUT1";
+                                        regulator-always-on;
+                                };
+
+                                safeout2_reg: ESAFEOUT2 {
+                                        regulator-name = "SAFEOUT2";
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power-key {
+                        gpios = <&gph2 6 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power";
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&keypad {
+        linux,input-no-autorepeat;
+        linux,input-wakeup;
+        samsung,keypad-num-rows = <3>;
+        samsung,keypad-num-columns = <3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
+                        <&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
+        status = "okay";
+
+        key_1 {
+                keypad,row = <0>;
+                keypad,column = <1>;
+                linux,code = <KEY_CONNECT>;
+        };
+
+        key_2 {
+                keypad,row = <0>;
+                keypad,column = <2>;
+                linux,code = <KEY_BACK>;
+        };
+
+        key_3 {
+                keypad,row = <1>;
+                keypad,column = <1>;
+                linux,code = <KEY_CAMERA_FOCUS>;
+        };
+
+        key_4 {
+                keypad,row = <1>;
+                keypad,column = <2>;
+                linux,code = <KEY_VOLUMEUP>;
+        };
+
+        key_5 {
+                keypad,row = <2>;
+                keypad,column = <1>;
+                linux,code = <KEY_CAMERA>;
+        };
+
+        key_6 {
+                keypad,row = <2>;
+                keypad,column = <2>;
+                linux,code = <KEY_VOLUMEDOWN>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&sdhci0 {
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+        vmmc-supply = <&ldo5_reg>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
+        pinctrl-names = "default";
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gph3 4 1>;
+        vmmc-supply = <&vtf_reg>;
+        cd-inverted;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&onenand {
+        status = "okay";
+};
+
+&hsotg {
+        vusb_a-supply = <&ldo3_reg>;
+        vusb_d-supply = <&ldo8_reg>;
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&fimd {
+        pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        clock-frequency = <0>;
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <16>;
+                        hback-porch = <16>;
+                        hsync-len = <2>;
+                        vback-porch = <3>;
+                        vfront-porch = <28>;
+                        vsync-len = <1>;
+                };
+        };
+};
+
+&pinctrl0 {
+        t_flash_detect: t-flash-detect {
+                samsung,pins = "gph3-4";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
new file mode 100644
index 000000000000..6387c77a6f7b
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -0,0 +1,449 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Board device tree source for Samsung Goni board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "s5pv210.dtsi"
+
+/ {
+        model = "Samsung Goni based on S5PC110";
+        compatible = "samsung,goni", "samsung,s5pv210";
+
+        aliases {
+                i2c3 = &i2c_pmic;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x30000000 0x05000000
+                        0x40000000 0x10000000
+                        0x50000000 0x08000000>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vtf_reg: fixed-regulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "V_TF_2.8V";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        reg = <0>;
+                        gpios = <&mp05 4 0>;
+                        enable-active-high;
+                };
+
+                pda_reg: fixed-regulator@1 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VCC_1.8V_PDA";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        reg = <1>;
+                };
+
+                bat_reg: fixed-regulator@2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "V_BAT";
+                        regulator-min-microvolt = <3700000>;
+                        regulator-max-microvolt = <3700000>;
+                        reg = <2>;
+                };
+
+                tsp_reg: fixed-regulator@3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "TSP_VDD";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        reg = <3>;
+                        gpios = <&gpj1 3 0>;
+                        enable-active-high;
+                };
+        };
+
+        i2c_pmic: i2c-pmic {
+                compatible = "i2c-gpio";
+                gpios = <&gpj4 0 0>, /* sda */
+                        <&gpj4 3 0>; /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pmic@66 {
+                        compatible = "national,lp3974";
+                        reg = <0x66>;
+
+                        max8998,pmic-buck1-default-dvs-idx = <0>;
+                        max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
+                                                        <&gph0 4 0>;
+                        max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
+                                                        <1200000>, <1200000>;
+
+                        max8998,pmic-buck2-default-dvs-idx = <0>;
+                        max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
+                        max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
+
+                        regulators {
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VALIVE_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VUSB+MIPI_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VADC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VTF_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VCC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VLCD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VUSB+VDAC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VCC+VCAM_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VPLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-boot-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "CAM_IO_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "CAM_ISP_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "CAM_A_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "CAM_CIF_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "CAM_AF_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VMIPI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "CAM_8M_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "VARM_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "VINT_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "VCC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "CAM_CORE_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power-key {
+                        gpios = <&gph2 6 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power";
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&keypad {
+        linux,input-no-autorepeat;
+        linux,input-wakeup;
+        samsung,keypad-num-rows = <3>;
+        samsung,keypad-num-columns = <3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
+                        <&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
+        status = "okay";
+
+        key_1 {
+                keypad,row = <0>;
+                keypad,column = <1>;
+                linux,code = <KEY_CONNECT>;
+        };
+
+        key_2 {
+                keypad,row = <0>;
+                keypad,column = <2>;
+                linux,code = <KEY_BACK>;
+        };
+
+        key_3 {
+                keypad,row = <1>;
+                keypad,column = <1>;
+                linux,code = <KEY_CAMERA_FOCUS>;
+        };
+
+        key_4 {
+                keypad,row = <1>;
+                keypad,column = <2>;
+                linux,code = <KEY_VOLUMEUP>;
+        };
+
+        key_5 {
+                keypad,row = <2>;
+                keypad,column = <1>;
+                linux,code = <KEY_CAMERA>;
+        };
+
+        key_6 {
+                keypad,row = <2>;
+                keypad,column = <2>;
+                linux,code = <KEY_VOLUMEDOWN>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&sdhci0 {
+        bus-width = <4>;
+        non-removable;
+        vmmc-supply = <&ldo5_reg>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gph3 4 1>;
+        vmmc-supply = <&vtf_reg>;
+        cd-inverted;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&hsotg {
+        vusb_a-supply = <&ldo3_reg>;
+        vusb_d-supply = <&ldo8_reg>;
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&i2c2 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <400000>;
+        samsung,i2c-slave-addr = <0x10>;
+        status = "okay";
+
+        tsp@4a {
+                compatible = "atmel,maxtouch";
+                reg = <0x4a>;
+                interrupt-parent = <&gpj0>;
+                interrupts = <5 2>;
+
+                atmel,x-line = <17>;
+                atmel,y-line = <11>;
+                atmel,x-size = <800>;
+                atmel,y-size = <480>;
+                atmel,burst-length = <0x21>;
+                atmel,threshold = <0x28>;
+                atmel,orientation = <1>;
+
+                vdd-supply = <&tsp_reg>;
+        };
+};
+
+&i2c0 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <100000>;
+        samsung,i2c-slave-addr = <0x10>;
+        status = "okay";
+
+        noon010pc30: sensor@30 {
+                compatible = "siliconfile,noon010pc30";
+                reg = <0x30>;
+                vddio-supply = <&ldo11_reg>;
+                vdda-supply = <&ldo13_reg>;
+                vdd_core-supply = <&ldo14_reg>;
+
+                clock-frequency = <16000000>;
+                clocks = <&clock_cam 0>;
+                clock-names = "mclk";
+                nreset-gpios = <&gpb 2 0>;
+                nstby-gpios = <&gpb 0 0>;
+
+                port {
+                        noon010pc30_ep: endpoint {
+                                remote-endpoint = <&fimc0_ep>;
+                                bus-width = <8>;
+                                hsync-active = <0>;
+                                vsync-active = <1>;
+                                pclk-sample = <1>;
+                        };
+                };
+        };
+};
+
+&camera {
+        pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>;
+        pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>;
+        pinctrl-names = "default", "idle";
+
+        parallel-ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* camera A input */
+                port@1 {
+                        reg = <1>;
+                        fimc0_ep: endpoint {
+                                remote-endpoint = <&noon010pc30_ep>;
+                                bus-width = <8>;
+                                hsync-active = <1>;
+                                vsync-active = <1>;
+                                pclk-sample = <0>;
+                        };
+                };
+        };
+};
+
+&fimd {
+        pinctrl-0 = <&lcd_clk &lcd_data24>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        /* 480x800@55Hz */
+                        clock-frequency = <23439570>;
+                        hactive = <480>;
+                        hfront-porch = <16>;
+                        hback-porch = <16>;
+                        hsync-len = <2>;
+                        vactive = <800>;
+                        vback-porch = <2>;
+                        vfront-porch = <28>;
+                        vsync-len = <1>;
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <0>;
+                        pixelclk-active = <0>;
+                };
+        };
+};
+
+&onenand {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
new file mode 100644
index 000000000000..8c714088e3c6
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -0,0 +1,839 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&pinctrl0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe0: gpe0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe1: gpe1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf2: gpf2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf3: gpf3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg0: gpg0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg1: gpg1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg2: gpg2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg3: gpg3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj0: gpj0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj1: gpj1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj2: gpj2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj3: gpj3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj4: gpj4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpgi: gpgi {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp01: mp01 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp02: mp02 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp03: mp03 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp04: mp04 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp05: mp05 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp06: mp06 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        mp07: mp07 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gph0: gph0 {
+                gpio-controller;
+                interrupt-controller;
+                interrupt-parent = <&vic0>;
+                interrupts = <0>, <1>, <2>, <3>,
+                                <4>, <5>, <6>, <7>;
+                #gpio-cells = <2>;
+                #interrupt-cells = <2>;
+        };
+
+        gph1: gph1 {
+                gpio-controller;
+                interrupt-controller;
+                interrupt-parent = <&vic0>;
+                interrupts = <8>, <9>, <10>, <11>,
+                                <12>, <13>, <14>, <15>;
+                #gpio-cells = <2>;
+                #interrupt-cells = <2>;
+        };
+
+        gph2: gph2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                #interrupt-cells = <2>;
+        };
+
+        gph3: gph3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                #interrupt-cells = <2>;
+        };
+
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart_audio: uart-audio {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s0_bus: i2s0-bus {
+                samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
+                                "gpi-4", "gpi-5", "gpi-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pcm1_bus: pcm1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        ac97_bus: ac97-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        spdif_bus: spdif-bus {
+                samsung,pins = "gpc1-0", "gpc1-1";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+                samsung,pin-function = <5>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpd1-4", "gpd1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row0: keypad-row-0 {
+                samsung,pins = "gph3-0";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row1: keypad-row-1 {
+                samsung,pins = "gph3-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row2: keypad-row-2 {
+                samsung,pins = "gph3-2";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row3: keypad-row-3 {
+                samsung,pins = "gph3-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row4: keypad-row-4 {
+                samsung,pins = "gph3-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row5: keypad-row-5 {
+                samsung,pins = "gph3-5";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row6: keypad-row-6 {
+                samsung,pins = "gph3-6";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_row7: keypad-row-7 {
+                samsung,pins = "gph3-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col0: keypad-col-0 {
+                samsung,pins = "gph2-0";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col1: keypad-col-1 {
+                samsung,pins = "gph2-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col2: keypad-col-2 {
+                samsung,pins = "gph2-2";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col3: keypad-col-3 {
+                samsung,pins = "gph2-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col4: keypad-col-4 {
+                samsung,pins = "gph2-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col5: keypad-col-5 {
+                samsung,pins = "gph2-5";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col6: keypad-col-6 {
+                samsung,pins = "gph2-6";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        keypad_col7: keypad-col-7 {
+                samsung,pins = "gph2-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpg0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpg0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpg0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpg0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpg1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpg1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpg1-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpg1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpg2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpg2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpg2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpg2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus8: sd2-bus-width8 {
+                samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd3_clk: sd3-clk {
+                samsung,pins = "gpg3-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd3_cmd: sd3-cmd {
+                samsung,pins = "gpg3-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd3_cd: sd3-cd {
+                samsung,pins = "gpg3-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd3_bus1: sd3-bus-width1 {
+                samsung,pins = "gpg3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd3_bus4: sd3-bus-width4 {
+                samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <2>;
+                samsung,pin-drv = <3>;
+        };
+
+        eint0: ext-int0 {
+                samsung,pins = "gph0-0";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        eint8: ext-int8 {
+                samsung,pins = "gph1-0";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        eint15: ext-int15 {
+                samsung,pins = "gph1-7";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        eint16: ext-int16 {
+                samsung,pins = "gph2-0";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        eint31: ext-int31 {
+                samsung,pins = "gph3-7";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        cam_port_a_io: cam-port-a-io {
+                samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+                                "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+                                "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        cam_port_a_clk_active: cam-port-a-clk-active {
+                samsung,pins = "gpe1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        cam_port_a_clk_idle: cam-port-a-clk-idle {
+                samsung,pins = "gpe1-3";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+
+        cam_port_b_io: cam-port-b-io {
+                samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+                                "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+                                "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        cam_port_b_clk_active: cam-port-b-clk-active {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        cam_port_b_clk_idle: cam-port-b-clk-idle {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+
+                lcd_ctrl: lcd-ctrl {
+                samsung,pins = "gpd0-0", "gpd0-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        lcd_sync: lcd-sync {
+                samsung,pins = "gpf0-0", "gpf0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        lcd_clk: lcd-clk {
+                samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        lcd_data24: lcd-data-width24 {
+                samsung,pins =  "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts
new file mode 100644
index 000000000000..1eedab7ffe94
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts
@@ -0,0 +1,78 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Board device tree source for YIC System SMDC110 board.
+ *
+ * NOTE: This file is completely based on original board file for mach-smdkc110
+ * available in Linux 3.15 and intends to provide equivalent level of hardware
+ * support. Due to lack of hardware, _no_ testing has been performed.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "s5pv210.dtsi"
+
+/ {
+        model = "YIC System SMDKC110 based on S5PC110";
+        compatible = "yic,smdkc110", "samsung,s5pv210";
+
+        chosen {
+                bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x20000000 0x20000000>;
+        };
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+
+        audio-codec@1b {
+                compatible = "wlf,wm8580";
+                reg = <0x1b>;
+        };
+
+        eeprom@50 {
+                compatible = "atmel,24c08";
+                reg = <0x50>;
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts
new file mode 100644
index 000000000000..cb8521899ec8
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts
@@ -0,0 +1,238 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Board device tree source for YIC System SMDV210 board.
+ *
+ * NOTE: This file is completely based on original board file for mach-smdkv210
+ * available in Linux 3.15 and intends to provide equivalent level of hardware
+ * support. Due to lack of hardware, _no_ testing has been performed.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "s5pv210.dtsi"
+
+/ {
+        model = "YIC System SMDKV210 based on S5PV210";
+        compatible = "yic,smdkv210", "samsung,s5pv210";
+
+        chosen {
+                bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x20000000 0x40000000>;
+        };
+
+        ethernet@18000000 {
+                compatible = "davicom,dm9000";
+                reg = <0xA8000000 0x2 0xA8000002 0x2>;
+                interrupt-parent = <&gph1>;
+                interrupts = <1 4>;
+                local-mac-address = [00 00 de ad be ef];
+                davicom,no-eeprom;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000 0>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm3_out>;
+        };
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&keypad {
+        linux,input-no-autorepeat;
+        linux,input-wakeup;
+        samsung,keypad-num-rows = <8>;
+        samsung,keypad-num-columns = <8>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
+                        <&keypad_row3>, <&keypad_row4>, <&keypad_row5>,
+                        <&keypad_row6>, <&keypad_row7>,
+                        <&keypad_col0>, <&keypad_col1>, <&keypad_col2>,
+                        <&keypad_col3>, <&keypad_col4>, <&keypad_col5>,
+                        <&keypad_col6>, <&keypad_col7>;
+        status = "okay";
+
+        key_1 {
+                keypad,row = <0>;
+                keypad,column = <3>;
+                linux,code = <KEY_1>;
+        };
+
+        key_2 {
+                keypad,row = <0>;
+                keypad,column = <4>;
+                linux,code = <KEY_2>;
+        };
+
+        key_3 {
+                keypad,row = <0>;
+                keypad,column = <5>;
+                linux,code = <KEY_3>;
+        };
+
+        key_4 {
+                keypad,row = <0>;
+                keypad,column = <6>;
+                linux,code = <KEY_4>;
+        };
+
+        key_5 {
+                keypad,row = <0
+                >;
+                keypad,column = <7>;
+                linux,code = <KEY_5>;
+        };
+
+        key_6 {
+                keypad,row = <1>;
+                keypad,column = <3>;
+                linux,code = <KEY_A>;
+        };
+        key_7 {
+                keypad,row = <1>;
+                keypad,column = <4>;
+                linux,code = <KEY_B>;
+        };
+
+        key_8 {
+                keypad,row = <1>;
+                keypad,column = <5>;
+                linux,code = <KEY_C>;
+        };
+
+        key_9 {
+                keypad,row = <1>;
+                keypad,column = <6>;
+                linux,code = <KEY_D>;
+        };
+
+        key_10 {
+                keypad,row = <1>;
+                keypad,column = <7>;
+                linux,code = <KEY_E>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sdhci0 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci1 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci3 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&hsotg {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&fimd {
+        pinctrl-0 = <&lcd_clk &lcd_data24>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        display-timings {
+                native-mode = <&timing0>;
+
+                timing0: timing@0 {
+                        /* 800x480@60Hz */
+                        clock-frequency = <24373920>;
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <8>;
+                        hback-porch = <13>;
+                        hsync-len = <3>;
+                        vback-porch = <7>;
+                        vfront-porch = <5>;
+                        vsync-len = <1>;
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <1>;
+                        pixelclk-active = <1>;
+                };
+        };
+};
+
+&pwm {
+        samsung,pwm-outputs = <3>;
+};
+
+&i2c0 {
+        status = "okay";
+
+        audio-codec@1b {
+                compatible = "wlf,wm8580";
+                reg = <0x1b>;
+        };
+
+        eeprom@50 {
+                compatible = "atmel,24c08";
+                reg = <0x50>;
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts
new file mode 100644
index 000000000000..622599fd2cfa
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-torbreck.dts
@@ -0,0 +1,92 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Board device tree source for Torbreck board.
+ *
+ * NOTE: This file is completely based on original board file for mach-torbreck
+ * available in Linux 3.15 and intends to provide equivalent level of hardware
+ * support. Due to lack of hardware, _no_ testing has been performed.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "s5pv210.dtsi"
+
+/ {
+        model = "aESOP Torbreck based on S5PV210";
+        compatible = "aesop,torbreck", "samsung,s5pv210";
+
+        chosen {
+                bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x20000000 0x20000000>;
+        };
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sdhci0 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci1 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&sdhci3 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
new file mode 100644
index 000000000000..8344a0ee2b86
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -0,0 +1,633 @@
+/*
+ * Samsung's S5PV210 SoC device tree source
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
+ *
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/s5pv210.h>
+#include <dt-bindings/clock/s5pv210-audss.h>
+
+/ {
+        aliases {
+                csis0 = &csis0;
+                fimc0 = &fimc0;
+                fimc1 = &fimc1;
+                fimc2 = &fimc2;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2s0 = &i2s0;
+                i2s1 = &i2s1;
+                i2s2 = &i2s2;
+                pinctrl0 = &pinctrl0;
+                spi0 = &spi0;
+                spi1 = &spi1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a8";
+                        reg = <0>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                external-clocks {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        xxti: oscillator@0 {
+                                compatible = "fixed-clock";
+                                reg = <0>;
+                                clock-frequency = <0>;
+                                clock-output-names = "xxti";
+                                #clock-cells = <0>;
+                        };
+
+                        xusbxti: oscillator@1 {
+                                compatible = "fixed-clock";
+                                reg = <1>;
+                                clock-frequency = <0>;
+                                clock-output-names = "xusbxti";
+                                #clock-cells = <0>;
+                        };
+                };
+
+                onenand: onenand@b0000000 {
+                        compatible = "samsung,s5pv210-onenand";
+                        reg = <0xb0600000 0x2000>,
+                                <0xb0000000 0x20000>,
+                                <0xb0040000 0x20000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <31>;
+                        clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
+                        clock-names = "bus", "onenand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                };
+
+                chipid@e0000000 {
+                        compatible = "samsung,s5pv210-chipid";
+                        reg = <0xe0000000 0x1000>;
+                };
+
+                clocks: clock-controller@e0100000 {
+                        compatible = "samsung,s5pv210-clock", "simple-bus";
+                        reg = <0xe0100000 0x10000>;
+                        clock-names = "xxti", "xusbxti";
+                        clocks = <&xxti>, <&xusbxti>;
+                        #clock-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pmu_syscon: syscon@e0108000 {
+                                compatible = "samsung-s5pv210-pmu", "syscon";
+                                reg = <0xe0108000 0x8000>;
+                        };
+                };
+
+                pinctrl0: pinctrl@e0200000 {
+                        compatible = "samsung,s5pv210-pinctrl";
+                        reg = <0xe0200000 0x1000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <30>;
+
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupts = <16>;
+                                interrupt-parent = <&vic0>;
+                        };
+                };
+
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "arm,amba-bus";
+                        ranges;
+
+                        pdma0: dma@e0900000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xe0900000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <19>;
+                                clocks = <&clocks CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        pdma1: dma@e0a00000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xe0a00000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <20>;
+                                clocks = <&clocks CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+
+                spi0: spi@e1300000 {
+                        compatible = "samsung,s5pv210-spi";
+                        reg = <0xe1300000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <15>;
+                        dmas = <&pdma0 7>, <&pdma0 6>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                spi1: spi@e1400000 {
+                        compatible = "samsung,s5pv210-spi";
+                        reg = <0xe1400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <16>;
+                        dmas = <&pdma1 7>, <&pdma1 6>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                keypad: keypad@e1600000 {
+                        compatible = "samsung,s5pv210-keypad";
+                        reg = <0xe1600000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <25>;
+                        clocks = <&clocks CLK_KEYIF>;
+                        clock-names = "keypad";
+                        status = "disabled";
+                };
+
+                i2c0: i2c@e1800000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0xe1800000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <14>;
+                        clocks = <&clocks CLK_I2C0>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_bus>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e1a00000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0xe1a00000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <19>;
+                        clocks = <&clocks CLK_I2C2>;
+                        clock-names = "i2c";
+                        pinctrl-0 = <&i2c2_bus>;
+                        pinctrl-names = "default";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                audio-subsystem {
+                        compatible = "samsung,s5pv210-audss", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clk_audss: clock-controller@eee10000 {
+                                compatible = "samsung,s5pv210-audss-clock";
+                                reg = <0xeee10000 0x1000>;
+                                clock-names = "hclk", "xxti",
+                                                "fout_epll",
+                                                "sclk_audio0";
+                                clocks = <&clocks DOUT_HCLKP>, <&xxti>,
+                                                <&clocks FOUT_EPLL>,
+                                                <&clocks SCLK_AUDIO0>;
+                                #clock-cells = <1>;
+                        };
+
+                        i2s0: i2s@eee30000 {
+                                compatible = "samsung,s5pv210-i2s";
+                                reg = <0xeee30000 0x1000>;
+                                interrupt-parent = <&vic2>;
+                                interrupts = <16>;
+                                dma-names = "rx", "tx", "tx-sec";
+                                dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>;
+                                clock-names = "iis",
+                                                "i2s_opclk0",
+                                                "i2s_opclk1";
+                                clocks = <&clk_audss CLK_I2S>,
+                                                <&clk_audss CLK_I2S>,
+                                                <&clk_audss CLK_DOUT_AUD_BUS>;
+                                samsung,idma-addr = <0xc0010000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2s0_bus>;
+                                #sound-dai-cells = <0>;
+                                status = "disabled";
+                        };
+                };
+
+                i2s1: i2s@e2100000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        reg = <0xe2100000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <17>;
+                        dma-names = "rx", "tx";
+                        dmas = <&pdma1 12>, <&pdma1 13>;
+                        clock-names = "iis", "i2s_opclk0";
+                        clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s1_bus>;
+                        #sound-dai-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2s2: i2s@e2a00000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        reg = <0xe2a00000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <18>;
+                        dma-names = "rx", "tx";
+                        dmas = <&pdma1 14>, <&pdma1 15>;
+                        clock-names = "iis", "i2s_opclk0";
+                        clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s2_bus>;
+                        #sound-dai-cells = <0>;
+                        status = "disabled";
+                };
+
+                pwm: pwm@e2500000 {
+                        compatible = "samsung,s5pc100-pwm";
+                        reg = <0xe2500000 0x1000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <21>, <22>, <23>, <24>, <25>;
+                        clock-names = "timers";
+                        clocks = <&clocks CLK_PWM>;
+                        #pwm-cells = <3>;
+                };
+
+                watchdog: watchdog@e2700000 {
+                        compatible = "samsung,s3c2410-wdt";
+                        reg = <0xe2700000 0x1000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <26>;
+                        clock-names = "watchdog";
+                        clocks = <&clocks CLK_WDT>;
+                };
+
+                rtc: rtc@e2800000 {
+                        compatible = "samsung,s3c6410-rtc";
+                        reg = <0xe2800000 0x100>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <28>, <29>;
+                        clocks = <&clocks CLK_RTC>;
+                        clock-names = "rtc";
+                        status = "disabled";
+                };
+
+                uart0: serial@e2900000 {
+                        compatible = "samsung,s5pv210-uart";
+                        reg = <0xe2900000 0x400>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        clock-names = "uart", "clk_uart_baud0",
+                                        "clk_uart_baud1";
+                        clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
+                                        <&clocks SCLK_UART0>;
+                        status = "disabled";
+                };
+
+                uart1: serial@e2900400 {
+                        compatible = "samsung,s5pv210-uart";
+                        reg = <0xe2900400 0x400>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <11>;
+                        clock-names = "uart", "clk_uart_baud0",
+                                        "clk_uart_baud1";
+                        clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
+                                        <&clocks SCLK_UART1>;
+                        status = "disabled";
+                };
+
+                uart2: serial@e2900800 {
+                        compatible = "samsung,s5pv210-uart";
+                        reg = <0xe2900800 0x400>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <12>;
+                        clock-names = "uart", "clk_uart_baud0",
+                                        "clk_uart_baud1";
+                        clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
+                                        <&clocks SCLK_UART2>;
+                        status = "disabled";
+                };
+
+                uart3: serial@e2900c00 {
+                        compatible = "samsung,s5pv210-uart";
+                        reg = <0xe2900c00 0x400>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <13>;
+                        clock-names = "uart", "clk_uart_baud0",
+                                        "clk_uart_baud1";
+                        clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
+                                        <&clocks SCLK_UART3>;
+                        status = "disabled";
+                };
+
+                sdhci0: sdhci@eb000000 {
+                        compatible = "samsung,s3c6410-sdhci";
+                        reg = <0xeb000000 0x100000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <26>;
+                        clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
+                        clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
+                                        <&clocks SCLK_MMC0>;
+                        status = "disabled";
+                };
+
+                sdhci1: sdhci@eb100000 {
+                        compatible = "samsung,s3c6410-sdhci";
+                        reg = <0xeb100000 0x100000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <27>;
+                        clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
+                        clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
+                                        <&clocks SCLK_MMC1>;
+                        status = "disabled";
+                };
+
+                sdhci2: sdhci@eb200000 {
+                        compatible = "samsung,s3c6410-sdhci";
+                        reg = <0xeb200000 0x100000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <28>;
+                        clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
+                        clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
+                                        <&clocks SCLK_MMC2>;
+                        status = "disabled";
+                };
+
+                sdhci3: sdhci@eb300000 {
+                        compatible = "samsung,s3c6410-sdhci";
+                        reg = <0xeb300000 0x100000>;
+                        interrupt-parent = <&vic3>;
+                        interrupts = <2>;
+                        clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3";
+                        clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
+                                        <&clocks SCLK_MMC3>;
+                        status = "disabled";
+                };
+
+                hsotg: hsotg@ec000000 {
+                        compatible = "samsung,s3c6400-hsotg";
+                        reg = <0xec000000 0x20000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <24>;
+                        clocks = <&clocks CLK_USB_OTG>;
+                        clock-names = "otg";
+                        phy-names = "usb2-phy";
+                        phys = <&usbphy 0>;
+                        status = "disabled";
+                };
+
+                usbphy: usbphy@ec100000 {
+                        compatible = "samsung,s5pv210-usb2-phy";
+                        reg = <0xec100000 0x100>;
+                        samsung,pmureg-phandle = <&pmu_syscon>;
+                        clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
+                        clock-names = "phy", "ref";
+                        #phy-cells = <1>;
+                        status = "disabled";
+                };
+
+                ehci: ehci@ec200000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0xec200000 0x100>;
+                        interrupts = <23>;
+                        interrupt-parent = <&vic1>;
+                        clocks = <&clocks CLK_USB_HOST>;
+                        clock-names = "usbhost";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usbphy 1>;
+                        };
+                };
+
+                ohci: ohci@ec300000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0xec300000 0x100>;
+                        interrupts = <23>;
+                        clocks = <&clocks CLK_USB_HOST>;
+                        clock-names = "usbhost";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usbphy 1>;
+                        };
+                };
+
+                mfc: codec@f1700000 {
+                        compatible = "samsung,mfc-v5";
+                        reg = <0xf1700000 0x10000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <14>;
+                        clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
+                        clock-names = "sclk_mfc", "mfc";
+                };
+
+                vic0: interrupt-controller@f2000000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0xf2000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                vic1: interrupt-controller@f2100000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0xf2100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                vic2: interrupt-controller@f2200000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0xf2200000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                vic3: interrupt-controller@f2300000 {
+                        compatible = "arm,pl192-vic";
+                        interrupt-controller;
+                        reg = <0xf2300000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                fimd: fimd@f8000000 {
+                        compatible = "samsung,exynos4210-fimd";
+                        interrupt-parent = <&vic2>;
+                        reg = <0xf8000000 0x20000>;
+                        interrupt-names = "fifo", "vsync", "lcd_sys";
+                        interrupts = <0>, <1>, <2>;
+                        clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
+                        clock-names = "sclk_fimd", "fimd";
+                        status = "disabled";
+                };
+
+                g2d: g2d@fa000000 {
+                        compatible = "samsung,s5pv210-g2d";
+                        reg = <0xfa000000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <9>;
+                        clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
+                        clock-names = "sclk_fimg2d", "fimg2d";
+                };
+
+                mdma1: mdma@fa200000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xfa200000 0x1000>;
+                        interrupt-parent = <&vic0>;
+                        interrupts = <18>;
+                        clocks = <&clocks CLK_MDMA>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
+                };
+
+                i2c1: i2c@fab00000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0xfab00000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <13>;
+                        clocks = <&clocks CLK_I2C1>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_bus>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                camera: camera {
+                        compatible = "samsung,fimc", "simple-bus";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <>;
+                        clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
+                        clock-names = "sclk_cam0", "sclk_cam1";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clock_cam: clock-controller {
+                                #clock-cells = <1>;
+                        };
+
+                        csis0: csis@fa600000 {
+                                compatible = "samsung,s5pv210-csis";
+                                reg = <0xfa600000 0x4000>;
+                                interrupt-parent = <&vic2>;
+                                interrupts = <29>;
+                                clocks = <&clocks CLK_CSIS>,
+                                                <&clocks SCLK_CSIS>;
+                                clock-names = "clk_csis",
+                                                "sclk_csis";
+                                bus-width = <4>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        fimc0: fimc@fb200000 {
+                                compatible = "samsung,s5pv210-fimc";
+                                reg = <0xfb200000 0x1000>;
+                                interrupts = <5>;
+                                interrupt-parent = <&vic2>;
+                                clocks = <&clocks CLK_FIMC0>,
+                                                <&clocks SCLK_FIMC0>;
+                                clock-names = "fimc",
+                                                "sclk_fimc";
+                                samsung,pix-limits = <4224 8192 1920 4224>;
+                                samsung,mainscaler-ext;
+                                samsung,cam-if;
+                        };
+
+                        fimc1: fimc@fb300000 {
+                                compatible = "samsung,s5pv210-fimc";
+                                reg = <0xfb300000 0x1000>;
+                                interrupt-parent = <&vic2>;
+                                interrupts = <6>;
+                                clocks = <&clocks CLK_FIMC1>,
+                                                <&clocks SCLK_FIMC1>;
+                                clock-names = "fimc",
+                                                "sclk_fimc";
+                                samsung,pix-limits = <4224 8192 1920 4224>;
+                                samsung,mainscaler-ext;
+                                samsung,cam-if;
+                        };
+
+                        fimc2: fimc@fb400000 {
+                                compatible = "samsung,s5pv210-fimc";
+                                reg = <0xfb400000 0x1000>;
+                                interrupt-parent = <&vic2>;
+                                interrupts = <7>;
+                                clocks = <&clocks CLK_FIMC2>,
+                                                <&clocks SCLK_FIMC2>;
+                                clock-names = "fimc",
+                                                "sclk_fimc";
+                                samsung,pix-limits = <4224 8192 1920 4224>;
+                                samsung,mainscaler-ext;
+                                samsung,lcd-wb;
+                        };
+                };
+        };
+};
+
+#include "s5pv210-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e01e5a081def..36c771a2d765 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -19,6 +19,41 @@
                 reg = <0x0 0x08000000>;
         };
 
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        core-module@10000000 {
+                compatible = "arm,core-module-versatile", "syscon";
+                reg = <0x10000000 0x200>;
+
+                /* OSC1 on AB, OSC4 on PB */
+                osc1: cm_aux_osc@24M {
+                        #clock-cells = <0>;
+                        compatible = "arm,versatile-cm-auxosc";
+                        clocks = <&xtal24mhz>;
+                };
+
+                /* The timer clock is the 24 MHz oscillator divided to 1MHz */
+                timclk: timclk@1M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+
+                pclk: pclk@24M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+        };
+
         flash@34000000 {
                 compatible = "arm,versatile-flash";
                 reg = <0x34000000 0x4000000>;
@@ -59,6 +94,8 @@
                         interrupt-controller;
                         #interrupt-cells = <1>;
                         reg = <0x10140000 0x1000>;
+                        clear-mask = <0xffffffff>;
+                        valid-mask = <0xffffffff>;
                 };
 
                 sic: intc@10003000 {
@@ -68,69 +105,93 @@
                         reg = <0x10003000 0x1000>;
                         interrupt-parent = <&vic>;
                         interrupts = <31>; /* Cascaded to vic */
+                        clear-mask = <0xffffffff>;
+                        valid-mask = <0xffc203f8>;
                 };
 
                 dma@10130000 {
                         compatible = "arm,pl081", "arm,primecell";
                         reg = <0x10130000 0x1000>;
                         interrupts = <17>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 uart0: uart@101f1000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f1000 0x1000>;
                         interrupts = <12>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 uart1: uart@101f2000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f2000 0x1000>;
                         interrupts = <13>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 uart2: uart@101f3000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f3000 0x1000>;
                         interrupts = <14>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 smc@10100000 {
                         compatible = "arm,primecell";
                         reg = <0x10100000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 mpmc@10110000 {
                         compatible = "arm,primecell";
                         reg = <0x10110000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 display@10120000 {
                         compatible = "arm,pl110", "arm,primecell";
                         reg = <0x10120000 0x1000>;
                         interrupts = <16>;
+                        clocks = <&osc1>, <&pclk>;
+                        clock-names = "clcd", "apb_pclk";
                 };
 
                 sctl@101e0000 {
                         compatible = "arm,primecell";
                         reg = <0x101e0000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 watchdog@101e1000 {
                         compatible = "arm,primecell";
                         reg = <0x101e1000 0x1000>;
                         interrupts = <0>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 timer@101e2000 {
                         compatible = "arm,sp804", "arm,primecell";
                         reg = <0x101e2000 0x1000>;
                         interrupts = <4>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer0", "timer1", "apb_pclk";
                 };
 
                 timer@101e3000 {
                         compatible = "arm,sp804", "arm,primecell";
                         reg = <0x101e3000 0x1000>;
                         interrupts = <5>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer0", "timer1", "apb_pclk";
                 };
 
                 gpio0: gpio@101e4000 {
@@ -141,6 +202,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpio1: gpio@101e5000 {
@@ -151,24 +214,32 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 rtc@101e8000 {
                         compatible = "arm,pl030", "arm,primecell";
                         reg = <0x101e8000 0x1000>;
                         interrupts = <10>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 sci@101f0000 {
                         compatible = "arm,primecell";
                         reg = <0x101f0000 0x1000>;
                         interrupts = <15>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 ssp@101f4000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x101f4000 0x1000>;
                         interrupts = <11>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "SSPCLK", "apb_pclk";
                 };
 
                 fpga {
@@ -181,23 +252,31 @@
                                 compatible = "arm,primecell";
                                 reg = <0x4000 0x1000>;
                                 interrupts = <24>;
+                                clocks = <&pclk>;
+                                clock-names = "apb_pclk";
                         };
                         mmc@5000 {
-                                compatible = "arm,primecell";
+                                compatible = "arm,pl180", "arm,primecell";
                                 reg = < 0x5000 0x1000>;
                                 interrupts-extended = <&vic 22 &sic 2>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
                         kmi@6000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x6000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <3>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
                         kmi@7000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x7000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <4>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 65f657711323..d025048119d3 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -13,6 +13,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpio3: gpio@101e7000 {
@@ -23,6 +25,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 fpga {
@@ -31,17 +35,23 @@
                                 reg = <0x9000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <6>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
                         sci@a000 {
                                 compatible = "arm,primecell";
                                 reg = <0xa000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <5>;
+                                clocks = <&xtal24mhz>;
+                                clock-names = "apb_pclk";
                         };
                         mmc@b000 {
-                                compatible = "arm,primecell";
+                                compatible = "arm,pl180", "arm,primecell";
                                 reg = <0xb000 0x1000>;
                                 interrupts-extended = <&vic 23 &sic 2>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
                 };
         };
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index fd6bff0c5b96..19211324772f 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -233,13 +233,13 @@ static void __init sp804_of_init(struct device_node *np)
         if (IS_ERR(clk1))
                 clk1 = NULL;
 
-        /* Get the 2nd clock if the timer has 2 timer clocks */
+        /* Get the 2nd clock if the timer has 3 timer clocks */
         if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
                 clk2 = of_clk_get(np, 1);
                 if (IS_ERR(clk2)) {
                         pr_err("sp804: %s clock not found: %d\n", np->name,
                                 (int)PTR_ERR(clk2));
-                        goto err;
+                        clk2 = NULL;
                 }
         } else
                 clk2 = clk1;
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 4bf72264b175..fbebcbce1e8c 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -27,6 +27,7 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_COMPACTION is not set
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index bada59d93b67..63bde0efc041 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,6 +1,7 @@
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
 CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
-CONFIG_MACH_IMX27LITE=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_MXT_TD60=y
-CONFIG_MACH_IMX27IPCAM=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 59b7e45142d8..16cfec4385c8 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,5 +1,6 @@
 CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=18
@@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
-CONFIG_MACH_IMX51_DT=y
+CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX50=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SX=y
 CONFIG_SOC_VF610=y
 CONFIG_PCI=y
 CONFIG_PCI_IMX6=y
@@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 CONFIG_NETFILTER=y
+CONFIG_CAN=y
+CONFIG_CAN_FLEXCAN=y
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_RFKILL=y
@@ -160,6 +164,7 @@ CONFIG_SPI=y
 CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MC9S08DZ60=y
+CONFIG_GPIO_STMPE=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
@@ -242,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
+CONFIG_FSL_EDMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
 CONFIG_DRM_IMX_FB_HELPER=y
@@ -288,6 +294,7 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 534836497998..3332a4231684 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -19,6 +19,7 @@ CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARCH_BCM_5301X=y
+CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
 CONFIG_MACH_BERLIN_BG2CD=y
@@ -27,7 +28,7 @@ CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_IMX51_DT=y
+CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index a9f992335eb2..c7906c2fd645 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_TASKSTATS=y
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/include/debug/s5pv210.S
index 30b511a580aa..4f1a73e2c1a1 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/s5pv210.S
@@ -1,9 +1,6 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/debug-macro.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
+/*
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,8 +9,9 @@
 
 /* pull in the relevant register and map files. */
 
-#include <linux/serial_s3c.h>
-#include <mach/map.h>
+#define S3C_ADDR_BASE   0xF6000000
+#define S3C_VA_UART     S3C_ADDR_BASE + 0x01000000
+#define S5PV210_PA_UART 0xe2900000
 
         /* note, for the boot process to work we have to keep the UART
          * virtual address aligned to an 1MiB boundary for the L1
@@ -22,8 +20,8 @@
          */
 
         .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C_PA_UART
-                ldr     \rv, = S3C_VA_UART
+                ldr     \rp, =S5PV210_PA_UART
+                ldr     \rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
                 add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
                 add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
@@ -33,9 +31,4 @@
 #define fifo_full fifo_full_s5pv210
 #define fifo_level fifo_level_s5pv210
 
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
 #include <debug/samsung.S>
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 5306de350133..312d43eb686a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -19,6 +19,7 @@
  * Author: Will Deacon <will.deacon@arm.com>
  */
 
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -36,6 +37,7 @@ struct arm_delay_ops arm_delay_ops = {
 
 static const struct delay_timer *delay_timer;
 static bool delay_calibrated;
+static u64 delay_res;
 
 int read_current_timer(unsigned long *timer_val)
 {
@@ -47,6 +49,11 @@ int read_current_timer(unsigned long *timer_val)
 }
 EXPORT_SYMBOL_GPL(read_current_timer);
 
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+        return (cyc * mult) >> shift;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
         cycles_t start = get_cycles();
@@ -69,18 +76,24 @@ static void __timer_udelay(unsigned long usecs)
 
 void __init register_current_timer_delay(const struct delay_timer *timer)
 {
-        if (!delay_calibrated) {
-                pr_info("Switching to timer-based delay loop\n");
+        u32 new_mult, new_shift;
+        u64 res;
+
+        clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq,
+                               NSEC_PER_SEC, 3600);
+        res = cyc_to_ns(1ULL, new_mult, new_shift);
+
+        if (!delay_calibrated && (!delay_res || (res < delay_res))) {
+                pr_info("Switching to timer-based delay loop, resolution %lluns\n", res);
                 delay_timer                     = timer;
                 lpj_fine                        = timer->freq / HZ;
+                delay_res                       = res;
 
                 /* cpufreq may scale loops_per_jiffy, so keep a private copy */
                 arm_delay_ops.ticks_per_jiffy   = lpj_fine;
                 arm_delay_ops.delay             = __timer_delay;
                 arm_delay_ops.const_udelay      = __timer_const_udelay;
                 arm_delay_ops.udelay            = __timer_udelay;
-
-                delay_calibrated                = true;
         } else {
                 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
         }
@@ -91,3 +104,8 @@ unsigned long calibrate_delay_is_known(void)
         delay_calibrated = true;
         return lpj_fine;
 }
+
+void calibration_delay_done(void)
+{
+        delay_calibrated = true;
+}
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 41c839167e87..fc938005ad39 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -9,7 +9,6 @@ config ARCH_BCM_MOBILE
         bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
         select ARM_ERRATA_754322
-        select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
         select ARM_GIC
         select GPIO_BCM_KONA
@@ -26,16 +25,18 @@ menu "Broadcom Mobile SoC Selection"
 config ARCH_BCM_281XX
         bool "Broadcom BCM281XX SoC family"
         default y
+        select HAVE_SMP
         help
-          Enable support for the the BCM281XX family, which includes
+          Enable support for the BCM281XX family, which includes
           BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
           variants.
 
 config ARCH_BCM_21664
         bool "Broadcom BCM21664 SoC family"
         default y
+        select HAVE_SMP
         help
-          Enable support for the the BCM21664 family, which includes
+          Enable support for the BCM21664 family, which includes
           BCM21663 and BCM21664 variants.
 
 config ARCH_BCM_MOBILE_L2_CACHE
@@ -49,6 +50,17 @@ config ARCH_BCM_MOBILE_SMC
         bool
         depends on ARCH_BCM_281XX || ARCH_BCM_21664
 
+config ARCH_BCM_MOBILE_SMP
+        bool "Broadcom mobile SoC SMP support"
+        depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
+        default y
+        select HAVE_ARM_SCU
+        select ARM_ERRATA_764369
+        help
+          SMP support for the BCM281XX and BCM21664 SoC families.
+          Provided as an option so SMP support for SoCs of this type
+          can be disabled for an SMP-enabled kernel.
+
 endmenu
 
 endif
@@ -87,4 +99,20 @@ config ARCH_BCM_5301X
           different SoC or with the older BCM47XX and BCM53XX based
           network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+config ARCH_BRCMSTB
+        bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+        depends on MMU
+        select ARM_GIC
+        select MIGHT_HAVE_PCI
+        select HAVE_SMP
+        select HAVE_ARM_ARCH_TIMER
+        select BRCMSTB_GISB_ARB
+        select BRCMSTB_L2_IRQ
+        help
+          Say Y if you intend to run the kernel on a Broadcom ARM-based STB
+          chipset.
+
+          This enables support for Broadcom ARM-based set-top box chipsets,
+          including the 7445 family of chips.
+
 endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 731292114975..67c492aabf4d 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -16,6 +16,9 @@ obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 # BCM21664
 obj-$(CONFIG_ARCH_BCM_21664)    += board_bcm21664.o
 
+# BCM281XX and BCM21664 SMP support
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+
 # BCM281XX and BCM21664 L2 cache control
 obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
 
@@ -30,3 +33,8 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
+
+ifeq ($(CONFIG_ARCH_BRCMSTB),y)
+obj-y                           += brcmstb.o
+obj-$(CONFIG_SMP)               += headsmp-brcmstb.o platsmp-brcmstb.o
+endif
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
new file mode 100644
index 000000000000..60a5afa06ed7
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static const char *brcmstb_match[] __initconst = {
+        "brcm,bcm7445",
+        "brcm,brcmstb",
+        NULL
+};
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+        .dt_compat      = brcmstb_match,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
new file mode 100644
index 000000000000..ec0c3d112b36
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_H__
+#define __BRCMSTB_H__
+
+void brcmstb_secondary_startup(void);
+
+#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
new file mode 100644
index 000000000000..199c1ea58248
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.S
@@ -0,0 +1,33 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+
+ENTRY(brcmstb_secondary_startup)
+        /*
+         * Ensure CPU is in a sane state by disabling all IRQs and switching
+         * into SVC mode.
+         */
+        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
+
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c
new file mode 100644
index 000000000000..66a0465528a5
--- /dev/null
+++ b/arch/arm/mach-bcm/kona_smp.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ * Copyright 2014 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/sched.h>
+
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+/* Size of mapped Cortex A9 SCU address space */
+#define CORTEX_A9_SCU_SIZE      0x58
+
+#define SECONDARY_TIMEOUT_NS    NSEC_PER_MSEC   /* 1 msec (in nanoseconds) */
+#define BOOT_ADDR_CPUID_MASK    0x3
+
+/* Name of device node property defining secondary boot register location */
+#define OF_SECONDARY_BOOT       "secondary-boot-reg"
+
+/* I/O address of register used to coordinate secondary core startup */
+static u32      secondary_boot;
+
+/*
+ * Enable the Cortex A9 Snoop Control Unit
+ *
+ * By the time this is called we already know there are multiple
+ * cores present.  We assume we're running on a Cortex A9 processor,
+ * so any trouble getting the base address register or getting the
+ * SCU base is a problem.
+ *
+ * Return 0 if successful or an error code otherwise.
+ */
+static int __init scu_a9_enable(void)
+{
+        unsigned long config_base;
+        void __iomem *scu_base;
+
+        if (!scu_a9_has_base()) {
+                pr_err("no configuration base address register!\n");
+                return -ENXIO;
+        }
+
+        /* Config base address register value is zero for uniprocessor */
+        config_base = scu_a9_get_base();
+        if (!config_base) {
+                pr_err("hardware reports only one core\n");
+                return -ENOENT;
+        }
+
+        scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
+        if (!scu_base) {
+                pr_err("failed to remap config base (%lu/%u) for SCU\n",
+                        config_base, CORTEX_A9_SCU_SIZE);
+                return -ENOMEM;
+        }
+
+        scu_enable(scu_base);
+
+        iounmap(scu_base);      /* That's the last we'll need of this */
+
+        return 0;
+}
+
+static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
+{
+        static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
+        struct device_node *node;
+        int ret;
+
+        BUG_ON(secondary_boot);         /* We're called only once */
+
+        /*
+         * This function is only called via smp_ops->smp_prepare_cpu().
+         * That only happens if a "/cpus" device tree node exists
+         * and has an "enable-method" property that selects the SMP
+         * operations defined herein.
+         */
+        node = of_find_node_by_path("/cpus");
+        BUG_ON(!node);
+
+        /*
+         * Our secondary enable method requires a "secondary-boot-reg"
+         * property to specify a register address used to request the
+         * ROM code boot a secondary code.  If we have any trouble
+         * getting this we fall back to uniprocessor mode.
+         */
+        if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
+                pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
+                        node->name);
+                ret = -ENOENT;          /* Arrange to disable SMP */
+                goto out;
+        }
+
+        /*
+         * Enable the SCU on Cortex A9 based SoCs.  If -ENOENT is
+         * returned, the SoC reported a uniprocessor configuration.
+         * We bail on any other error.
+         */
+        ret = scu_a9_enable();
+out:
+        of_node_put(node);
+        if (ret) {
+                /* Update the CPU present map to reflect uniprocessor mode */
+                BUG_ON(ret != -ENOENT);
+                pr_warn("disabling SMP\n");
+                init_cpu_present(&only_cpu_0);
+        }
+}
+
+/*
+ * The ROM code has the secondary cores looping, waiting for an event.
+ * When an event occurs each core examines the bottom two bits of the
+ * secondary boot register.  When a core finds those bits contain its
+ * own core id, it performs initialization, including computing its boot
+ * address by clearing the boot register value's bottom two bits.  The
+ * core signals that it is beginning its execution by writing its boot
+ * address back to the secondary boot register, and finally jumps to
+ * that address.
+ *
+ * So to start a core executing we need to:
+ * - Encode the (hardware) CPU id with the bottom bits of the secondary
+ *   start address.
+ * - Write that value into the secondary boot register.
+ * - Generate an event to wake up the secondary CPU(s).
+ * - Wait for the secondary boot register to be re-written, which
+ *   indicates the secondary core has started.
+ */
+static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        void __iomem *boot_reg;
+        phys_addr_t boot_func;
+        u64 start_clock;
+        u32 cpu_id;
+        u32 boot_val;
+        bool timeout = false;
+
+        cpu_id = cpu_logical_map(cpu);
+        if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
+                pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
+                return -EINVAL;
+        }
+
+        if (!secondary_boot) {
+                pr_err("required secondary boot register not specified\n");
+                return -EINVAL;
+        }
+
+        boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
+        if (!boot_reg) {
+                pr_err("unable to map boot register for cpu %u\n", cpu_id);
+                return -ENOSYS;
+        }
+
+        /*
+         * Secondary cores will start in secondary_startup(),
+         * defined in "arch/arm/kernel/head.S"
+         */
+        boot_func = virt_to_phys(secondary_startup);
+        BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
+        BUG_ON(boot_func > (phys_addr_t)U32_MAX);
+
+        /* The core to start is encoded in the low bits */
+        boot_val = (u32)boot_func | cpu_id;
+        writel_relaxed(boot_val, boot_reg);
+
+        sev();
+
+        /* The low bits will be cleared once the core has started */
+        start_clock = local_clock();
+        while (!timeout && readl_relaxed(boot_reg) == boot_val)
+                timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
+
+        iounmap(boot_reg);
+
+        if (!timeout)
+                return 0;
+
+        pr_err("timeout waiting for cpu %u to start\n", cpu_id);
+
+        return -ENOSYS;
+}
+
+static struct smp_operations bcm_smp_ops __initdata = {
+        .smp_prepare_cpus       = bcm_smp_prepare_cpus,
+        .smp_boot_secondary     = bcm_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
+                        &bcm_smp_ops);
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
new file mode 100644
index 000000000000..af780e9c23a6
--- /dev/null
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -0,0 +1,363 @@
+/*
+ * Broadcom STB CPU SMP and hotplug support for ARM
+ *
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+#include <linux/spinlock.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/mach-types.h>
+#include <asm/smp_plat.h>
+
+#include "brcmstb.h"
+
+enum {
+        ZONE_MAN_CLKEN_MASK             = BIT(0),
+        ZONE_MAN_RESET_CNTL_MASK        = BIT(1),
+        ZONE_MAN_MEM_PWR_MASK           = BIT(4),
+        ZONE_RESERVED_1_MASK            = BIT(5),
+        ZONE_MAN_ISO_CNTL_MASK          = BIT(6),
+        ZONE_MANUAL_CONTROL_MASK        = BIT(7),
+        ZONE_PWR_DN_REQ_MASK            = BIT(9),
+        ZONE_PWR_UP_REQ_MASK            = BIT(10),
+        ZONE_BLK_RST_ASSERT_MASK        = BIT(12),
+        ZONE_PWR_OFF_STATE_MASK         = BIT(25),
+        ZONE_PWR_ON_STATE_MASK          = BIT(26),
+        ZONE_DPG_PWR_STATE_MASK         = BIT(28),
+        ZONE_MEM_PWR_STATE_MASK         = BIT(29),
+        ZONE_RESET_STATE_MASK           = BIT(31),
+        CPU0_PWR_ZONE_CTRL_REG          = 1,
+        CPU_RESET_CONFIG_REG            = 2,
+};
+
+static void __iomem *cpubiuctrl_block;
+static void __iomem *hif_cont_block;
+static u32 cpu0_pwr_zone_ctrl_reg;
+static u32 cpu_rst_cfg_reg;
+static u32 hif_cont_reg;
+
+#ifdef CONFIG_HOTPLUG_CPU
+static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
+
+static int per_cpu_sw_state_rd(u32 cpu)
+{
+        sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+        return per_cpu(per_cpu_sw_state, cpu);
+}
+
+static void per_cpu_sw_state_wr(u32 cpu, int val)
+{
+        per_cpu(per_cpu_sw_state, cpu) = val;
+        dmb();
+        sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+        dsb_sev();
+}
+#else
+static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
+#endif
+
+static void __iomem *pwr_ctrl_get_base(u32 cpu)
+{
+        void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
+        base += (cpu_logical_map(cpu) * 4);
+        return base;
+}
+
+static u32 pwr_ctrl_rd(u32 cpu)
+{
+        void __iomem *base = pwr_ctrl_get_base(cpu);
+        return readl_relaxed(base);
+}
+
+static void pwr_ctrl_wr(u32 cpu, u32 val)
+{
+        void __iomem *base = pwr_ctrl_get_base(cpu);
+        writel(val, base);
+}
+
+static void cpu_rst_cfg_set(u32 cpu, int set)
+{
+        u32 val;
+        val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
+        if (set)
+                val |= BIT(cpu_logical_map(cpu));
+        else
+                val &= ~BIT(cpu_logical_map(cpu));
+        writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
+}
+
+static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
+{
+        const int reg_ofs = cpu_logical_map(cpu) * 8;
+        writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
+        writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
+}
+
+static void brcmstb_cpu_boot(u32 cpu)
+{
+        pr_info("SMP: Booting CPU%d...\n", cpu);
+
+        /*
+         * set the reset vector to point to the secondary_startup
+         * routine
+         */
+        cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+
+        /* unhalt the cpu */
+        cpu_rst_cfg_set(cpu, 0);
+}
+
+static void brcmstb_cpu_power_on(u32 cpu)
+{
+        /*
+         * The secondary cores power was cut, so we must go through
+         * power-on initialization.
+         */
+        u32 tmp;
+
+        pr_info("SMP: Powering up CPU%d...\n", cpu);
+
+        /* Request zone power up */
+        pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
+
+        /* Wait for the power up FSM to complete */
+        do {
+                tmp = pwr_ctrl_rd(cpu);
+        } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
+
+        per_cpu_sw_state_wr(cpu, 1);
+}
+
+static int brcmstb_cpu_get_power_state(u32 cpu)
+{
+        int tmp = pwr_ctrl_rd(cpu);
+        return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+static void brcmstb_cpu_die(u32 cpu)
+{
+        v7_exit_coherency_flush(all);
+
+        /* Prevent all interrupts from reaching this CPU. */
+        arch_local_irq_disable();
+
+        /*
+         * Final full barrier to ensure everything before this instruction has
+         * quiesced.
+         */
+        isb();
+        dsb();
+
+        per_cpu_sw_state_wr(cpu, 0);
+
+        /* Sit and wait to die */
+        wfi();
+
+        /* We should never get here... */
+        panic("Spurious interrupt on CPU %d received!\n", cpu);
+}
+
+static int brcmstb_cpu_kill(u32 cpu)
+{
+        u32 tmp;
+
+        pr_info("SMP: Powering down CPU%d...\n", cpu);
+
+        while (per_cpu_sw_state_rd(cpu))
+                ;
+
+        /* Program zone reset */
+        pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
+                              ZONE_PWR_DN_REQ_MASK);
+
+        /* Verify zone reset */
+        tmp = pwr_ctrl_rd(cpu);
+        if (!(tmp & ZONE_RESET_STATE_MASK))
+                pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
+                        __func__, cpu);
+
+        /* Wait for power down */
+        do {
+                tmp = pwr_ctrl_rd(cpu);
+        } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
+
+        /* Settle-time from Broadcom-internal DVT reference code */
+        udelay(7);
+
+        /* Assert reset on the CPU */
+        cpu_rst_cfg_set(cpu, 1);
+
+        return 1;
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
+{
+        int rc = 0;
+        char *name;
+        struct device_node *syscon_np = NULL;
+
+        name = "syscon-cpu";
+
+        syscon_np = of_parse_phandle(np, name, 0);
+        if (!syscon_np) {
+                pr_err("can't find phandle %s\n", name);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+        cpubiuctrl_block = of_iomap(syscon_np, 0);
+        if (!cpubiuctrl_block) {
+                pr_err("iomap failed for cpubiuctrl_block\n");
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+        rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
+                                        &cpu0_pwr_zone_ctrl_reg);
+        if (rc) {
+                pr_err("failed to read 1st entry from %s property (%d)\n", name,
+                        rc);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+        rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
+                                        &cpu_rst_cfg_reg);
+        if (rc) {
+                pr_err("failed to read 2nd entry from %s property (%d)\n", name,
+                        rc);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+cleanup:
+        if (syscon_np)
+                of_node_put(syscon_np);
+
+        return rc;
+}
+
+static int __init setup_hifcont_regs(struct device_node *np)
+{
+        int rc = 0;
+        char *name;
+        struct device_node *syscon_np = NULL;
+
+        name = "syscon-cont";
+
+        syscon_np = of_parse_phandle(np, name, 0);
+        if (!syscon_np) {
+                pr_err("can't find phandle %s\n", name);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+        hif_cont_block = of_iomap(syscon_np, 0);
+        if (!hif_cont_block) {
+                pr_err("iomap failed for hif_cont_block\n");
+                rc = -EINVAL;
+                goto cleanup;
+        }
+
+        /* offset is at top of hif_cont_block */
+        hif_cont_reg = 0;
+
+cleanup:
+        if (syscon_np)
+                of_node_put(syscon_np);
+
+        return rc;
+}
+
+static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+        int rc;
+        struct device_node *np;
+        char *name;
+
+        name = "brcm,brcmstb-smpboot";
+        np = of_find_compatible_node(NULL, NULL, name);
+        if (!np) {
+                pr_err("can't find compatible node %s\n", name);
+                return;
+        }
+
+        rc = setup_hifcpubiuctrl_regs(np);
+        if (rc)
+                return;
+
+        rc = setup_hifcont_regs(np);
+        if (rc)
+                return;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void brcmstb_secondary_init(unsigned int cpu)
+{
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /* Bring up power to the core if necessary */
+        if (brcmstb_cpu_get_power_state(cpu) == 0)
+                brcmstb_cpu_power_on(cpu);
+
+        brcmstb_cpu_boot(cpu);
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return 0;
+}
+
+static struct smp_operations brcmstb_smp_ops __initdata = {
+        .smp_prepare_cpus       = brcmstb_cpu_ctrl_setup,
+        .smp_secondary_init     = brcmstb_secondary_init,
+        .smp_boot_secondary     = brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = brcmstb_cpu_kill,
+        .cpu_die                = brcmstb_cpu_die,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 2631cfc5ab0d..24f85be71671 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -13,7 +13,9 @@ config MACH_BERLIN_BG2
         bool "Marvell Armada 1500 (BG2)"
         select CACHE_L2X0
         select CPU_PJ4B
+        select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
         select PINCTRL_BERLIN_BG2
 
 config MACH_BERLIN_BG2CD
@@ -25,6 +27,7 @@ config MACH_BERLIN_BG2CD
 config MACH_BERLIN_BG2Q
         bool "Marvell Armada 1500 Pro (BG2-Q)"
         select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select PINCTRL_BERLIN_BG2Q
 
diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile
index ab69fe956f49..c0719ecd1890 100644
--- a/arch/arm/mach-berlin/Makefile
+++ b/arch/arm/mach-berlin/Makefile
@@ -1 +1,2 @@
-obj-y += berlin.o
+obj-y                   += berlin.o
+obj-$(CONFIG_SMP)       += headsmp.o platsmp.o
diff --git a/arch/arm/mach-berlin/headsmp.S b/arch/arm/mach-berlin/headsmp.S
new file mode 100644
index 000000000000..4a4c56a58ad3
--- /dev/null
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Marvell Technology Group Ltd.
+ *
+ * Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+ENTRY(berlin_secondary_startup)
+ ARM_BE8(setend be)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(berlin_secondary_startup)
+
+/*
+ * If the following instruction is set in the reset exception vector, CPUs
+ * will fetch the value of the software reset address vector when being
+ * reset.
+ */
+.global boot_inst
+boot_inst:
+        ldr     pc, [pc, #140]
+
+        .align
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
new file mode 100644
index 000000000000..702e7982015a
--- /dev/null
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2014 Marvell Technology Group Ltd.
+ *
+ * Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define CPU_RESET               0x00
+
+#define RESET_VECT              0x00
+#define SW_RESET_ADDR           0x94
+
+extern void berlin_secondary_startup(void);
+extern u32 boot_inst;
+
+static void __iomem *cpu_ctrl;
+
+static inline void berlin_perform_reset_cpu(unsigned int cpu)
+{
+        u32 val;
+
+        val = readl(cpu_ctrl + CPU_RESET);
+        val |= BIT(cpu_logical_map(cpu));
+        writel(val, cpu_ctrl + CPU_RESET);
+}
+
+static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (!cpu_ctrl)
+                return -EFAULT;
+
+        /*
+         * Reset the CPU, making it to execute the instruction in the reset
+         * exception vector.
+         */
+        berlin_perform_reset_cpu(cpu);
+
+        return 0;
+}
+
+static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np;
+        void __iomem *scu_base;
+        void __iomem *vectors_base;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        scu_base = of_iomap(np, 0);
+        of_node_put(np);
+        if (!scu_base)
+                return;
+
+        np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
+        cpu_ctrl = of_iomap(np, 0);
+        of_node_put(np);
+        if (!cpu_ctrl)
+                goto unmap_scu;
+
+        vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
+        if (!vectors_base)
+                goto unmap_scu;
+
+        scu_enable(scu_base);
+        flush_cache_all();
+
+        /*
+         * Write the first instruction the CPU will execute after being reset
+         * in the reset exception vector.
+         */
+        writel(boot_inst, vectors_base + RESET_VECT);
+
+        /*
+         * Write the secondary startup address into the SW reset address
+         * vector. This is used by boot_inst.
+         */
+        writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
+
+        iounmap(vectors_base);
+unmap_scu:
+        iounmap(scu_base);
+}
+
+static struct smp_operations berlin_smp_ops __initdata = {
+        .smp_prepare_cpus       = berlin_smp_prepare_cpus,
+        .smp_boot_secondary     = berlin_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(berlin_smp, "marvell,berlin-smp", &berlin_smp_ops);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9cc5617..47b904b3b973 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
 
 /* PMU(Power Management Unit) support */
 
-#define PMU_TABLE_END   NULL
+#define PMU_TABLE_END   (-1U)
 
 enum sys_powerdown {
         SYS_AFTR,
@@ -144,7 +144,7 @@ enum sys_powerdown {
 };
 
 struct exynos_pmu_conf {
-        void __iomem *reg;
+        unsigned int offset;
         unsigned int val[NUM_SYS_POWERDOWN];
 };
 
@@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
 extern unsigned int samsung_rev(void);
 
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+        __raw_writel(val, pmu_base_addr + offset);
+}
+
+static inline u32 pmu_raw_readl(u32 offset)
+{
+        return __raw_readl(pmu_base_addr + offset);
+}
+
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 3164ef2e6b6c..c426093bdbd9 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_PMU,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
                 .length         = SZ_4K,
@@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
                 .length         = 144 * SZ_1K,
                 .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_PMU,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
         },
 };
 
@@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
 {
         struct device_node *np;
         u32 val = 0x1;
-        void __iomem *addr = EXYNOS_SWRESET;
+        void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
 
         if (of_machine_is_compatible("samsung,exynos5440")) {
                 u32 status;
@@ -175,17 +165,6 @@ static struct platform_device exynos_cpuidle = {
         .id                = -1,
 };
 
-void __init exynos_cpuidle_init(void)
-{
-        if (soc_is_exynos4210() || soc_is_exynos5250())
-                platform_device_register(&exynos_cpuidle);
-}
-
-void __init exynos_cpufreq_init(void)
-{
-        platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
-}
-
 void __iomem *sysram_base_addr;
 void __iomem *sysram_ns_base_addr;
 
@@ -335,8 +314,11 @@ static void __init exynos_dt_machine_init(void)
         if (!IS_ENABLED(CONFIG_SMP))
                 exynos_sysram_init();
 
-        exynos_cpuidle_init();
-        exynos_cpufreq_init();
+        if (of_machine_is_compatible("samsung,exynos4210") ||
+                        of_machine_is_compatible("samsung,exynos5250"))
+                platform_device_register(&exynos_cpuidle);
+
+        platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 963002fb15c3..f0b7e92bad6c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -27,9 +27,6 @@
 #define EXYNOS4_PA_SYSCON               0x10010000
 #define EXYNOS5_PA_SYSCON               0x10050100
 
-#define EXYNOS4_PA_PMU                  0x10020000
-#define EXYNOS5_PA_PMU                  0x10040000
-
 #define EXYNOS4_PA_CMU                  0x10030000
 #define EXYNOS5_PA_CMU                  0x10010000
 
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index a96b78f93f2b..b2f8b60cf0e9 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -26,6 +26,10 @@
 #define EXYNOS5420_CPUS_PER_CLUSTER     4
 #define EXYNOS5420_NR_CLUSTERS          2
 
+#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN   BIT(9)
+#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE      BIT(29)
+#define EXYNOS5420_USE_L2_COMMON_UP_STATE       BIT(30)
+
 /*
  * The common v7_exit_coherency_flush API could not be used because of the
  * Erratum 799270 workaround. This macro is the same as the common one (in
@@ -51,7 +55,7 @@
         "dsb\n\t" \
         "ldmfd  sp!, {fp, ip}" \
         : \
-        : "Ir" (S5P_INFORM0) \
+        : "Ir" (pmu_base_addr + S5P_INFORM0) \
         : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
           "r9", "r10", "lr", "memory")
 
@@ -73,36 +77,9 @@ cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
 
 #define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
 
-static int exynos_cluster_power_control(unsigned int cluster, int enable)
-{
-        unsigned int tries = 100;
-        unsigned int val;
-
-        if (enable) {
-                exynos_cluster_power_up(cluster);
-                val = S5P_CORE_LOCAL_PWR_EN;
-        } else {
-                exynos_cluster_power_down(cluster);
-                val = 0;
-        }
-
-        /* Wait until cluster power control is applied */
-        while (tries--) {
-                if (exynos_cluster_power_state(cluster) == val)
-                        return 0;
-
-                cpu_relax();
-        }
-        pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
-                enable ? "on" : "off");
-
-        return -ETIMEDOUT;
-}
-
 static int exynos_power_up(unsigned int cpu, unsigned int cluster)
 {
         unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
-        int err = 0;
 
         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
         if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
@@ -126,12 +103,9 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
                  * cores.
                  */
                 if (was_cluster_down)
-                        err = exynos_cluster_power_control(cluster, 1);
+                        exynos_cluster_power_up(cluster);
 
-                if (!err)
-                        exynos_cpu_power_up(cpunr);
-                else
-                        exynos_cluster_power_control(cluster, 0);
+                exynos_cpu_power_up(cpunr);
         } else if (cpu_use_count[cpu][cluster] != 2) {
                 /*
                  * The only possible values are:
@@ -147,7 +121,7 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
         arch_spin_unlock(&exynos_mcpm_lock);
         local_irq_enable();
 
-        return err;
+        return 0;
 }
 
 /*
@@ -178,9 +152,10 @@ static void exynos_power_down(void)
         if (cpu_use_count[cpu][cluster] == 0) {
                 exynos_cpu_power_down(cpunr);
 
-                if (exynos_cluster_unused(cluster))
-                        /* TODO: Turn off the cluster here to save power. */
+                if (exynos_cluster_unused(cluster)) {
+                        exynos_cluster_power_down(cluster);
                         last_man = true;
+                }
         } else if (cpu_use_count[cpu][cluster] == 1) {
                 /*
                  * A power_up request went ahead of us.
@@ -257,10 +232,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
         return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        arch_spin_lock(&exynos_mcpm_lock);
+        if (cpu_use_count[cpu][cluster] == 0)
+                cpu_use_count[cpu][cluster] = 1;
+        arch_spin_unlock(&exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+        unsigned int mpidr, cpunr;
+
+        exynos_power_down();
+
+        /*
+         * Execution reaches here only if cpu did not power down.
+         * Hence roll back the changes done in exynos_power_down function.
+         *
+         * CAUTION: "This function requires the stack data to be visible through
+         * power down and can only be executed on processors like A15 and A7
+         * that hit the cache with the C bit clear in the SCTLR register."
+        */
+        mpidr = read_cpuid_mpidr();
+        cpunr = exynos_pmu_cpunr(mpidr);
+
+        exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
         .power_up               = exynos_power_up,
         .power_down             = exynos_power_down,
         .wait_for_powerdown     = exynos_wait_for_powerdown,
+        .suspend                = exynos_suspend,
+        .powered_up             = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
@@ -312,6 +323,7 @@ static int __init exynos_mcpm_init(void)
 {
         struct device_node *node;
         void __iomem *ns_sram_base_addr;
+        unsigned int value, i;
         int ret;
 
         node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
@@ -338,7 +350,7 @@ static int __init exynos_mcpm_init(void)
          * To increase the stability of KFC reset we need to program
          * the PMU SPARE3 register
          */
-        __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+        pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
 
         exynos_mcpm_usage_count_init();
 
@@ -357,6 +369,26 @@ static int __init exynos_mcpm_init(void)
         pr_info("Exynos MCPM support installed\n");
 
         /*
+         * On Exynos5420/5800 for the A15 and A7 clusters:
+         *
+         * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
+         * in a cluster are turned off before turning off the cluster L2.
+         *
+         * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
+         * off before waking it up.
+         *
+         * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
+         * turned on before the first man is powered up.
+         */
+        for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
+                value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
+                value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
+                         EXYNOS5420_USE_ARM_CORE_DOWN_STATE    |
+                         EXYNOS5420_USE_L2_COMMON_UP_STATE;
+                pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
+        }
+
+        /*
          * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
          * as part of secondary_cpu_start().  Let's redirect it to the
          * mcpm_entry_point().
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index e5a8d764f24c..a9f1cf759949 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,6 +26,8 @@
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
 
+#include <mach/map.h>
+
 #include "common.h"
 #include "regs-pmu.h"
 
@@ -41,7 +43,7 @@ extern void exynos4_secondary_startup(void);
  */
 void exynos_cpu_power_down(int cpu)
 {
-        __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+        pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 }
 
 /**
@@ -52,8 +54,8 @@ void exynos_cpu_power_down(int cpu)
  */
 void exynos_cpu_power_up(int cpu)
 {
-        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+        pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                        EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 }
 
 /**
@@ -63,7 +65,7 @@ void exynos_cpu_power_up(int cpu)
  */
 int exynos_cpu_power_state(int cpu)
 {
-        return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+        return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
                         S5P_CORE_LOCAL_PWR_EN);
 }
 
@@ -73,7 +75,7 @@ int exynos_cpu_power_state(int cpu)
  */
 void exynos_cluster_power_down(int cluster)
 {
-        __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+        pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 }
 
 /**
@@ -82,8 +84,8 @@ void exynos_cluster_power_down(int cluster)
  */
 void exynos_cluster_power_up(int cluster)
 {
-        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-                     EXYNOS_COMMON_CONFIGURATION(cluster));
+        pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                        EXYNOS_COMMON_CONFIGURATION(cluster));
 }
 
 /**
@@ -93,14 +95,14 @@ void exynos_cluster_power_up(int cluster)
  */
 int exynos_cluster_power_state(int cluster)
 {
-        return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
-                        S5P_CORE_LOCAL_PWR_EN);
+        return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+                S5P_CORE_LOCAL_PWR_EN);
 }
 
 static inline void __iomem *cpu_boot_reg_base(void)
 {
         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
-                return S5P_INFORM5;
+                return pmu_base_addr + S5P_INFORM5;
         return sysram_base_addr;
 }
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 6ab68a068e93..18646b7e226b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -28,7 +28,6 @@
 #include <asm/suspend.h>
 
 #include <plat/pm-common.h>
-#include <plat/pll.h>
 #include <plat/regs-srom.h>
 
 #include <mach/map.h>
@@ -102,11 +101,15 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 }
 
 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-                        (sysram_base_addr + 0x24) : S5P_INFORM0))
+                        pmu_base_addr + S5P_INFORM7 : \
+                        (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (sysram_base_addr + 0x24) : \
+                        pmu_base_addr + S5P_INFORM0))
 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                        S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-                        (sysram_base_addr + 0x20) : S5P_INFORM1))
+                        pmu_base_addr + S5P_INFORM6 : \
+                        (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (sysram_base_addr + 0x20) : \
+                        pmu_base_addr + S5P_INFORM1))
 
 #define S5P_CHECK_AFTR  0xFCBA0D10
 #define S5P_CHECK_SLEEP 0x00000BAD
@@ -114,7 +117,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 static void exynos_set_wakeupmask(long mask)
 {
-        __raw_writel(mask, S5P_WAKEUP_MASK);
+        pmu_raw_writel(mask, S5P_WAKEUP_MASK);
 }
 
 static void exynos_cpu_set_boot_vector(long flags)
@@ -191,27 +194,27 @@ static void exynos_pm_prepare(void)
         unsigned int tmp;
 
         /* Set wake-up mask registers */
-        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-        __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+        pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+        pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 
         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
         if (soc_is_exynos5250()) {
                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
-                tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+                tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
-                __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+                pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
         }
 
         /* Set value of power down register for sleep mode */
 
         exynos_sys_powerdown_conf(SYS_SLEEP);
-        __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+        pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
         /* ensure at least INFORM0 has the resume address */
 
-        __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+        pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 }
 
 static void exynos_pm_central_suspend(void)
@@ -219,9 +222,9 @@ static void exynos_pm_central_suspend(void)
         unsigned long tmp;
 
         /* Setting Central Sequence Register for power down mode */
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+        pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 }
 
 static int exynos_pm_suspend(void)
@@ -233,7 +236,7 @@ static int exynos_pm_suspend(void)
         /* Setting SEQ_OPTION register */
 
         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+        pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
                 exynos_cpu_save_register();
@@ -251,12 +254,12 @@ static int exynos_pm_central_resume(void)
          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
          * in this situation.
          */
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
-                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+                pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
                 /* clear the wakeup state register */
-                __raw_writel(0x0, S5P_WAKEUP_STAT);
+                pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
                 /* No need to perform below restore code */
                 return -1;
         }
@@ -274,13 +277,13 @@ static void exynos_pm_resume(void)
 
         /* For release retention */
 
-        __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
-        __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+        pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 
         if (soc_is_exynos5250())
                 s3c_pm_do_restore(exynos5_sys_save,
@@ -294,7 +297,7 @@ static void exynos_pm_resume(void)
 early_wakeup:
 
         /* Clear SLEEP mode set in INFORM1 */
-        __raw_writel(0x0, S5P_INFORM1);
+        pmu_raw_writel(0x0, S5P_INFORM1);
 
         return;
 }
@@ -338,7 +341,7 @@ static int exynos_suspend_enter(suspend_state_t state)
         s3c_pm_restore_uarts();
 
         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
-                        __raw_readl(S5P_WAKEUP_STAT));
+                        pmu_raw_readl(S5P_WAKEUP_STAT));
 
         s3c_pm_check_restore();
 
@@ -408,9 +411,9 @@ void __init exynos_pm_init(void)
         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
         /* All wakeup disable */
-        tmp = __raw_readl(S5P_WAKEUP_MASK);
+        tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
         tmp |= ((0xFF << 8) | (0x1F << 1));
-        __raw_writel(tmp, S5P_WAKEUP_MASK);
+        pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 
         register_syscore_ops(&exynos_pm_syscore_ops);
         suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index dcfcb44c3c55..ff9d23f0a7d9 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -18,7 +18,7 @@
 static const struct exynos_pmu_conf *exynos_pmu_config;
 
 static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
-        /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+        /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
@@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
 };
 
 static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
-        /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+        /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
         { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
         { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
         { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
@@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static void __iomem * const exynos5_list_both_cnt_feed[] = {
+static unsigned int const exynos5_list_both_cnt_feed[] = {
         EXYNOS5_ARM_CORE0_OPTION,
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
         EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
 
-static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
+static unsigned int const exynos5_list_diable_wfi_wfe[] = {
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_FSYS_ARM_OPTION,
         EXYNOS5_ISP_ARM_OPTION,
@@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
          * Enable both SC_FEEDBACK and SC_COUNTER
          */
         for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
-                tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+                tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
                 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
                         EXYNOS5_USE_SC_COUNTER);
-                __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+                pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
         }
 
         /*
          * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
          */
-        tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+        tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
         tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
-        __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+        pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
 
         /*
          * Disable WFI/WFE on XXX_OPTION
          */
         for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
-                tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+                tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
                 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
                          EXYNOS5_OPTION_USE_STANDBYWFI);
-                __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+                pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
         }
 }
 
@@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
         if (soc_is_exynos5250())
                 exynos5_init_pmu();
 
-        for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
-                __raw_writel(exynos_pmu_config[i].val[mode],
-                                exynos_pmu_config[i].reg);
+        for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
+                pmu_raw_writel(exynos_pmu_config[i].val[mode],
+                                exynos_pmu_config[i].offset);
 
         if (soc_is_exynos4412()) {
-                for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
-                        __raw_writel(exynos4412_pmu_config[i].val[mode],
-                                exynos4412_pmu_config[i].reg);
+                for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
+                        pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
+                                        exynos4412_pmu_config[i].offset);
         }
 }
 
@@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
                  * When SYS_WDTRESET is set, watchdog timer reset request
                  * is ignored by power management unit.
                  */
-                value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+                value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
                 value &= ~EXYNOS5_SYS_WDTRESET;
-                __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+                pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
 
-                value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+                value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
                 value &= ~EXYNOS5_SYS_WDTRESET;
-                __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+                pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
 
                 exynos_pmu_config = exynos5250_pmu_config;
                 pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1993e6bd5388..96a1569262b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,300 +12,298 @@
 #ifndef __ASM_ARCH_REGS_PMU_H
 #define __ASM_ARCH_REGS_PMU_H __FILE__
 
-#include <mach/map.h>
-
-#define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
-
-#define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
+#define S5P_CENTRAL_SEQ_CONFIGURATION           0x0200
 
 #define S5P_CENTRAL_LOWPWR_CFG                  (1 << 16)
 
-#define S5P_CENTRAL_SEQ_OPTION                  S5P_PMUREG(0x0208)
+#define S5P_CENTRAL_SEQ_OPTION                  0x0208
 
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
 
-#define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
-#define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
+#define EXYNOS_SWRESET                          0x0400
+#define EXYNOS5440_SWRESET                      0x00C4
 
-#define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
+#define S5P_WAKEUP_STAT                         0x0600
+#define S5P_EINT_WAKEUP_MASK                    0x0604
+#define S5P_WAKEUP_MASK                         0x0608
 
-#define S5P_INFORM0                             S5P_PMUREG(0x0800)
-#define S5P_INFORM1                             S5P_PMUREG(0x0804)
-#define S5P_INFORM5                             S5P_PMUREG(0x0814)
-#define S5P_INFORM6                             S5P_PMUREG(0x0818)
-#define S5P_INFORM7                             S5P_PMUREG(0x081C)
-#define S5P_PMU_SPARE3                          S5P_PMUREG(0x090C)
+#define S5P_INFORM0                             0x0800
+#define S5P_INFORM1                             0x0804
+#define S5P_INFORM5                             0x0814
+#define S5P_INFORM6                             0x0818
+#define S5P_INFORM7                             0x081C
+#define S5P_PMU_SPARE3                          0x090C
 
-#define S5P_ARM_CORE0_LOWPWR                    S5P_PMUREG(0x1000)
-#define S5P_DIS_IRQ_CORE0                       S5P_PMUREG(0x1004)
-#define S5P_DIS_IRQ_CENTRAL0                    S5P_PMUREG(0x1008)
-#define S5P_ARM_CORE1_LOWPWR                    S5P_PMUREG(0x1010)
-#define S5P_DIS_IRQ_CORE1                       S5P_PMUREG(0x1014)
-#define S5P_DIS_IRQ_CENTRAL1                    S5P_PMUREG(0x1018)
-#define S5P_ARM_COMMON_LOWPWR                   S5P_PMUREG(0x1080)
-#define S5P_L2_0_LOWPWR                         S5P_PMUREG(0x10C0)
-#define S5P_L2_1_LOWPWR                         S5P_PMUREG(0x10C4)
-#define S5P_CMU_ACLKSTOP_LOWPWR                 S5P_PMUREG(0x1100)
-#define S5P_CMU_SCLKSTOP_LOWPWR                 S5P_PMUREG(0x1104)
-#define S5P_CMU_RESET_LOWPWR                    S5P_PMUREG(0x110C)
-#define S5P_APLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1120)
-#define S5P_MPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1124)
-#define S5P_VPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1128)
-#define S5P_EPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x112C)
-#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR        S5P_PMUREG(0x1138)
-#define S5P_CMU_RESET_GPSALIVE_LOWPWR           S5P_PMUREG(0x113C)
-#define S5P_CMU_CLKSTOP_CAM_LOWPWR              S5P_PMUREG(0x1140)
-#define S5P_CMU_CLKSTOP_TV_LOWPWR               S5P_PMUREG(0x1144)
-#define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
-#define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
-#define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
-#define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
-#define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
-#define S5P_CMU_RESET_TV_LOWPWR                 S5P_PMUREG(0x1164)
-#define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
-#define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
-#define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
-#define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
-#define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
-#define S5P_TOP_RETENTION_LOWPWR                S5P_PMUREG(0x1184)
-#define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
-#define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
-#define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
-#define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
-#define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
-#define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
-#define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
-#define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
-#define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
-#define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
-#define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
-#define S5P_PAD_RETENTION_UART_LOWPWR           S5P_PMUREG(0x1224)
-#define S5P_PAD_RETENTION_MMCA_LOWPWR           S5P_PMUREG(0x1228)
-#define S5P_PAD_RETENTION_MMCB_LOWPWR           S5P_PMUREG(0x122C)
-#define S5P_PAD_RETENTION_EBIA_LOWPWR           S5P_PMUREG(0x1230)
-#define S5P_PAD_RETENTION_EBIB_LOWPWR           S5P_PMUREG(0x1234)
-#define S5P_PAD_RETENTION_ISOLATION_LOWPWR      S5P_PMUREG(0x1240)
-#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR        S5P_PMUREG(0x1260)
-#define S5P_XUSBXTI_LOWPWR                      S5P_PMUREG(0x1280)
-#define S5P_XXTI_LOWPWR                         S5P_PMUREG(0x1284)
-#define S5P_EXT_REGULATOR_LOWPWR                S5P_PMUREG(0x12C0)
-#define S5P_GPIO_MODE_LOWPWR                    S5P_PMUREG(0x1300)
-#define S5P_GPIO_MODE_MAUDIO_LOWPWR             S5P_PMUREG(0x1340)
-#define S5P_CAM_LOWPWR                          S5P_PMUREG(0x1380)
-#define S5P_TV_LOWPWR                           S5P_PMUREG(0x1384)
-#define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
-#define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
-#define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
-#define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
-#define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
-#define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
+#define S5P_ARM_CORE0_LOWPWR                    0x1000
+#define S5P_DIS_IRQ_CORE0                       0x1004
+#define S5P_DIS_IRQ_CENTRAL0                    0x1008
+#define S5P_ARM_CORE1_LOWPWR                    0x1010
+#define S5P_DIS_IRQ_CORE1                       0x1014
+#define S5P_DIS_IRQ_CENTRAL1                    0x1018
+#define S5P_ARM_COMMON_LOWPWR                   0x1080
+#define S5P_L2_0_LOWPWR                         0x10C0
+#define S5P_L2_1_LOWPWR                         0x10C4
+#define S5P_CMU_ACLKSTOP_LOWPWR                 0x1100
+#define S5P_CMU_SCLKSTOP_LOWPWR                 0x1104
+#define S5P_CMU_RESET_LOWPWR                    0x110C
+#define S5P_APLL_SYSCLK_LOWPWR                  0x1120
+#define S5P_MPLL_SYSCLK_LOWPWR                  0x1124
+#define S5P_VPLL_SYSCLK_LOWPWR                  0x1128
+#define S5P_EPLL_SYSCLK_LOWPWR                  0x112C
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR        0x1138
+#define S5P_CMU_RESET_GPSALIVE_LOWPWR           0x113C
+#define S5P_CMU_CLKSTOP_CAM_LOWPWR              0x1140
+#define S5P_CMU_CLKSTOP_TV_LOWPWR               0x1144
+#define S5P_CMU_CLKSTOP_MFC_LOWPWR              0x1148
+#define S5P_CMU_CLKSTOP_G3D_LOWPWR              0x114C
+#define S5P_CMU_CLKSTOP_LCD0_LOWPWR             0x1150
+#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           0x1158
+#define S5P_CMU_CLKSTOP_GPS_LOWPWR              0x115C
+#define S5P_CMU_RESET_CAM_LOWPWR                0x1160
+#define S5P_CMU_RESET_TV_LOWPWR                 0x1164
+#define S5P_CMU_RESET_MFC_LOWPWR                0x1168
+#define S5P_CMU_RESET_G3D_LOWPWR                0x116C
+#define S5P_CMU_RESET_LCD0_LOWPWR               0x1170
+#define S5P_CMU_RESET_MAUDIO_LOWPWR             0x1178
+#define S5P_CMU_RESET_GPS_LOWPWR                0x117C
+#define S5P_TOP_BUS_LOWPWR                      0x1180
+#define S5P_TOP_RETENTION_LOWPWR                0x1184
+#define S5P_TOP_PWR_LOWPWR                      0x1188
+#define S5P_LOGIC_RESET_LOWPWR                  0x11A0
+#define S5P_ONENAND_MEM_LOWPWR                  0x11C0
+#define S5P_G2D_ACP_MEM_LOWPWR                  0x11C8
+#define S5P_USBOTG_MEM_LOWPWR                   0x11CC
+#define S5P_HSMMC_MEM_LOWPWR                    0x11D0
+#define S5P_CSSYS_MEM_LOWPWR                    0x11D4
+#define S5P_SECSS_MEM_LOWPWR                    0x11D8
+#define S5P_PAD_RETENTION_DRAM_LOWPWR           0x1200
+#define S5P_PAD_RETENTION_MAUDIO_LOWPWR         0x1204
+#define S5P_PAD_RETENTION_GPIO_LOWPWR           0x1220
+#define S5P_PAD_RETENTION_UART_LOWPWR           0x1224
+#define S5P_PAD_RETENTION_MMCA_LOWPWR           0x1228
+#define S5P_PAD_RETENTION_MMCB_LOWPWR           0x122C
+#define S5P_PAD_RETENTION_EBIA_LOWPWR           0x1230
+#define S5P_PAD_RETENTION_EBIB_LOWPWR           0x1234
+#define S5P_PAD_RETENTION_ISOLATION_LOWPWR      0x1240
+#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR        0x1260
+#define S5P_XUSBXTI_LOWPWR                      0x1280
+#define S5P_XXTI_LOWPWR                         0x1284
+#define S5P_EXT_REGULATOR_LOWPWR                0x12C0
+#define S5P_GPIO_MODE_LOWPWR                    0x1300
+#define S5P_GPIO_MODE_MAUDIO_LOWPWR             0x1340
+#define S5P_CAM_LOWPWR                          0x1380
+#define S5P_TV_LOWPWR                           0x1384
+#define S5P_MFC_LOWPWR                          0x1388
+#define S5P_G3D_LOWPWR                          0x138C
+#define S5P_LCD0_LOWPWR                         0x1390
+#define S5P_MAUDIO_LOWPWR                       0x1398
+#define S5P_GPS_LOWPWR                          0x139C
+#define S5P_GPS_ALIVE_LOWPWR                    0x13A0
 
-#define EXYNOS_ARM_CORE0_CONFIGURATION          S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE0_CONFIGURATION          0x2000
 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr)      \
                         (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
 #define EXYNOS_ARM_CORE_STATUS(_nr)             \
                         (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
 
-#define EXYNOS_ARM_COMMON_CONFIGURATION         S5P_PMUREG(0x2500)
+#define EXYNOS_ARM_COMMON_CONFIGURATION         0x2500
 #define EXYNOS_COMMON_CONFIGURATION(_nr)        \
                         (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
 #define EXYNOS_COMMON_STATUS(_nr)               \
                         (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_COMMON_OPTION(_nr)               \
+                        (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
 
-#define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
-#define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
-#define S5P_PAD_RET_UART_OPTION                 S5P_PMUREG(0x3128)
-#define S5P_PAD_RET_MMCA_OPTION                 S5P_PMUREG(0x3148)
-#define S5P_PAD_RET_MMCB_OPTION                 S5P_PMUREG(0x3168)
-#define S5P_PAD_RET_EBIA_OPTION                 S5P_PMUREG(0x3188)
-#define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
+#define S5P_PAD_RET_MAUDIO_OPTION               0x3028
+#define S5P_PAD_RET_GPIO_OPTION                 0x3108
+#define S5P_PAD_RET_UART_OPTION                 0x3128
+#define S5P_PAD_RET_MMCA_OPTION                 0x3148
+#define S5P_PAD_RET_MMCB_OPTION                 0x3168
+#define S5P_PAD_RET_EBIA_OPTION                 0x3188
+#define S5P_PAD_RET_EBIB_OPTION                 0x31A8
 
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 
 /* Only for EXYNOS4210 */
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
-#define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
-#define S5P_PCIE_MEM_LOWPWR             S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
-#define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR     0x1154
+#define S5P_CMU_RESET_LCD1_LOWPWR       0x1174
+#define S5P_MODIMIF_MEM_LOWPWR          0x11C4
+#define S5P_PCIE_MEM_LOWPWR             0x11E0
+#define S5P_SATA_MEM_LOWPWR             0x11E4
+#define S5P_LCD1_LOWPWR                 0x1394
 
 /* Only for EXYNOS4x12 */
-#define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
-#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
-#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
-#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1110)
-#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1114)
-#define S5P_CMU_RESET_COREBLK_LOWPWR            S5P_PMUREG(0x111C)
-#define S5P_MPLLUSER_SYSCLK_LOWPWR              S5P_PMUREG(0x1130)
-#define S5P_CMU_CLKSTOP_ISP_LOWPWR              S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_ISP_LOWPWR                S5P_PMUREG(0x1174)
-#define S5P_TOP_BUS_COREBLK_LOWPWR              S5P_PMUREG(0x1190)
-#define S5P_TOP_RETENTION_COREBLK_LOWPWR        S5P_PMUREG(0x1194)
-#define S5P_TOP_PWR_COREBLK_LOWPWR              S5P_PMUREG(0x1198)
-#define S5P_OSCCLK_GATE_LOWPWR                  S5P_PMUREG(0x11A4)
-#define S5P_LOGIC_RESET_COREBLK_LOWPWR          S5P_PMUREG(0x11B0)
-#define S5P_OSCCLK_GATE_COREBLK_LOWPWR          S5P_PMUREG(0x11B4)
-#define S5P_HSI_MEM_LOWPWR                      S5P_PMUREG(0x11C4)
-#define S5P_ROTATOR_MEM_LOWPWR                  S5P_PMUREG(0x11DC)
-#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   S5P_PMUREG(0x123C)
-#define S5P_PAD_ISOLATION_COREBLK_LOWPWR        S5P_PMUREG(0x1250)
-#define S5P_GPIO_MODE_COREBLK_LOWPWR            S5P_PMUREG(0x1320)
-#define S5P_TOP_ASB_RESET_LOWPWR                S5P_PMUREG(0x1344)
-#define S5P_TOP_ASB_ISOLATION_LOWPWR            S5P_PMUREG(0x1348)
-#define S5P_ISP_LOWPWR                          S5P_PMUREG(0x1394)
-#define S5P_DRAM_FREQ_DOWN_LOWPWR               S5P_PMUREG(0x13B0)
-#define S5P_DDRPHY_DLLOFF_LOWPWR                S5P_PMUREG(0x13B4)
-#define S5P_CMU_SYSCLK_ISP_LOWPWR               S5P_PMUREG(0x13B8)
-#define S5P_CMU_SYSCLK_GPS_LOWPWR               S5P_PMUREG(0x13BC)
-#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           S5P_PMUREG(0x13C0)
+#define S5P_ISP_ARM_LOWPWR                      0x1050
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        0x1054
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      0x1058
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         0x1110
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         0x1114
+#define S5P_CMU_RESET_COREBLK_LOWPWR            0x111C
+#define S5P_MPLLUSER_SYSCLK_LOWPWR              0x1130
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR              0x1154
+#define S5P_CMU_RESET_ISP_LOWPWR                0x1174
+#define S5P_TOP_BUS_COREBLK_LOWPWR              0x1190
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR        0x1194
+#define S5P_TOP_PWR_COREBLK_LOWPWR              0x1198
+#define S5P_OSCCLK_GATE_LOWPWR                  0x11A4
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR          0x11B0
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR          0x11B4
+#define S5P_HSI_MEM_LOWPWR                      0x11C4
+#define S5P_ROTATOR_MEM_LOWPWR                  0x11DC
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   0x123C
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR        0x1250
+#define S5P_GPIO_MODE_COREBLK_LOWPWR            0x1320
+#define S5P_TOP_ASB_RESET_LOWPWR                0x1344
+#define S5P_TOP_ASB_ISOLATION_LOWPWR            0x1348
+#define S5P_ISP_LOWPWR                          0x1394
+#define S5P_DRAM_FREQ_DOWN_LOWPWR               0x13B0
+#define S5P_DDRPHY_DLLOFF_LOWPWR                0x13B4
+#define S5P_CMU_SYSCLK_ISP_LOWPWR               0x13B8
+#define S5P_CMU_SYSCLK_GPS_LOWPWR               0x13BC
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           0x13C0
 
-#define S5P_ARM_L2_0_OPTION                     S5P_PMUREG(0x2608)
-#define S5P_ARM_L2_1_OPTION                     S5P_PMUREG(0x2628)
-#define S5P_ONENAND_MEM_OPTION                  S5P_PMUREG(0x2E08)
-#define S5P_HSI_MEM_OPTION                      S5P_PMUREG(0x2E28)
-#define S5P_G2D_ACP_MEM_OPTION                  S5P_PMUREG(0x2E48)
-#define S5P_USBOTG_MEM_OPTION                   S5P_PMUREG(0x2E68)
-#define S5P_HSMMC_MEM_OPTION                    S5P_PMUREG(0x2E88)
-#define S5P_CSSYS_MEM_OPTION                    S5P_PMUREG(0x2EA8)
-#define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
-#define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
+#define S5P_ARM_L2_0_OPTION                     0x2608
+#define S5P_ARM_L2_1_OPTION                     0x2628
+#define S5P_ONENAND_MEM_OPTION                  0x2E08
+#define S5P_HSI_MEM_OPTION                      0x2E28
+#define S5P_G2D_ACP_MEM_OPTION                  0x2E48
+#define S5P_USBOTG_MEM_OPTION                   0x2E68
+#define S5P_HSMMC_MEM_OPTION                    0x2E88
+#define S5P_CSSYS_MEM_OPTION                    0x2EA8
+#define S5P_SECSS_MEM_OPTION                    0x2EC8
+#define S5P_ROTATOR_MEM_OPTION                  0x2F48
 
 /* Only for EXYNOS4412 */
-#define S5P_ARM_CORE2_LOWPWR                    S5P_PMUREG(0x1020)
-#define S5P_DIS_IRQ_CORE2                       S5P_PMUREG(0x1024)
-#define S5P_DIS_IRQ_CENTRAL2                    S5P_PMUREG(0x1028)
-#define S5P_ARM_CORE3_LOWPWR                    S5P_PMUREG(0x1030)
-#define S5P_DIS_IRQ_CORE3                       S5P_PMUREG(0x1034)
-#define S5P_DIS_IRQ_CENTRAL3                    S5P_PMUREG(0x1038)
+#define S5P_ARM_CORE2_LOWPWR                    0x1020
+#define S5P_DIS_IRQ_CORE2                       0x1024
+#define S5P_DIS_IRQ_CENTRAL2                    0x1028
+#define S5P_ARM_CORE3_LOWPWR                    0x1030
+#define S5P_DIS_IRQ_CORE3                       0x1034
+#define S5P_DIS_IRQ_CENTRAL3                    0x1038
 
 /* For EXYNOS5 */
 
-#define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
-#define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
+#define EXYNOS5_AUTO_WDTRESET_DISABLE                           0x0408
+#define EXYNOS5_MASK_WDTRESET_REQUEST                           0x040C
 
 #define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
 
-#define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           S5P_PMUREG(0x1000)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1004)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1008)
-#define EXYNOS5_ARM_CORE1_SYS_PWR_REG                           S5P_PMUREG(0x1010)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1014)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1018)
-#define EXYNOS5_FSYS_ARM_SYS_PWR_REG                            S5P_PMUREG(0x1040)
-#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG            S5P_PMUREG(0x1048)
-#define EXYNOS5_ISP_ARM_SYS_PWR_REG                             S5P_PMUREG(0x1050)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG               S5P_PMUREG(0x1054)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG             S5P_PMUREG(0x1058)
-#define EXYNOS5_ARM_COMMON_SYS_PWR_REG                          S5P_PMUREG(0x1080)
-#define EXYNOS5_ARM_L2_SYS_PWR_REG                              S5P_PMUREG(0x10C0)
-#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1100)
-#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1104)
-#define EXYNOS5_CMU_RESET_SYS_PWR_REG                           S5P_PMUREG(0x110C)
-#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1120)
-#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1124)
-#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x112C)
-#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG                      S5P_PMUREG(0x1130)
-#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG                       S5P_PMUREG(0x1134)
-#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG                      S5P_PMUREG(0x1138)
-#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1140)
-#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1144)
-#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1148)
-#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x114C)
-#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1150)
-#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1154)
-#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1164)
-#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1170)
-#define EXYNOS5_TOP_BUS_SYS_PWR_REG                             S5P_PMUREG(0x1180)
-#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG                       S5P_PMUREG(0x1184)
-#define EXYNOS5_TOP_PWR_SYS_PWR_REG                             S5P_PMUREG(0x1188)
-#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1190)
-#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1194)
-#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1198)
-#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG                         S5P_PMUREG(0x11A0)
-#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG                         S5P_PMUREG(0x11A4)
-#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B0)
-#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B4)
-#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11C0)
-#define EXYNOS5_G2D_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11C8)
-#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11CC)
-#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D0)
-#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D4)
-#define EXYNOS5_SECSS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D8)
-#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG                         S5P_PMUREG(0x11DC)
-#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E0)
-#define EXYNOS5_INTROM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E4)
-#define EXYNOS5_JPEG_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11E8)
-#define EXYNOS5_HSI_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11EC)
-#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11F4)
-#define EXYNOS5_SATA_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11FC)
-#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG                  S5P_PMUREG(0x1200)
-#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG                   S5P_PMUREG(0x1204)
-#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG                S5P_PMUREG(0x1208)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG                  S5P_PMUREG(0x1220)
-#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG                  S5P_PMUREG(0x1224)
-#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG                  S5P_PMUREG(0x1228)
-#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG                  S5P_PMUREG(0x122C)
-#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG                  S5P_PMUREG(0x1230)
-#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG                  S5P_PMUREG(0x1234)
-#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG                   S5P_PMUREG(0x1238)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG           S5P_PMUREG(0x123C)
-#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG                       S5P_PMUREG(0x1240)
-#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1250)
-#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG                         S5P_PMUREG(0x1260)
-#define EXYNOS5_XUSBXTI_SYS_PWR_REG                             S5P_PMUREG(0x1280)
-#define EXYNOS5_XXTI_SYS_PWR_REG                                S5P_PMUREG(0x1284)
-#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG                       S5P_PMUREG(0x12C0)
-#define EXYNOS5_GPIO_MODE_SYS_PWR_REG                           S5P_PMUREG(0x1300)
-#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x1320)
-#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1340)
-#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG                       S5P_PMUREG(0x1344)
-#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG                   S5P_PMUREG(0x1348)
-#define EXYNOS5_GSCL_SYS_PWR_REG                                S5P_PMUREG(0x1400)
-#define EXYNOS5_ISP_SYS_PWR_REG                                 S5P_PMUREG(0x1404)
-#define EXYNOS5_MFC_SYS_PWR_REG                                 S5P_PMUREG(0x1408)
-#define EXYNOS5_G3D_SYS_PWR_REG                                 S5P_PMUREG(0x140C)
-#define EXYNOS5_DISP1_SYS_PWR_REG                               S5P_PMUREG(0x1414)
-#define EXYNOS5_MAU_SYS_PWR_REG                                 S5P_PMUREG(0x1418)
-#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG                    S5P_PMUREG(0x1480)
-#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG                     S5P_PMUREG(0x1484)
-#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG                     S5P_PMUREG(0x1488)
-#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG                     S5P_PMUREG(0x148C)
-#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG                   S5P_PMUREG(0x1494)
-#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG                     S5P_PMUREG(0x1498)
-#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG                     S5P_PMUREG(0x14C0)
-#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG                      S5P_PMUREG(0x14C4)
-#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG                      S5P_PMUREG(0x14C8)
-#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG                      S5P_PMUREG(0x14CC)
-#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG                    S5P_PMUREG(0x14D4)
-#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG                      S5P_PMUREG(0x14D8)
-#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG                      S5P_PMUREG(0x1580)
-#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG                       S5P_PMUREG(0x1584)
-#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG                       S5P_PMUREG(0x1588)
-#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG                       S5P_PMUREG(0x158C)
-#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG                     S5P_PMUREG(0x1594)
-#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1598)
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           0x1000
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             0x1004
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           0x1008
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG                           0x1010
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG             0x1014
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG           0x1018
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG                            0x1040
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG            0x1048
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG                             0x1050
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG               0x1054
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG             0x1058
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG                          0x1080
+#define EXYNOS5_ARM_L2_SYS_PWR_REG                              0x10C0
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG                        0x1100
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG                        0x1104
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG                           0x110C
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG                 0x1120
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG                 0x1124
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG                    0x112C
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG                      0x1130
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG                       0x1134
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG                      0x1138
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG                         0x1140
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG                         0x1144
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG                         0x1148
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG                         0x114C
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG                         0x1150
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG                         0x1154
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG                     0x1164
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG                     0x1170
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG                             0x1180
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG                       0x1184
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG                             0x1188
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG                      0x1190
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG                0x1194
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG                      0x1198
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG                         0x11A0
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG                         0x11A4
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG                  0x11B0
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG                  0x11B4
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG                          0x11C0
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG                             0x11C8
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG                          0x11CC
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG                           0x11D0
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG                           0x11D4
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG                           0x11D8
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG                         0x11DC
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG                          0x11E0
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG                          0x11E4
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG                            0x11E8
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG                             0x11EC
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG                          0x11F4
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG                            0x11FC
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG                  0x1200
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG                   0x1204
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG                0x1208
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG                  0x1220
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG                  0x1224
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG                  0x1228
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG                  0x122C
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG                  0x1230
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG                  0x1234
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG                   0x1238
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG           0x123C
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG                       0x1240
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG                0x1250
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG                         0x1260
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG                             0x1280
+#define EXYNOS5_XXTI_SYS_PWR_REG                                0x1284
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG                       0x12C0
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG                           0x1300
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG                    0x1320
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG                       0x1340
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG                       0x1344
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG                   0x1348
+#define EXYNOS5_GSCL_SYS_PWR_REG                                0x1400
+#define EXYNOS5_ISP_SYS_PWR_REG                                 0x1404
+#define EXYNOS5_MFC_SYS_PWR_REG                                 0x1408
+#define EXYNOS5_G3D_SYS_PWR_REG                                 0x140C
+#define EXYNOS5_DISP1_SYS_PWR_REG                               0x1414
+#define EXYNOS5_MAU_SYS_PWR_REG                                 0x1418
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG                    0x1480
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG                     0x1484
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG                     0x1488
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG                     0x148C
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG                   0x1494
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG                     0x1498
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG                     0x14C0
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG                      0x14C4
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG                      0x14C8
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG                      0x14CC
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG                    0x14D4
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG                      0x14D8
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG                      0x1580
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG                       0x1584
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG                       0x1588
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG                       0x158C
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG                     0x1594
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG                       0x1598
 
-#define EXYNOS5_ARM_CORE0_OPTION                                S5P_PMUREG(0x2008)
-#define EXYNOS5_ARM_CORE1_OPTION                                S5P_PMUREG(0x2088)
-#define EXYNOS5_FSYS_ARM_OPTION                                 S5P_PMUREG(0x2208)
-#define EXYNOS5_ISP_ARM_OPTION                                  S5P_PMUREG(0x2288)
-#define EXYNOS5_ARM_COMMON_OPTION                               S5P_PMUREG(0x2408)
-#define EXYNOS5_ARM_L2_OPTION                                   S5P_PMUREG(0x2608)
-#define EXYNOS5_TOP_PWR_OPTION                                  S5P_PMUREG(0x2C48)
-#define EXYNOS5_TOP_PWR_SYSMEM_OPTION                           S5P_PMUREG(0x2CC8)
-#define EXYNOS5_JPEG_MEM_OPTION                                 S5P_PMUREG(0x2F48)
-#define EXYNOS5_GSCL_OPTION                                     S5P_PMUREG(0x4008)
-#define EXYNOS5_ISP_OPTION                                      S5P_PMUREG(0x4028)
-#define EXYNOS5_MFC_OPTION                                      S5P_PMUREG(0x4048)
-#define EXYNOS5_G3D_OPTION                                      S5P_PMUREG(0x4068)
-#define EXYNOS5_DISP1_OPTION                                    S5P_PMUREG(0x40A8)
-#define EXYNOS5_MAU_OPTION                                      S5P_PMUREG(0x40C8)
+#define EXYNOS5_ARM_CORE0_OPTION                                0x2008
+#define EXYNOS5_ARM_CORE1_OPTION                                0x2088
+#define EXYNOS5_FSYS_ARM_OPTION                                 0x2208
+#define EXYNOS5_ISP_ARM_OPTION                                  0x2288
+#define EXYNOS5_ARM_COMMON_OPTION                               0x2408
+#define EXYNOS5_ARM_L2_OPTION                                   0x2608
+#define EXYNOS5_TOP_PWR_OPTION                                  0x2C48
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION                           0x2CC8
+#define EXYNOS5_JPEG_MEM_OPTION                                 0x2F48
+#define EXYNOS5_GSCL_OPTION                                     0x4008
+#define EXYNOS5_ISP_OPTION                                      0x4028
+#define EXYNOS5_MFC_OPTION                                      0x4048
+#define EXYNOS5_G3D_OPTION                                      0x4068
+#define EXYNOS5_DISP1_OPTION                                    0x40A8
+#define EXYNOS5_MAU_OPTION                                      0x40C8
 
 #define EXYNOS5_USE_SC_FEEDBACK                                 (1 << 1)
 #define EXYNOS5_USE_SC_COUNTER                                  (1 << 0)
@@ -319,4 +317,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL                              0x3
 
+#include <asm/cputype.h>
+#define MAX_CPUS_IN_CLUSTER     4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+        return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
+                 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index feee4dbb0760..984882943f77 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,12 +1,36 @@
-config ARCH_HI3xxx
-        bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+        bool "Hisilicon SoC Support"
+        depends on ARCH_MULTIPLATFORM
         select ARM_AMBA
         select ARM_GIC
         select ARM_TIMER_SP804
+        select POWER_RESET
+        select POWER_RESET_HISI
+        select POWER_SUPPLY
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+        bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7
+        select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select PINCTRL
+        select PINCTRL_SINGLE
+        help
+          Support for Hisilicon Hi36xx SoC family
+
+config ARCH_HIX5HD2
+        bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
         select CACHE_L2X0
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select PINCTRL
         select PINCTRL_SINGLE
         help
-          Support for Hisilicon Hi36xx/Hi37xx processor family
+          Support for Hisilicon HIX5HD2 SoC family
+endmenu
+
+endif
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index 2ae1b59267c2..ee2506b9cde3 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -3,4 +3,4 @@
 #
 
 obj-y   += hisilicon.o
-obj-$(CONFIG_SMP)               += platsmp.o hotplug.o
+obj-$(CONFIG_SMP)               += platsmp.o hotplug.o headsmp.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index af23ec204538..88b1f487d065 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,4 +12,9 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
 extern int hi3xxx_cpu_kill(unsigned int cpu);
 extern void hi3xxx_set_cpu(int cpu, bool enable);
 
+extern void hix5hd2_secondary_startup(void);
+extern struct smp_operations hix5hd2_smp_ops;
+extern void hix5hd2_set_cpu(int cpu, bool enable);
+extern void hix5hd2_cpu_die(unsigned int cpu);
+
 #endif
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
new file mode 100644
index 000000000000..278889c00b77
--- /dev/null
+++ b/arch/arm/mach-hisi/headsmp.S
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (c) 2014 Hisilicon Limited.
+ *  Copyright (c) 2014 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __CPUINIT
+
+ENTRY(hix5hd2_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 741faf3e7100..7cda6dda3cd0 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -14,16 +14,10 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-
-#include <asm/proc-fns.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "core.h"
-
 #define HI3620_SYSCTRL_PHYS_BASE                0xfc802000
 #define HI3620_SYSCTRL_VIRT_BASE                0xfe802000
 
@@ -51,32 +45,6 @@ static void __init hi3620_map_io(void)
         iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
 }
 
-static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
-{
-        struct device_node *np;
-        void __iomem *base;
-        int offset;
-
-        np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
-        if (!np) {
-                pr_err("failed to find hisilicon,sysctrl node\n");
-                return;
-        }
-        base = of_iomap(np, 0);
-        if (!base) {
-                pr_err("failed to map address in hisilicon,sysctrl node\n");
-                return;
-        }
-        if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
-                pr_err("failed to find reboot-offset property\n");
-                return;
-        }
-        writel_relaxed(0xdeadbeef, base + offset);
-
-        while (1)
-                cpu_do_idle();
-}
-
 static const char *hi3xxx_compat[] __initconst = {
         "hisilicon,hi3620-hi4511",
         NULL,
@@ -85,6 +53,13 @@ static const char *hi3xxx_compat[] __initconst = {
 DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
         .map_io         = hi3620_map_io,
         .dt_compat      = hi3xxx_compat,
-        .smp            = smp_ops(hi3xxx_smp_ops),
-        .restart        = hi3xxx_restart,
+MACHINE_END
+
+static const char *hix5hd2_compat[] __initconst = {
+        "hisilicon,hix5hd2",
+        NULL,
+};
+
+DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
+        .dt_compat      = hix5hd2_compat,
 MACHINE_END
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
index abd441b0c604..84e6919f68c7 100644
--- a/arch/arm/mach-hisi/hotplug.c
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -57,6 +57,14 @@
 #define CPU0_NEON_SRST_REQ_EN           (1 << 4)
 #define CPU0_SRST_REQ_EN                (1 << 0)
 
+#define HIX5HD2_PERI_CRG20              0x50
+#define CRG20_CPU1_RESET                (1 << 17)
+
+#define HIX5HD2_PERI_PMC0               0x1000
+#define PMC0_CPU1_WAIT_MTCOMS_ACK       (1 << 8)
+#define PMC0_CPU1_PMC_ENABLE            (1 << 7)
+#define PMC0_CPU1_POWERDOWN             (1 << 3)
+
 enum {
         HI3620_CTRL,
         ERROR_CTRL,
@@ -157,6 +165,50 @@ void hi3xxx_set_cpu(int cpu, bool enable)
                 set_cpu_hi3620(cpu, enable);
 }
 
+static bool hix5hd2_hotplug_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
+        if (np) {
+                ctrl_base = of_iomap(np, 0);
+                return true;
+        }
+        return false;
+}
+
+void hix5hd2_set_cpu(int cpu, bool enable)
+{
+        u32 val = 0;
+
+        if (!ctrl_base)
+                if (!hix5hd2_hotplug_init())
+                        BUG();
+
+        if (enable) {
+                /* power on cpu1 */
+                val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
+                val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
+                val |= PMC0_CPU1_PMC_ENABLE;
+                writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
+                /* unreset */
+                val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
+                val &= ~CRG20_CPU1_RESET;
+                writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
+        } else {
+                /* power down cpu1 */
+                val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
+                val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
+                val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
+                writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
+
+                /* reset */
+                val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
+                val |= CRG20_CPU1_RESET;
+                writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
+        }
+}
+
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -199,4 +251,10 @@ int hi3xxx_cpu_kill(unsigned int cpu)
         hi3xxx_set_cpu(cpu, false);
         return 1;
 }
+
+void hix5hd2_cpu_die(unsigned int cpu)
+{
+        flush_cache_all();
+        hix5hd2_set_cpu(cpu, false);
+}
 #endif
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 471f1ee3be2b..575dd8285f1f 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -17,6 +17,8 @@
 
 #include "core.h"
 
+#define HIX5HD2_BOOT_ADDRESS            0xffff0000
+
 static void __iomem *ctrl_base;
 
 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
@@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu)
         return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
 }
 
-static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
+static void __init hisi_enable_scu_a9(void)
 {
-        struct device_node *np = NULL;
         unsigned long base = 0;
-        u32 offset = 0;
         void __iomem *scu_base = NULL;
 
         if (scu_a9_has_base()) {
@@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
                 scu_enable(scu_base);
                 iounmap(scu_base);
         }
+}
+
+static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np = NULL;
+        u32 offset = 0;
+
+        hisi_enable_scu_a9();
         if (!ctrl_base) {
                 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
                 if (!np) {
@@ -87,3 +95,42 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
         .cpu_kill               = hi3xxx_cpu_kill,
 #endif
 };
+
+static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
+{
+        hisi_enable_scu_a9();
+}
+
+void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
+        void __iomem *virt;
+
+        virt = ioremap(start_addr, PAGE_SIZE);
+
+        writel_relaxed(0xe51ff004, virt);       /* ldr pc, [rc, #-4] */
+        writel_relaxed(jump_addr, virt + 4);    /* pc jump phy address */
+        iounmap(virt);
+}
+
+static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        phys_addr_t jumpaddr;
+
+        jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
+        hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
+        hix5hd2_set_cpu(cpu, true);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        return 0;
+}
+
+
+struct smp_operations hix5hd2_smp_ops __initdata = {
+        .smp_prepare_cpus       = hix5hd2_smp_prepare_cpus,
+        .smp_boot_secondary     = hix5hd2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = hix5hd2_cpu_die,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
+CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ab6bcfd2e220..9de84a215abd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -64,18 +64,8 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
         bool
 
-config ARCH_MX1
-        bool
-
-config ARCH_MX25
-        bool
-
-config MACH_MX27
-        bool
-
 config SOC_IMX1
         bool
-        select ARCH_MX1
         select CPU_ARM920T
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -88,7 +78,6 @@ config SOC_IMX21
 
 config SOC_IMX25
         bool
-        select ARCH_MX25
         select ARCH_MXC_IOMUX_V3
         select CPU_ARM926T
         select MXC_AVIC
@@ -99,7 +88,6 @@ config SOC_IMX27
         select ARCH_HAS_OPP
         select CPU_ARM926T
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX27
         select MXC_AVIC
         select PINCTRL_IMX27
 
@@ -118,18 +106,6 @@ config SOC_IMX35
         select PINCTRL_IMX35
         select SMP_ON_UP if SMP
 
-config SOC_IMX5
-        bool
-        select ARCH_HAS_OPP
-        select ARCH_MXC_IOMUX_V3
-        select MXC_TZIC
-
-config  SOC_IMX51
-        bool
-        select HAVE_IMX_SRC
-        select PINCTRL_IMX51
-        select SOC_IMX5
-
 if ARCH_MULTI_V4T
 
 comment "MX1 platforms:"
@@ -365,15 +341,6 @@ config MACH_IMX27_VISSTRIM_M10
           This includes specific configurations for the board and its
           peripherals.
 
-config MACH_IMX27LITE
-        bool "LogicPD MX27 LITEKIT platform"
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX27
-        help
-          Include support for MX27 LITEKIT platform. This includes specific
-          configurations for the board and its peripherals.
-
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -405,15 +372,6 @@ config MACH_MXT_TD60
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
 
-config MACH_IMX27IPCAM
-        bool "IMX27 IPCAM platform"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX27
-        help
-          Include support for IMX27 IPCAM platform. This includes specific
-          configurations for the board and its peripherals.
-
 config MACH_IMX27_DT
         bool "Support i.MX27 platforms from device tree"
         select SOC_IMX27
@@ -699,24 +657,29 @@ if ARCH_MULTI_V7
 
 comment "Device tree only"
 
+config SOC_IMX5
+        bool
+        select ARCH_HAS_OPP
+        select HAVE_IMX_SRC
+        select MXC_TZIC
+
 config  SOC_IMX50
         bool "i.MX50 support"
-        select HAVE_IMX_SRC
         select PINCTRL_IMX50
         select SOC_IMX5
 
         help
           This enables support for Freescale i.MX50 processor.
 
-config MACH_IMX51_DT
+config SOC_IMX51
         bool "i.MX51 support"
-        select SOC_IMX51
+        select PINCTRL_IMX51
+        select SOC_IMX5
         help
           This enables support for Freescale i.MX51 processor
 
 config  SOC_IMX53
         bool "i.MX53 support"
-        select HAVE_IMX_SRC
         select PINCTRL_IMX53
         select SOC_IMX5
 
@@ -733,8 +696,6 @@ config SOC_IMX6
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select MFD_SYSCON
-        select PL310_ERRATA_588369 if CACHE_L2X0
-        select PL310_ERRATA_727915 if CACHE_L2X0
         select PL310_ERRATA_769419 if CACHE_L2X0
 
 config SOC_IMX6Q
@@ -770,8 +731,6 @@ config SOC_VF610
         select ARM_GIC
         select PINCTRL_VF610
         select VF_PIT_TIMER
-        select PL310_ERRATA_588369 if CACHE_L2X0
-        select PL310_ERRATA_727915 if CACHE_L2X0
         select PL310_ERRATA_769419 if CACHE_L2X0
 
         help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bbe93bbfd003..ac88599ca080 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o \
@@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
+# i.MX6SX reuses i.MX6Q cpuidle driver
+obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
 endif
 
 ifdef CONFIG_SND_IMX_SOC
@@ -38,9 +40,6 @@ obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
 
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
-
 # i.MX1 based machines
 obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
 obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
@@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
-obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
 obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
 obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
-obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
 obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
@@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
 endif
 obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
 
-obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
+obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 7f739be3de2c..37c307a8d896 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -15,100 +15,103 @@
  * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx1-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-/* CCM register addresses */
-#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-#define CCM_CSCR        IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
-#define CCM_PCDR        IO_ADDR_CCM(0x20)
-
-/* SCM register addresses */
-#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-#define SCM_GCCR        IO_ADDR_SCM(0xc)
-
 static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
                                        "prem", "fclk", };
 
-enum imx1_clks {
-        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
-        spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
-        uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
-        usbd_gate, clk_max
-};
+static struct clk *clk[IMX1_CLK_MAX];
+static struct clk_onecell_data clk_data;
 
-static struct clk *clk[clk_max];
+static void __iomem *ccm __initdata;
+#define CCM_CSCR        (ccm + 0x0000)
+#define CCM_MPCTL0      (ccm + 0x0004)
+#define CCM_SPCTL0      (ccm + 0x000c)
+#define CCM_PCDR        (ccm + 0x0020)
+#define SCM_GCCR        (ccm + 0x0810)
 
-int __init mx1_clocks_init(unsigned long fref)
+static void __init _mx1_clocks_init(unsigned long fref)
 {
-        int i;
+        clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
+        clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
+        clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
+        clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+        clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
+        clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+        clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
+        clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+        clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
+        clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
+        clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
+        clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
+        clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
+        clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
+        clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
+        clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+        clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
+        clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
+        clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
+        clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
+        clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
+        clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
+        clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+}
 
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[clk32] = imx_clk_fixed("clk32", fref);
-        clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
-        clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
-        clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
-        clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
-                        ARRAY_SIZE(prem_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
-        clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
-        clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
-        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
-        clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
-        clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
-        clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
-        clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
-        clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
-        clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
-        clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
-        clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
-                        ARRAY_SIZE(clko_sel_clks));
-        clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
-        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
-        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
-        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
-        clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
-        clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
-        clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+int __init mx1_clocks_init(unsigned long fref)
+{
+        ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx1 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        _mx1_clocks_init(fref);
 
-        clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
-        clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
-        clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
+        clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
 
         mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
 
         return 0;
 }
+
+static void __init mx1_clocks_init_dt(struct device_node *np)
+{
+        ccm = of_iomap(np, 0);
+        BUG_ON(!ccm);
+
+        _mx1_clocks_init(32768);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index bdc2e4630a08..4b4c75339aa6 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -7,178 +7,165 @@
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
  */
 
 #include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/err.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx21-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+static void __iomem *ccm __initdata;
 
 /* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-static const char *mpll_sel_clks[] = { "fpm", "ckih", };
-static const char *spll_sel_clks[] = { "fpm", "ckih", };
-
-enum imx21_clks {
-        ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
-        per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
-        uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
-        pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
-        lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
-        per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
-        ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
-        emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
-        gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
+#define CCM_CSCR        (ccm + 0x00)
+#define CCM_MPCTL0      (ccm + 0x04)
+#define CCM_SPCTL0      (ccm + 0x0c)
+#define CCM_PCDR0       (ccm + 0x18)
+#define CCM_PCDR1       (ccm + 0x1c)
+#define CCM_PCCR0       (ccm + 0x20)
+#define CCM_PCCR1       (ccm + 0x24)
+
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
+static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
+
+static struct clk *clk[IMX21_CLK_MAX];
+static struct clk_onecell_data clk_data;
+
+static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+        BUG_ON(!ccm);
+
+        clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
+        clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
+        clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+        clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+
+        clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
+        clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
+        clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
+        clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+        clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+        clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+        clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
+        clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
+        clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
+
+        clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+
+        clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
+
+        clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
+        clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+        clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
+
+        clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
+        clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
+        clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
+        clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
+
+        clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
+        clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
+        clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+        clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+        clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+        clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
+        clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
+        clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
+        clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
+        clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
+        clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+        clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+        clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+        clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
+        clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+        clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
+        clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+        clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+        clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+        clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+        clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+
+        clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
+        clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
+        clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
+        clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
+        clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+}
 
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
-        int i;
-
-        clk[ckil] = imx_clk_fixed("ckil", lref);
-        clk[ckih] = imx_clk_fixed("ckih", href);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
-                        ARRAY_SIZE(spll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
-        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
-        clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
-        clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
-        clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
-        clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
-        clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
-        clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
-        clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
-        clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
-        clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
-        clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
-        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
-        clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
-        clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
-        clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
-        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
-        clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
-        clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
-        clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
-        clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
-        clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
-        clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
-        clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
-        clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
-        clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
-        clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX21 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[per1], "per1", NULL);
-        clk_register_clkdev(clk[per2], "per2", NULL);
-        clk_register_clkdev(clk[per3], "per3", NULL);
-        clk_register_clkdev(clk[per4], "per4", NULL);
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
-        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
-        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
-        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
-        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
-        clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
-        clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-        clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
-        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
-        clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
-        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
-        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[brom_gate], "brom", NULL);
-        clk_register_clkdev(clk[emma_gate], "emma", NULL);
-        clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
-        clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
-        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
-        clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
-        clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
-        clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
+        ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
+
+        _mx21_clocks_init(lref, href);
+
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
+        clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
+        clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
+        clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
+        clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
+        clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
+        clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
+        clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
 
         mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
 
         return 0;
 }
+
+static void __init mx21_clocks_init_dt(struct device_node *np)
+{
+        ccm = of_iomap(np, 0);
+
+        _mx21_clocks_init(32768, 26000000);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index ae578c096ad8..59c0c8558c6b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -32,8 +32,6 @@
 #include "hardware.h"
 #include "mx25.h"
 
-#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
-
 #define CCM_MPCTL       0x00
 #define CCM_UPCTL       0x04
 #define CCM_CCTL        0x08
@@ -56,7 +54,7 @@
 #define CCM_LTR3        0x4c
 #define CCM_MCR         0x64
 
-#define ccm(x)  (CRM_BASE + (x))
+#define ccm(x)  (ccm_base + (x))
 
 static struct clk_onecell_data clk_data;
 
@@ -91,9 +89,10 @@ enum mx25_clks {
 
 static struct clk *clk[clk_max];
 
-static int __init __mx25_clocks_init(unsigned long osc_rate)
+static int __init __mx25_clocks_init(unsigned long osc_rate,
+                                     void __iomem *ccm_base)
 {
-        int i;
+        BUG_ON(!ccm_base);
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
         clk[osc] = imx_clk_fixed("osc", osc_rate);
@@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
         /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
         clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX25 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_prepare_enable(clk[emi_ahb]);
 
         /* Clock source for gpt must be derived from AHB */
         clk_set_parent(clk[per5_sel], clk[ahb]);
 
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-
         /*
          * Let's initially set up CLKO parent as ipg, since this configuration
          * is used on some imx25 board designs to clock the audio codec.
@@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
 
 int __init mx25_clocks_init(void)
 {
-        __mx25_clocks_init(24000000);
+        void __iomem *ccm;
 
+        ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
+
+        __mx25_clocks_init(24000000, ccm);
+
+        clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         /* i.mx25 has the i.mx21 type uart */
         clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
         clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@@ -314,29 +313,27 @@ int __init mx25_clocks_init(void)
         return 0;
 }
 
-int __init mx25_clocks_init_dt(void)
+static void __init mx25_clocks_init_dt(struct device_node *np)
 {
-        struct device_node *np;
+        struct device_node *refnp;
         unsigned long osc_rate = 24000000;
+        void __iomem *ccm;
 
         /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
+        for_each_compatible_node(refnp, NULL, "fixed-clock") {
                 u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
+                if (of_property_read_u32(refnp, "clock-frequency", &rate))
                         continue;
 
-                if (of_device_is_compatible(np, "fsl,imx-osc"))
+                if (of_device_is_compatible(refnp, "fsl,imx-osc"))
                         osc_rate = rate;
         }
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
+        ccm = of_iomap(np, 0);
+        __mx25_clocks_init(osc_rate, ccm);
+
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        __mx25_clocks_init(osc_rate);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
-
-        return 0;
 }
+CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 317a662626d6..ab6349ec23b9 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -1,61 +1,36 @@
 #include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx27-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+static void __iomem *ccm __initdata;
 
 /* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS     (1 << 31)
-#define CCM_CSCR_SSI2           (1 << 23)
-#define CCM_CSCR_SSI1           (1 << 22)
-#define CCM_CSCR_VPU            (1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
+#define CCM_CSCR                (ccm + 0x00)
+#define CCM_MPCTL0              (ccm + 0x04)
+#define CCM_MPCTL1              (ccm + 0x08)
+#define CCM_SPCTL0              (ccm + 0x0c)
+#define CCM_SPCTL1              (ccm + 0x10)
+#define CCM_PCDR0               (ccm + 0x18)
+#define CCM_PCDR1               (ccm + 0x1c)
+#define CCM_PCCR0               (ccm + 0x20)
+#define CCM_PCCR1               (ccm + 0x24)
+#define CCM_CCSR                (ccm + 0x28)
 
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
 static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
-static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
 static const char *clko_sel_clks[] = {
-        "ckil", "fpm", "ckih", "ckih",
-        "ckih", "mpll", "spll", "cpu_div",
+        "ckil", "fpm", "ckih_gate", "ckih_gate",
+        "ckih_gate", "mpll", "spll", "cpu_div",
         "ahb", "ipg", "per1_div", "per2_div",
         "per3_div", "per4_div", "ssi1_div", "ssi2_div",
         "nfc_div", "mshc_div", "vpu_div", "60m",
@@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
 
 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
 
-enum mx27_clks {
-        dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
-        per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
-        clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
-        clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
-        sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
-        rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
-        kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
-        gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
-        gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
-        emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
-        cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
-        vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
-        usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
-        vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
-        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
-        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
-        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-        mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
-        rtic_ahb_gate, mshc_baud_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
+static struct clk *clk[IMX27_CLK_MAX];
 static struct clk_onecell_data clk_data;
 
-int __init mx27_clocks_init(unsigned long fref)
+static void __init _mx27_clocks_init(unsigned long fref)
 {
-        int i;
-        struct device_node *np;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckih] = imx_clk_fixed("ckih", fref);
-        clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
-        clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+        BUG_ON(!ccm);
 
-        clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
-                        mpll_osc_sel_clks,
-                        ARRAY_SIZE(mpll_osc_sel_clks));
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
-        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
-        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+        clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
+        clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
+        clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
+        clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+        clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
+        clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+        clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+        clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
+        clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
 
         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
-                clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+                clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+                clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
         } else {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
-                clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
+                clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
+                clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
         }
 
-        clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
-        clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
-        clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
-        clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
-        clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
-        clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
-        clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
-        clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
-        clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+        clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
+        clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+        clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+        clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+        clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+        clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+        clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+        clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
+        clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
+        clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+        clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+
         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+                clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
         else
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
-        clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
-        clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
-        clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
-        clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
-        clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
-        clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
-        clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
-        clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
-        clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
-        clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
-        clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
-        clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
-        clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
-        clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
-        clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
-        clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
-        clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
-        clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
-        clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
-        clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
-        clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
-        clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
-        clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
-        clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
-        clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
-        clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
-        clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
-        clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
-        clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
-        clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
-        clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
-        clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
-        clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
-        clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
-        clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
-        clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
-        clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
-        clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
-        clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
-        clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
-        clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
-        clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
-        clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+                clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX27 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
+        clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+        clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
+        clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
+        clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+        clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+        clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
+        clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+        clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+        clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
+        clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+        clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+        clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+        clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+        clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+        clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+        clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+        clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+        clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+        clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+        clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+        clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+        clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+        clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+        clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+        clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+        clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+        clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
+        clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+        clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
+        clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
+        clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+        clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+        clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+        clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+        clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+        clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+        clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+        clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+        clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
+        clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+        clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+        clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+        clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+        clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+        clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+        clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+        clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+        clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+        clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+        clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+        clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+        clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
-        if (np) {
-                clk_data.clks = clk;
-                clk_data.clk_num = ARRAY_SIZE(clk);
-                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-        }
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
-        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
-        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
-        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
-        clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
-        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
-        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
-        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
-        clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
-        clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
+        clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
 
-        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
-
-        clk_prepare_enable(clk[emi_ahb_gate]);
+        clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
 
         imx_print_silicon_rev("i.MX27", mx27_revision());
+}
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+        ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
+
+        _mx27_clocks_init(fref);
+
+        clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
+        clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
+        clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
+        clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
+        clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
+        clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
+        clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
+        clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
+        clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
+        clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
+        clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
+        clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
+
+        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
 
         return 0;
 }
 
-int __init mx27_clocks_init_dt(void)
+static void __init mx27_clocks_init_dt(struct device_node *np)
 {
-        struct device_node *np;
+        struct device_node *refnp;
         u32 fref = 26000000; /* default */
 
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+        for_each_compatible_node(refnp, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
                         continue;
 
-                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                if (!of_property_read_u32(refnp, "clock-frequency", &fref))
                         break;
         }
 
-        return mx27_clocks_init(fref);
+        ccm = of_iomap(np, 0);
+
+        _mx27_clocks_init(fref);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 }
+CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 4a9de0835eb1..286ef422cebc 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
 int __init mx31_clocks_init(unsigned long fref)
 {
         void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
-        int i;
         struct device_node *np;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
         clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
         clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx31 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
 
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 71c86a2f856d..a0d2b57fd376 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
         u32 pdr0, consumer_sel, hsp_sel;
         struct arm_ahb_div *aad;
         unsigned char *hsp_div;
-        u32 i;
 
         pdr0 = __raw_readl(base + MXC_CCM_PDR0);
         consumer_sel = (pdr0 >> 16) & 0xf;
@@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
         clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX35 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
         clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 21d2b111c83d..72d65214223e 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -18,11 +18,54 @@
 #include <linux/of_irq.h>
 #include <dt-bindings/clock/imx5-clock.h>
 
-#include "crm-regs-imx5.h"
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
+#define MX51_DPLL1_BASE         0x83f80000
+#define MX51_DPLL2_BASE         0x83f84000
+#define MX51_DPLL3_BASE         0x83f88000
+
+#define MX53_DPLL1_BASE         0x63f80000
+#define MX53_DPLL2_BASE         0x63f84000
+#define MX53_DPLL3_BASE         0x63f88000
+#define MX53_DPLL4_BASE         0x63f8c000
+
+#define MXC_CCM_CCR             (ccm_base + 0x00)
+#define MXC_CCM_CCDR            (ccm_base + 0x04)
+#define MXC_CCM_CSR             (ccm_base + 0x08)
+#define MXC_CCM_CCSR            (ccm_base + 0x0c)
+#define MXC_CCM_CACRR           (ccm_base + 0x10)
+#define MXC_CCM_CBCDR           (ccm_base + 0x14)
+#define MXC_CCM_CBCMR           (ccm_base + 0x18)
+#define MXC_CCM_CSCMR1          (ccm_base + 0x1c)
+#define MXC_CCM_CSCMR2          (ccm_base + 0x20)
+#define MXC_CCM_CSCDR1          (ccm_base + 0x24)
+#define MXC_CCM_CS1CDR          (ccm_base + 0x28)
+#define MXC_CCM_CS2CDR          (ccm_base + 0x2c)
+#define MXC_CCM_CDCDR           (ccm_base + 0x30)
+#define MXC_CCM_CHSCDR          (ccm_base + 0x34)
+#define MXC_CCM_CSCDR2          (ccm_base + 0x38)
+#define MXC_CCM_CSCDR3          (ccm_base + 0x3c)
+#define MXC_CCM_CSCDR4          (ccm_base + 0x40)
+#define MXC_CCM_CWDR            (ccm_base + 0x44)
+#define MXC_CCM_CDHIPR          (ccm_base + 0x48)
+#define MXC_CCM_CDCR            (ccm_base + 0x4c)
+#define MXC_CCM_CTOR            (ccm_base + 0x50)
+#define MXC_CCM_CLPCR           (ccm_base + 0x54)
+#define MXC_CCM_CISR            (ccm_base + 0x58)
+#define MXC_CCM_CIMR            (ccm_base + 0x5c)
+#define MXC_CCM_CCOSR           (ccm_base + 0x60)
+#define MXC_CCM_CGPR            (ccm_base + 0x64)
+#define MXC_CCM_CCGR0           (ccm_base + 0x68)
+#define MXC_CCM_CCGR1           (ccm_base + 0x6c)
+#define MXC_CCM_CCGR2           (ccm_base + 0x70)
+#define MXC_CCM_CCGR3           (ccm_base + 0x74)
+#define MXC_CCM_CCGR4           (ccm_base + 0x78)
+#define MXC_CCM_CCGR5           (ccm_base + 0x7c)
+#define MXC_CCM_CCGR6           (ccm_base + 0x80)
+#define MXC_CCM_CCGR7           (ccm_base + 0x84)
+
 /* Low-power Audio Playback Mode clock */
 static const char *lp_apm_sel[] = { "osc", };
 
@@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static void __init mx5_clocks_common_init(unsigned long rate_ckil,
-                unsigned long rate_osc, unsigned long rate_ckih1,
-                unsigned long rate_ckih2)
+static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 {
-        int i;
+        imx5_pm_set_ccm_base(ccm_base);
 
         clk[IMX5_CLK_DUMMY]             = imx_clk_fixed("dummy", 0);
-        clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", rate_ckil);
-        clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", rate_osc);
-        clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", rate_ckih1);
-        clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", rate_ckih2);
+        clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", 0);
+        clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", 0);
+        clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", 0);
+        clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", 0);
 
         clk[IMX5_CLK_PERIPH_APM]        = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
                                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
@@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[IMX5_CLK_SAHARA_IPG_GATE]   = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
         clk[IMX5_CLK_SATA_REF]          = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX5 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
-        clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
         clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
-        clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
-        clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
         clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
@@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 
 static void __init mx50_clocks_init(struct device_node *np)
 {
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         unsigned long r;
-        int i;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+        pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
 
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
         clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
         clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX50 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(0, 0, 0, 0);
-
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
 }
 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
 
-int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
-                        unsigned long rate_ckih1, unsigned long rate_ckih2)
+static void __init mx51_clocks_init(struct device_node *np)
 {
-        int i;
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         u32 val;
-        struct device_node *np;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
+        pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
+
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
         clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                                 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
         clk[IMX5_CLK_SPDIF1_GATE]       = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX51 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
-
-        clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
-
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
 
@@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
 
-        /* System timer */
-        mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
-
         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
         imx_print_silicon_rev("i.MX51", mx51_revision());
         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
@@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         val = readl(MXC_CCM_CLPCR);
         val |= 1 << 23;
         writel(val, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-static void __init mx51_clocks_init_dt(struct device_node *np)
-{
-        mx51_clocks_init(0, 0, 0, 0);
 }
-CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
+CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
 
 static void __init mx53_clocks_init(struct device_node *np)
 {
-        int i;
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         unsigned long r;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
-        clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
+        pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
 
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
         clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
                                                 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX53 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(0, 0, 0, 0);
-
-        clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
-
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8556c787e59c..6cceb7765c14 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -19,6 +19,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
 
 #include "clk.h"
 #include "common.h"
@@ -73,48 +74,13 @@ static const char *lvds_sels[] = {
         "pcie_ref_125m", "sata_ref_100m",
 };
 
-enum mx6q_clks {
-        dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
-        pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
-        pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
-        periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
-        esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
-        gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
-        ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
-        ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
-        ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
-        usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
-        emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
-        periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
-        asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
-        gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
-        ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
-        ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
-        ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
-        usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
-        emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
-        mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
-        can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
-        esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
-        hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
-        ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
-        gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
-        ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
-        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
-        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
-        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
-        lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
-};
-
-static struct clk *clk[clk_max];
+static struct clk *clk[IMX6QDL_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static enum mx6q_clks const clks_init_on[] __initconst = {
-        mmdc_ch0_axi, rom, arm,
+static unsigned int const clks_init_on[] __initconst = {
+        IMX6QDL_CLK_MMDC_CH0_AXI,
+        IMX6QDL_CLK_ROM,
+        IMX6QDL_CLK_ARM,
 };
 
 static struct clk_div_table clk_enet_ref_table[] = {
@@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         int i;
         int ret;
 
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
-        clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
-        clk[osc] = imx_obtain_fixed_clock("osc", 0);
+        clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+        clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
+        clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         base = of_iomap(np, 0);
@@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 video_div_table[2].div = 1;
         };
 
-        /*                   type                               name         parent_name  base     div_mask */
-        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
-        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
-        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
-        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
-        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
-        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
-        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
+        /*                                             type             name         parent_name  base     div_mask */
+        clk[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,   "pll1_sys",     "osc", base,        0x7f);
+        clk[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,       "pll2_bus",     "osc", base + 0x30, 0x1);
+        clk[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,   "pll3_usb_otg", "osc", base + 0x10, 0x3);
+        clk[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll4_audio",   "osc", base + 0x70, 0x7f);
+        clk[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll5_video",   "osc", base + 0xa0, 0x7f);
+        clk[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,  "pll6_enet",    "osc", base + 0xe0, 0x3);
+        clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,   "pll7_usb_host","osc", base + 0x20, 0x3);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          * - Keep refcount when do usbphy clk_enable/disable, in that case,
          * the clk framework may need to enable/disable usbphy's parent
          */
-        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
-        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
+        clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
+        clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
 
         /*
          * usbphy*_gate needs to be on after system boots up, and software
          * never needs to control it anymore.
          */
-        clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
-        clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
+        clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
+        clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
 
-        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
-        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+        clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+        clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 
-        clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
-        clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+        clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+        clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
-        clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+        clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
                         &imx_ccm_lock);
 
-        clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
-        clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
 
         /*
          * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
@@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          * the "output_enable" bit as a gate, even though it's really just
          * enabling clock output.
          */
-        clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
-        clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
-
-        /*                                name              parent_name        reg       idx */
-        clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
-        clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
-        clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
-        clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
-        clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
-        clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
-        clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
-
-        /*                                    name         parent_name     mult div */
-        clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
-        clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
-        clk[pll3_80m]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
-        clk[pll3_60m]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
-        clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
-
-        clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
-        clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
-        clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
-        clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
+        clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
+
+        /*                                            name              parent_name        reg       idx */
+        clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+        clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
+        clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
+        clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
+        clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
+        clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
+        clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
+
+        /*                                                name         parent_name     mult div */
+        clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+        clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+        clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+
+        clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
         np = ccm_node;
         base = of_iomap(np, 0);
@@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         imx6q_pm_set_ccm_base(base);
 
-        /*                                  name                reg       shift width parent_names     num_parents */
-        clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
-        clk[pll1_sw]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
-        clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-        clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
-        clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
-        clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[spdif_sel]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[gpu2d_axi]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu3d_axi]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu2d_core_sel]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
-        clk[gpu3d_core_sel]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
-        clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
-        clk[ipu1_sel]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ipu2_sel]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ldb_di0_sel]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-        clk[ldb_di1_sel]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di0_sel]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di1_sel]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di0_sel]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di1_sel]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
-        clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
-        clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
-        clk[ssi1_sel]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[ssi2_sel]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[ssi3_sel]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[usdhc1_sel]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc2_sel]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc3_sel]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc4_sel]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
-        clk[emi_sel]          = imx_clk_fixup_mux("emi_sel",      base + 0x1c, 27, 2, emi_sels,        ARRAY_SIZE(emi_sels),          imx_cscmr1_fixup);
-        clk[emi_slow_sel]     = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels,   ARRAY_SIZE(emi_slow_sels),     imx_cscmr1_fixup);
-        clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
-        clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
-        clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
-        clk[cko2_sel]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
-        clk[cko]              = imx_clk_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
-
-        /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
-        clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
-        clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
-
-        /*                                      name                parent_name          reg       shift width */
-        clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
-        clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
-        clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
-        clk[ipg_per]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
-        clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
-        clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
-        clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
-        clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
-        clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
-        clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
-        clk[can_root]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
-        clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
-        clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
-        clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
-        clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
-        clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
-        clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-        clk[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
-        clk[ldb_di0_podf]     = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
-        clk[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
-        clk[ldb_di1_podf]     = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
-        clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
-        clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
-        clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
-        clk[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
-        clk[hsi_tx_podf]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
-        clk[ssi1_pred]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
-        clk[ssi1_podf]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
-        clk[ssi2_pred]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
-        clk[ssi2_podf]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
-        clk[ssi3_pred]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
-        clk[ssi3_podf]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
-        clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
-        clk[usdhc1_podf]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
-        clk[usdhc2_podf]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
-        clk[usdhc3_podf]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
-        clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
-        clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
-        clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
-        clk[emi_podf]         = imx_clk_fixup_divider("emi_podf",   "emi_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
-        clk[emi_slow_podf]    = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
-        clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
-        clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
-        clk[cko2_podf]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
-
-        /*                                            name                 parent_name    reg        shift width busy: reg, shift */
-        clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
-        clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
-        clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
-        clk[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
-        clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
-
-        /*                                name             parent_name          reg         shift */
-        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
-        clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
-        clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
-        clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
-        clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
-        clk[can2_serial]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
-        clk[ecspi1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
-        clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
-        clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
-        clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
+        /*                                              name                reg       shift width parent_names     num_parents */
+        clk[IMX6QDL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clk[IMX6QDL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clk[IMX6QDL_CLK_PERIPH_PRE]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[IMX6QDL_CLK_PERIPH2_PRE]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[IMX6QDL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clk[IMX6QDL_CLK_AXI_SEL]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
+        clk[IMX6QDL_CLK_ESAI_SEL]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_ASRC_SEL]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_SPDIF_SEL]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[IMX6QDL_CLK_GPU2D_CORE_SEL]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+        clk[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
+        clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+        clk[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_HSI_TX_SEL]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
+        clk[IMX6QDL_CLK_PCIE_AXI_SEL]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
+        clk[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+        clk[IMX6QDL_CLK_EMI_SEL]          = imx_clk_fixup_mux("emi_sel",      base + 0x1c, 27, 2, emi_sels,        ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_EMI_SLOW_SEL]     = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels,   ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
+        clk[IMX6QDL_CLK_VPU_AXI_SEL]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
+        clk[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
+        clk[IMX6QDL_CLK_CKO2_SEL]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
+        clk[IMX6QDL_CLK_CKO]              = imx_clk_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
+
+        /*                                          name         reg      shift width busy: reg, shift parent_names  num_parents */
+        clk[IMX6QDL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+        /*                                                  name                parent_name          reg       shift width */
+        clk[IMX6QDL_CLK_PERIPH_CLK2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
+        clk[IMX6QDL_CLK_PERIPH2_CLK2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clk[IMX6QDL_CLK_IPG]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
+        clk[IMX6QDL_CLK_IPG_PER]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_ESAI_PRED]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
+        clk[IMX6QDL_CLK_ESAI_PODF]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
+        clk[IMX6QDL_CLK_ASRC_PRED]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
+        clk[IMX6QDL_CLK_ASRC_PODF]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
+        clk[IMX6QDL_CLK_SPDIF_PRED]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
+        clk[IMX6QDL_CLK_SPDIF_PODF]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
+        clk[IMX6QDL_CLK_CAN_ROOT]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
+        clk[IMX6QDL_CLK_ECSPI_ROOT]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+        clk[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
+        clk[IMX6QDL_CLK_GPU3D_CORE_PODF]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
+        clk[IMX6QDL_CLK_GPU3D_SHADER]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
+        clk[IMX6QDL_CLK_IPU1_PODF]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
+        clk[IMX6QDL_CLK_IPU2_PODF]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
+        clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clk[IMX6QDL_CLK_LDB_DI0_PODF]     = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
+        clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clk[IMX6QDL_CLK_LDB_DI1_PODF]     = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
+        clk[IMX6QDL_CLK_IPU1_DI0_PRE]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
+        clk[IMX6QDL_CLK_IPU1_DI1_PRE]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
+        clk[IMX6QDL_CLK_IPU2_DI0_PRE]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
+        clk[IMX6QDL_CLK_IPU2_DI1_PRE]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
+        clk[IMX6QDL_CLK_HSI_TX_PODF]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
+        clk[IMX6QDL_CLK_SSI1_PRED]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
+        clk[IMX6QDL_CLK_SSI1_PODF]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
+        clk[IMX6QDL_CLK_SSI2_PRED]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
+        clk[IMX6QDL_CLK_SSI2_PODF]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
+        clk[IMX6QDL_CLK_SSI3_PRED]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
+        clk[IMX6QDL_CLK_SSI3_PODF]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
+        clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
+        clk[IMX6QDL_CLK_USDHC1_PODF]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
+        clk[IMX6QDL_CLK_USDHC2_PODF]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
+        clk[IMX6QDL_CLK_USDHC3_PODF]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
+        clk[IMX6QDL_CLK_USDHC4_PODF]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
+        clk[IMX6QDL_CLK_ENFC_PRED]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
+        clk[IMX6QDL_CLK_ENFC_PODF]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
+        clk[IMX6QDL_CLK_EMI_PODF]         = imx_clk_fixup_divider("emi_podf",   "emi_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_EMI_SLOW_PODF]    = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_VPU_AXI_PODF]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
+        clk[IMX6QDL_CLK_CKO1_PODF]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
+        clk[IMX6QDL_CLK_CKO2_PODF]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
+
+        /*                                                        name                 parent_name    reg        shift width busy: reg, shift */
+        clk[IMX6QDL_CLK_AXI]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
+        clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
+        clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+        clk[IMX6QDL_CLK_ARM]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
+        clk[IMX6QDL_CLK_AHB]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
+
+        /*                                            name             parent_name          reg         shift */
+        clk[IMX6QDL_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
+        clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+        clk[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
+        clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
+        clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
+        clk[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
+        clk[IMX6QDL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
+        clk[IMX6QDL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
+        clk[IMX6QDL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
+        clk[IMX6QDL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
         if (cpu_is_imx6dl())
-                /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
-                clk[ecspi5] = imx_clk_gate2("i2c4",        "ipg_per",           base + 0x6c, 8);
+                clk[IMX6DL_CLK_I2C4]  = imx_clk_gate2("i2c4",          "ipg_per",           base + 0x6c, 8);
         else
-                clk[ecspi5] = imx_clk_gate2("ecspi5",      "ecspi_root",        base + 0x6c, 8);
-        clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
-        clk[esai]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
-        clk[esai_ahb]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
-        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
-        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
+                clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
+        clk[IMX6QDL_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
+        clk[IMX6QDL_CLK_ESAI]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_ESAI_AHB]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_GPT_IPG]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
+        clk[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
         if (cpu_is_imx6dl())
                 /*
                  * The multiplexer and divider of imx6q clock gpu3d_shader get
                  * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
                  */
-                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+                clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
         else
-                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
-        clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
-        clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
-        clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
-        clk[i2c1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
-        clk[i2c2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
-        clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
-        clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
-        clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
-        clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
-        clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
-        clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
-        clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
-        clk[ipu2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
-        clk[ipu2_di0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
-        clk[ldb_di0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
-        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
-        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
-        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+                clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+        clk[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
+        clk[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
+        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+        clk[IMX6QDL_CLK_I2C1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
+        clk[IMX6QDL_CLK_I2C2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
+        clk[IMX6QDL_CLK_I2C3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
+        clk[IMX6QDL_CLK_IIM]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
+        clk[IMX6QDL_CLK_ENFC]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+        clk[IMX6QDL_CLK_VDOA]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
+        clk[IMX6QDL_CLK_IPU1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
+        clk[IMX6QDL_CLK_IPU1_DI0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
+        clk[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
+        clk[IMX6QDL_CLK_IPU2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
+        clk[IMX6QDL_CLK_IPU2_DI0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
+        clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
+        clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+        clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
+        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
         if (cpu_is_imx6dl())
                 /*
                  * The multiplexer and divider of the imx6q clock gpu2d get
                  * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
                  */
-                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+                clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
         else
-                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
-        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
-        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
-        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
-        clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
-        clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
-        clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
-        clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
-        clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
-        clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
-        clk[pwm4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
-        clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
-        clk[gpmi_bch]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
-        clk[gpmi_io]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
-        clk[gpmi_apb]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
-        clk[rom]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
-        clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
-        clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
-        clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-        clk[spdif]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
-        clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
-        clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
-        clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
-        clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
-        clk[usdhc1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
-        clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
-        clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
-        clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
-        clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
-        clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
-        clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
-        clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
-        clk[cko2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX6q clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+                clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
+        clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
+        clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+        clk[IMX6QDL_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
+        clk[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
+        clk[IMX6QDL_CLK_PCIE_AXI]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+        clk[IMX6QDL_CLK_PER1_BCH]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
+        clk[IMX6QDL_CLK_PWM1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
+        clk[IMX6QDL_CLK_PWM2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
+        clk[IMX6QDL_CLK_PWM3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
+        clk[IMX6QDL_CLK_PWM4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
+        clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
+        clk[IMX6QDL_CLK_GPMI_BCH]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
+        clk[IMX6QDL_CLK_GPMI_IO]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
+        clk[IMX6QDL_CLK_GPMI_APB]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
+        clk[IMX6QDL_CLK_ROM]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
+        clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
+        clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
+        clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+        clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+        clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
+        clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
+        clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
+        clk[IMX6QDL_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
+        clk[IMX6QDL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
+        clk[IMX6QDL_CLK_USBOH3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
+        clk[IMX6QDL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
+        clk[IMX6QDL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
+        clk[IMX6QDL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
+        clk[IMX6QDL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[IMX6QDL_CLK_EIM_SLOW]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
+        clk[IMX6QDL_CLK_VDO_AXI]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
+        clk[IMX6QDL_CLK_VPU_AXI]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
+        clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+        clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
+        clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
 
         if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
             cpu_is_imx6dl()) {
-                clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
-                clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
         }
 
-        clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
-        clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
-        clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
-        clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
 
         /*
          * The gpmi needs 100MHz frequency in the EDO/Sync mode,
          * We can not get the 100MHz from the pll2_pfd0_352m.
          * So choose pll2_pfd2_396m as enfc_sel's parent.
          */
-        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+        clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clk[clks_init_on[i]]);
 
         if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-                clk_prepare_enable(clk[usbphy1_gate]);
-                clk_prepare_enable(clk[usbphy2_gate]);
+                clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
         }
 
         /*
          * Let's initially set up CLKO with OSC24M, since this configuration
          * is widely used by imx6q board designs to clock audio codec.
          */
-        ret = clk_set_parent(clk[cko2_sel], clk[osc]);
+        ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
         if (!ret)
-                ret = clk_set_parent(clk[cko], clk[cko2]);
+                ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
         if (ret)
                 pr_warn("failed to set up CLKO: %d\n", ret);
 
         /* Audio-related clocks configuration */
-        clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+        clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
 
         /* All existing boards with PCIe use LVDS1 */
         if (IS_ENABLED(CONFIG_PCI_IMX6))
-                clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);
+                clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
 }
 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 5408ca70c8d6..fef46faf692f 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -348,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
         clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
 
-        for (i = 0; i < ARRAY_SIZE(clks); i++)
-                if (IS_ERR(clks[i]))
-                        pr_err("i.MX6SL clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clks[i]));
+        imx_check_clocks(clks, ARRAY_SIZE(clks));
 
         clk_data.clks = clks;
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
         /* Ensure the AHB clk is at 132MHz. */
         ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
         if (ret)
@@ -383,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
-        mxc_timer_init_dt(np);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 72f8902235d1..ecde72bdfe88 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = {
 static u32 share_count_asrc;
 static u32 share_count_audio;
 static u32 share_count_esai;
+static u32 share_count_ssi1;
+static u32 share_count_ssi2;
+static u32 share_count_ssi3;
 
 static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 {
@@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
         clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
         clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
-        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
-        clks[IMX6SX_CLK_SSI1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
-        clks[IMX6SX_CLK_SSI2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
-        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
+        clks[IMX6SX_CLK_SSI1]         = imx_clk_gate2_shared("ssi1",          "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SX_CLK_SSI2]         = imx_clk_gate2_shared("ssi2",          "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2_shared("ssi3",          "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
         clks[IMX6SX_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
         clks[IMX6SX_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_podf",         base + 0x7c, 26);
         clks[IMX6SX_CLK_SAI1_IPG]     = imx_clk_gate2("sai1_ipg",      "ipg",               base + 0x7c, 28);
@@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         /* mask handshake of mmdc */
         writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
 
-        for (i = 0; i < ARRAY_SIZE(clks); i++)
-                if (IS_ERR(clks[i]))
-                        pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
+        imx_check_clocks(clks, ARRAY_SIZE(clks));
 
         clk_data.clks = clks;
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
 
@@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
-        mxc_timer_init_dt(np);
 }
 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index 22dc3ee21fd4..f60d6d569ce3 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -295,14 +295,18 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 
         clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
 
-        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
-        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11);
+        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);
+        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));
 
         clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
         clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
         clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
         clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
 
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+
         clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
         clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
         clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index edc35df7bed4..df12b5307175 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -7,6 +7,16 @@
 
 DEFINE_SPINLOCK(imx_ccm_lock);
 
+void __init imx_check_clocks(struct clk *clks[], unsigned int count)
+{
+        unsigned i;
+
+        for (i = 0; i < count; i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX clk %u: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+}
+
 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
 {
         struct of_phandle_args phandle;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index e29f6ebe9f39..d5ba76fee115 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -6,6 +6,8 @@
 
 extern spinlock_t imx_ccm_lock;
 
+void imx_check_clocks(struct clk *clks[], unsigned int count);
+
 extern void imx_cscmr1_fixup(u32 *val);
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
@@ -95,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
                         shift, 0, &imx_ccm_lock);
 }
 
+static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
+                void __iomem *reg, u8 shift)
+{
+        return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                        shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
                 u8 shift, u8 width, const char **parents, int num_parents)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 9ab785ce13e8..22ba8973bcb9 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -19,6 +19,7 @@ struct pt_regs;
 struct clk;
 struct device_node;
 enum mxc_cpu_pwr_mode;
+struct of_device_id;
 
 void mx1_map_io(void);
 void mx21_map_io(void);
@@ -26,48 +27,34 @@ void mx25_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
-void mx51_map_io(void);
-void mx53_map_io(void);
 void imx1_init_early(void);
 void imx21_init_early(void);
 void imx25_init_early(void);
 void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
-void imx51_init_early(void);
-void imx53_init_early(void);
 void mxc_init_irq(void __iomem *);
-void tzic_init_irq(void __iomem *);
+void tzic_init_irq(void);
 void mx1_init_irq(void);
 void mx21_init_irq(void);
 void mx25_init_irq(void);
 void mx27_init_irq(void);
 void mx31_init_irq(void);
 void mx35_init_irq(void);
-void mx51_init_irq(void);
-void mx53_init_irq(void);
 void imx1_soc_init(void);
 void imx21_soc_init(void);
 void imx25_soc_init(void);
 void imx27_soc_init(void);
 void imx31_soc_init(void);
 void imx35_soc_init(void);
-void imx51_soc_init(void);
-void imx51_init_late(void);
-void imx53_init_late(void);
 void epit_timer_init(void __iomem *base, int irq);
 void mxc_timer_init(void __iomem *, int);
-void mxc_timer_init_dt(struct device_node *);
 int mx1_clocks_init(unsigned long fref);
 int mx21_clocks_init(unsigned long lref, unsigned long fref);
 int mx25_clocks_init(void);
 int mx27_clocks_init(unsigned long fref);
 int mx31_clocks_init(unsigned long fref);
 int mx35_clocks_init(void);
-int mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2);
-int mx25_clocks_init_dt(void);
-int mx27_clocks_init_dt(void);
 int mx31_clocks_init_dt(void);
 struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
@@ -75,8 +62,10 @@ void mxc_set_cpu_type(unsigned int type);
 void mxc_restart(enum reboot_mode, const char *);
 void mxc_arch_reset_init(void __iomem *);
 void mxc_arch_reset_init_dt(void);
+int mx51_revision(void);
 int mx53_revision(void);
 void imx_set_aips(void __iomem *);
+void imx_aips_allow_unprivileged_access(const char *compat);
 int mxc_device_init(void);
 void imx_set_soc_revision(unsigned int rev);
 unsigned int imx_get_soc_revision(void);
@@ -117,7 +106,7 @@ static inline void imx_scu_standby_enable(void) {}
 #endif
 void imx_src_init(void);
 void imx_gpc_init(void);
-void imx_gpc_pre_suspend(void);
+void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
 void imx_gpc_restore_all(void);
@@ -127,7 +116,7 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_int_mem_clk_lpm(void);
+void imx6q_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
 
 void imx_cpu_die(unsigned int cpu);
@@ -144,12 +133,17 @@ static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 void imx6q_pm_init(void);
 void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
+void imx6sx_pm_init(void);
 void imx6q_pm_set_ccm_base(void __iomem *base);
 
 #ifdef CONFIG_PM
-void imx5_pm_init(void);
+void imx51_pm_init(void);
+void imx53_pm_init(void);
+void imx5_pm_set_ccm_base(void __iomem *base);
 #else
-static inline void imx5_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
+static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
 #endif
 
 #ifdef CONFIG_NEON
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index c1c99a72c6a1..3403bac94a31 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -16,6 +16,8 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "hardware.h"
 #include "common.h"
@@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1;
 
 #define IIM_SREV 0x24
 
+static u32 imx5_read_srev_reg(const char *compat)
+{
+        void __iomem *iim_base;
+        struct device_node *np;
+        u32 srev;
+
+        np = of_find_compatible_node(NULL, NULL, compat);
+        iim_base = of_iomap(np, 0);
+        WARN_ON(!iim_base);
+
+        srev = readl(iim_base + IIM_SREV) & 0xff;
+
+        iounmap(iim_base);
+
+        return srev;
+}
+
 static int get_mx51_srev(void)
 {
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+        u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
 
         switch (rev) {
         case 0x0:
@@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void)
 
 static int get_mx53_srev(void)
 {
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+        u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
 
         switch (rev) {
         case 0x0:
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index bbe8ff1f0412..df42c14ff749 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -2,6 +2,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 
@@ -60,6 +61,18 @@ void __init imx_set_aips(void __iomem *base)
         __raw_writel(reg, base + 0x50);
 }
 
+void __init imx_aips_allow_unprivileged_access(
+                const char *compat)
+{
+        void __iomem *aips_base_addr;
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, compat) {
+                aips_base_addr = of_iomap(np, 0);
+                imx_set_aips(aips_base_addr);
+        }
+}
+
 struct device * __init imx_soc_device_init(void)
 {
         struct soc_device_attribute *soc_dev_attr;
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 6bcae0479049..10844d3bb926 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -13,6 +13,7 @@
 
 #include "common.h"
 #include "cpuidle.h"
+#include "hardware.h"
 
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
@@ -66,10 +67,11 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
 int __init imx6q_cpuidle_init(void)
 {
         /* Need to enable SCU standby for entering WAIT modes */
-        imx_scu_standby_enable();
+        if (!cpu_is_imx6sx())
+                imx_scu_standby_enable();
 
         /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
-        imx6q_set_int_mem_clk_lpm();
+        imx6q_set_int_mem_clk_lpm(true);
 
         return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h
deleted file mode 100644
index 5e3f1f0f4cab..000000000000
--- a/arch/arm/mach-imx/crm-regs-imx5.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MX51_CCM_BASE           MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
-#define MX51_DPLL1_BASE         MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
-#define MX51_DPLL2_BASE         MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
-#define MX51_DPLL3_BASE         MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE      MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE           MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-
-/*MX53*/
-#define MX53_CCM_BASE           MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
-#define MX53_DPLL1_BASE         MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
-#define MX53_DPLL2_BASE         MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
-#define MX53_DPLL3_BASE         MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE         MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                  0x00
-#define MXC_PLL_DP_CONFIG               0x04
-#define MXC_PLL_DP_OP                   0x08
-#define MXC_PLL_DP_MFD                  0x0C
-#define MXC_PLL_DP_MFN                  0x10
-#define MXC_PLL_DP_MFNMINUS             0x14
-#define MXC_PLL_DP_MFNPLUS              0x18
-#define MXC_PLL_DP_HFS_OP               0x1C
-#define MXC_PLL_DP_HFS_MFD              0x20
-#define MXC_PLL_DP_HFS_MFN              0x24
-#define MXC_PLL_DP_MFN_TOGC             0x28
-#define MXC_PLL_DP_DESTAT               0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
-#define MXC_PLL_DP_CTL_ADE              0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
-#define MXC_PLL_DP_CTL_HFSM             0x80
-#define MXC_PLL_DP_CTL_PRE              0x40
-#define MXC_PLL_DP_CTL_UPEN             0x20
-#define MXC_PLL_DP_CTL_RST              0x10
-#define MXC_PLL_DP_CTL_RCP              0x8
-#define MXC_PLL_DP_CTL_PLM              0x4
-#define MXC_PLL_DP_CTL_BRM0             0x2
-#define MXC_PLL_DP_CTL_LRF              0x1
-
-#define MXC_PLL_DP_CONFIG_BIST          0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE        0x4
-#define MXC_PLL_DP_CONFIG_AREN          0x2
-#define MXC_PLL_DP_CONFIG_LDREQ         0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET        4
-#define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET        0
-#define MXC_PLL_DP_OP_PDF_MASK          0xF
-
-#define MXC_PLL_DP_MFD_OFFSET           0
-#define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET           0x0
-#define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR             (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR            (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR             (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR            (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR           (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR           (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR           (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1          (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2          (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1          (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR          (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR          (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR           (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR          (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2          (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3          (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4          (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR            (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR          (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR            (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR            (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR           (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR            (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR            (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR           (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR            (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0           (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1           (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2           (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3           (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4           (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5           (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6           (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7           (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR           (MX51_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN             (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK       (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN            (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN            (1 << 9)
-#define MXC_CCM_CCR_FPM_EN              (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET        (0)
-#define MXC_CCM_CCR_OSCNT_MASK  (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK        (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK        (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK        (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY  (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE   (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_FPM_READY   (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B    (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL         (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET    (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK      (0x3 << 7)
-#define MXC_CCM_CCSR_STEP_SEL_LP_APM       0
-#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
-#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET   (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK     (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET   (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK     (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL    (1 << 2) /* 0: pll1_main_clk,
-                                                    1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL    (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL    (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET   (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK     (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL               (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL            (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET         (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL                (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET           (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK             (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET           (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK             (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET         (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK           (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET         (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET           (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK             (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET           (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK             (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET           (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK             (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET       (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK         (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET       (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK         (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET        (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK          (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET    (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK      (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET     (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK       (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET        (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK          (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET    (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK      (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET    (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK      (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET        (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK          (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET      (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK        (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL     (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL        (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET          (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK            (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET          (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK            (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET           (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                  (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET              (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK                (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET            (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK              (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                     (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                     (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET           (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK             (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL                      (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                  (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET              (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK                (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET             (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK               (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL             (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL             (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)             (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)               (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET         (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK           (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET         (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK           (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET               (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                 (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET              (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK                (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET              (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK                (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET             (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK               (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET               (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                 (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM                      (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET           (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK             (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM                       (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM                       (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET            (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK              (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET            (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK              (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET     (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK                (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET     (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK       (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET             (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK               (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET               (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                 (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET                (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                  (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET               (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                 (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET               (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                 (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET             (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK               (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET             (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK               (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET            (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK              (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK              (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET             (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK               (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET             (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK               (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET              (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK                (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET              (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK                (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET          (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK                (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET              (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK                (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET        (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK          (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET        (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK          (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET        (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK          (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET        (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK          (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY              (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                    (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                 (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY        (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                    (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                  (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                  (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER             (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET        (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK          (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS         (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS         (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS        (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS         (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS         (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS        (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS        (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN              (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET         (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK           (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY                     (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC               (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS                     (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM        (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET       (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK         (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET                (0)
-#define MXC_CCM_CLPCR_LPM_MASK                  (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED                    (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED        (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED                    (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED                    (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED                  (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED                  (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED                     (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY                         (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY                        (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY                         (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY                          (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3                           (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2                           (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1                           (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED   (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED               (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED             (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED             (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED             (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED                (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY                    (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY                    (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY                     (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3                      (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2                      (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1                      (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK                     (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL                            (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET            (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK              (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGRx_CG_MASK                           0x3
-#define MXC_CCM_CCGRx_MOD_OFF                           0x0
-#define MXC_CCM_CCGRx_MOD_ON                            0x3
-#define MXC_CCM_CCGRx_MOD_IDLE                          0x1
-
-#define MXC_CCM_CCGRx_CG15_MASK                         (0x3 << 30)
-#define MXC_CCM_CCGRx_CG14_MASK                         (0x3 << 28)
-#define MXC_CCM_CCGRx_CG13_MASK                         (0x3 << 26)
-#define MXC_CCM_CCGRx_CG12_MASK                         (0x3 << 24)
-#define MXC_CCM_CCGRx_CG11_MASK                         (0x3 << 22)
-#define MXC_CCM_CCGRx_CG10_MASK                         (0x3 << 20)
-#define MXC_CCM_CCGRx_CG9_MASK                          (0x3 << 18)
-#define MXC_CCM_CCGRx_CG8_MASK                          (0x3 << 16)
-#define MXC_CCM_CCGRx_CG5_MASK                          (0x3 << 10)
-#define MXC_CCM_CCGRx_CG4_MASK                          (0x3 << 8)
-#define MXC_CCM_CCGRx_CG3_MASK                          (0x3 << 6)
-#define MXC_CCM_CCGRx_CG2_MASK                          (0x3 << 4)
-#define MXC_CCM_CCGRx_CG1_MASK                          (0x3 << 2)
-#define MXC_CCM_CCGRx_CG0_MASK                          (0x3 << 0)
-
-#define MXC_CCM_CCGRx_CG15_OFFSET                       30
-#define MXC_CCM_CCGRx_CG14_OFFSET                       28
-#define MXC_CCM_CCGRx_CG13_OFFSET                       26
-#define MXC_CCM_CCGRx_CG12_OFFSET                       24
-#define MXC_CCM_CCGRx_CG11_OFFSET                       22
-#define MXC_CCM_CCGRx_CG10_OFFSET                       20
-#define MXC_CCM_CCGRx_CG9_OFFSET                        18
-#define MXC_CCM_CCGRx_CG8_OFFSET                        16
-#define MXC_CCM_CCGRx_CG7_OFFSET                        14
-#define MXC_CCM_CCGRx_CG6_OFFSET                        12
-#define MXC_CCM_CCGRx_CG5_OFFSET                        10
-#define MXC_CCM_CCGRx_CG4_OFFSET                        8
-#define MXC_CCM_CCGRx_CG3_OFFSET                        6
-#define MXC_CCM_CCGRx_CG2_OFFSET                        4
-#define MXC_CCM_CCGRx_CG1_OFFSET                        2
-#define MXC_CCM_CCGRx_CG0_OFFSET                        0
-
-#define MXC_DPTC_LP_BASE        (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE        (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE      (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE       (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE        (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE        (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE        (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE      (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE       (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE    (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE    (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE   (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE       (MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID          (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC           (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC           (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC           (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC      (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC          (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC           (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC           (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS           (MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS            (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN            (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1            (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0            (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0            (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1            (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT            (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC            (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR            (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0          (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1          (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0          (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1          (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0             (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1             (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2             (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3             (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR            (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR             (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR             (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU          (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON            (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET        8
-#define MXC_GPC_PGR_ARMPG_MASK          (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR        (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR        (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR        (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR        (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR        (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR        (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR            1
-#define MXC_SRPGCR_PCR          1
-#define MXC_EMPGCR_PCR          1
-#define MXC_PGSR_PSR            1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM       (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM   (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR    (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR    (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR    (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR     (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR     (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR     (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR  (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR  (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR  (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR  (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR  (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR  (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR         (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR         (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR         (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR    (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR    (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR    (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif                          /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
deleted file mode 100644
index 26389f35a2b2..000000000000
--- a/arch/arm/mach-imx/devices-imx51.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx51_fec_data;
-#define imx51_add_fec(pdata)    \
-        imx_add_fec(&imx51_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
-#define imx51_add_fsl_usb2_udc(pdata)   \
-        imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
-#define imx51_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
-#define imx51_add_hsi2c(pdata)  \
-        imx51_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
-#define imx51_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
-#define imx51_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
-
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
-#define imx51_add_mxc_ehci_otg(pdata)   \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
-#define imx51_add_mxc_ehci_hs(id, pdata)        \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
-#define imx51_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
-#define imx51_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx51_cspi_data;
-#define imx51_add_cspi(pdata)   \
-        imx_add_spi_imx(&imx51_cspi_data, pdata)
-
-extern const struct imx_spi_imx_data imx51_ecspi_data[];
-#define imx51_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
-#define imx51_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx51_pata_imx_data;
-#define imx51_add_pata_imx() \
-        imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 2d260a5a307c..1d2cc1805f3e 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
         bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
+        default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35
 
 config IMX_HAVE_PLATFORM_FLEXCAN
         bool
@@ -10,7 +10,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC
 
 config IMX_HAVE_PLATFORM_GPIO_KEYS
         bool
-        default y if SOC_IMX51
 
 config IMX_HAVE_PLATFORM_IMX21_HCD
         bool
@@ -43,15 +42,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI
 config IMX_HAVE_PLATFORM_IMX_UART
         bool
 
-config IMX_HAVE_PLATFORM_IMX_UDC
-        bool
-
 config IMX_HAVE_PLATFORM_IPU_CORE
         bool
 
-config IMX_HAVE_PLATFORM_MX1_CAMERA
-        bool
-
 config IMX_HAVE_PLATFORM_MX2_CAMERA
         bool
 
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 1cbc14cd80d1..8fdb12b4ca7e 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -16,9 +16,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 61352a80bb59..67f7fb13050d 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -176,22 +176,6 @@ struct platform_device *__init imx_add_imx_uart_1irq(
                 const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
-#include <linux/platform_data/usb-imx_udc.h>
-struct imx_imx_udc_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq0;
-        resource_size_t irq1;
-        resource_size_t irq2;
-        resource_size_t irq3;
-        resource_size_t irq4;
-        resource_size_t irq5;
-        resource_size_t irq6;
-};
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata);
-
 #include <linux/platform_data/video-mx3fb.h>
 #include <linux/platform_data/camera-mx3.h>
 struct imx_ipu_core_data {
@@ -208,16 +192,6 @@ struct platform_device *__init imx_add_mx3_sdc_fb(
                 const struct imx_ipu_core_data *data,
                 struct mx3fb_platform_data *pdata);
 
-#include <linux/platform_data/camera-mx1.h>
-struct imx_mx1_camera_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata);
-
 #include <linux/platform_data/camera-mx2.h>
 struct imx_mx2_camera_data {
         const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index 63eba08f87b1..d86f9250b4ee 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -35,18 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
         imx_fec_data_entry_single(MX35, "imx27-fec");
 #endif
 
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx27 type fec */
-const struct imx_fec_data imx51_fec_data __initconst =
-        imx_fec_data_entry_single(MX51, "imx27-fec");
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx25 type fec */
-const struct imx_fec_data imx53_fec_data __initconst =
-        imx_fec_data_entry_single(MX53, "imx25-fec");
-#endif
-
 struct platform_device *__init imx_add_fec(
                 const struct imx_fec_data *data,
                 const struct fec_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 3c06bd96e9cc..23b0061347cb 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -38,11 +38,6 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
         imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
-#endif
-
 struct platform_device *__init imx_add_fsl_usb2_udc(
                 const struct imx_fsl_usb2_udc_data *data,
                 const struct fsl_usb2_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 57d342e85c2f..644ac2689882 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -70,32 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
-#define imx51_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx51_imx_i2c_data_entry(0, 1),
-        imx51_imx_i2c_data_entry(1, 2),
-        {
-                .devid = "imx21-i2c",
-                .id = 2,
-                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
-                .iosize = SZ_16K,
-                .irq = MX51_INT_HS_I2C,
-        },
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
-#define imx53_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx53_imx_i2c_data_entry(0, 1),
-        imx53_imx_i2c_data_entry(1, 2),
-        imx53_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index 8f22a4c98a4c..f42200b7aca9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -41,16 +41,6 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX35, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX51, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX53, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_keypad(
                 const struct imx_imx_keypad_data *data,
                 const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index bfcb8f3dfa8d..1c7c721ebff1 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -66,26 +66,6 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
-#define imx51_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx_ssi_data_entry(0, 1),
-        imx51_imx_ssi_data_entry(1, 2),
-        imx51_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
-#define imx53_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx_ssi_data_entry(0, 1),
-        imx53_imx_ssi_data_entry(1, 2),
-        imx53_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_ssi(
                 const struct imx_imx_ssi_data *data,
                 const struct imx_ssi_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index faac4aa6ca6d..8c01836bc1d4 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -94,28 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
-#define imx51_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
-        imx51_imx_uart_data_entry(0, 1),
-        imx51_imx_uart_data_entry(1, 2),
-        imx51_imx_uart_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
-#define imx53_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
-        imx53_imx_uart_data_entry(0, 1),
-        imx53_imx_uart_data_entry(1, 2),
-        imx53_imx_uart_data_entry(2, 3),
-        imx53_imx_uart_data_entry(3, 4),
-        imx53_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_uart_3irq(
                 const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index ec75d6413686..54f63bc25ca4 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -45,24 +45,6 @@ const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
         imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
-#define imx51_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx2_wdt_data_entry(0, 1),
-        imx51_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
-#define imx53_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx2_wdt_data_entry(0, 1),
-        imx53_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx2_wdt(
                 const struct imx_imx2_wdt_data *data)
 {
diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c
deleted file mode 100644
index 5ced7e4e2c71..000000000000
--- a/arch/arm/mach-imx/devices/platform-imx_udc.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_udc_data_entry_single(soc, _size)                       \
-        {                                                               \
-                .iobase = soc ## _USBD_BASE_ADDR,                       \
-                .iosize = _size,                                        \
-                .irq0 = soc ## _INT_USBD0,                              \
-                .irq1 = soc ## _INT_USBD1,                              \
-                .irq2 = soc ## _INT_USBD2,                              \
-                .irq3 = soc ## _INT_USBD3,                              \
-                .irq4 = soc ## _INT_USBD4,                              \
-                .irq5 = soc ## _INT_USBD5,                              \
-                .irq6 = soc ## _INT_USBD6,                              \
-        }
-
-#define imx_imx_udc_data_entry(soc, _size)                              \
-        [_id] = imx_imx_udc_data_entry_single(soc, _size)
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
-        imx_imx_udc_data_entry_single(MX1, SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq0,
-                        .end = data->irq0,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq1,
-                        .end = data->irq1,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq2,
-                        .end = data->irq2,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq3,
-                        .end = data->irq3,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq4,
-                        .end = data->irq4,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq5,
-                        .end = data->irq5,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq6,
-                        .end = data->irq6,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imx_udc", 0,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c
deleted file mode 100644
index 2c6788131080..000000000000
--- a/arch/arm/mach-imx/devices/platform-mx1-camera.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx1_camera_data_entry_single(soc, _size)                    \
-        {                                                               \
-                .iobase = soc ## _CSI ## _BASE_ADDR,                    \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CSI,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
-        imx_mx1_camera_data_entry_single(MX1, 10);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("mx1-camera", 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 5d4bbbfde641..296353662ff0 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -50,15 +50,6 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
         imx_mxc_ehci_data_entry_single(MX35, 1, HS);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
-const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
-        imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
-        imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
 struct platform_device *__init imx_add_mxc_ehci(
                 const struct imx_mxc_ehci_data *data,
                 const struct mxc_usbh_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index 7af1c53e42b5..fa618a34f462 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -54,11 +54,6 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
 #endif
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-        imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
-#endif
-
 struct platform_device *__init imx_add_mxc_nand(
                 const struct imx_mxc_nand_data *data,
                 const struct mxc_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
index c58404badb59..851fbc8af7a9 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
@@ -48,9 +48,6 @@ static int __init imxXX_add_mxc_rnga(void)
 #endif /* if defined(CONFIG_SOC_IMX31) */
                 ret = ERR_PTR(-ENODEV);
 
-        if (IS_ERR(ret))
-                return PTR_ERR(ret);
-
-        return 0;
+        return PTR_ERR_OR_ZERO(ret);
 }
 arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
index e4ec11c8ce55..1c7f895a69d2 100644
--- a/arch/arm/mach-imx/devices/platform-pata_imx.c
+++ b/arch/arm/mach-imx/devices/platform-pata_imx.c
@@ -28,16 +28,6 @@ const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
         imx_pata_imx_data_entry_single(MX35, SZ_16K);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX51, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX53, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_pata_imx(
                 const struct imx_pata_imx_data *data)
 {
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index e66a4e316311..fb8d4a2ad48c 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -43,30 +43,6 @@ imx35_sdhci_esdhc_imx_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_sdhci_esdhc_imx_data
-imx51_sdhci_esdhc_imx_data[] __initconst = {
-#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid)
-        imx51_sdhci_esdhc_imx_data_entry(0, 1),
-        imx51_sdhci_esdhc_imx_data_entry(1, 2),
-        imx51_sdhci_esdhc_imx_data_entry(2, 3),
-        imx51_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_sdhci_esdhc_imx_data
-imx53_sdhci_esdhc_imx_data[] __initconst = {
-#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid)
-        imx53_sdhci_esdhc_imx_data_entry(0, 1),
-        imx53_sdhci_esdhc_imx_data_entry(1, 2),
-        imx53_sdhci_esdhc_imx_data_entry(2, 3),
-        imx53_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
         .wp_type = ESDHC_WP_NONE,
         .cd_type = ESDHC_CD_NONE,
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 8880bcb11e05..aca825d74c48 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -79,33 +79,6 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx51_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
-#define imx51_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx51_ecspi_data_entry(0, 1),
-        imx51_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx53_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-/* i.mx53 has the i.mx51 type ecspi */
-const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
-#define imx53_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx53_ecspi_data_entry(0, 1),
-        imx53_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_spi_imx(
                 const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata)
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 134c190e3003..42a5a3d14c5f 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index 448d9115539d..c56974346c16 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 05de4e1e39d7..bede21d9b981 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 554e7cccff53..f424a543755c 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
deleted file mode 100644
index e49710b10c68..000000000000
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "hardware.h"
-
-#define MXC_OTG_OFFSET                  0
-#define MXC_H1_OFFSET                   0x200
-#define MXC_H2_OFFSET                   0x400
-
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
-
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
-#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
-#define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
-
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
-
-#define MXC_USBCMD_OFFSET               0x140
-
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
-
-int mx51_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-        void __iomem *usb_base;
-        void __iomem *usbotg_base;
-        void __iomem *usbother_base;
-        int ret = 0;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base) {
-                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-                return -ENOMEM;
-        }
-
-        switch (port) {
-        case 0: /* OTG port */
-                usbotg_base = usb_base + MXC_OTG_OFFSET;
-                break;
-        case 1: /* Host 1 port */
-                usbotg_base = usb_base + MXC_H1_OFFSET;
-                break;
-        case 2: /* Host 2 port */
-                usbotg_base = usb_base + MXC_H2_OFFSET;
-                break;
-        default:
-                printk(KERN_ERR"%s no such port %d\n", __func__, port);
-                ret = -ENOENT;
-                goto error;
-        }
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        switch (port) {
-        case 0: /*OTG port */
-                if (flags & MXC_EHCI_INTERNAL_PHY) {
-                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                                v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                /* OC/USBPWR is used */
-                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        } else {
-                                /* OC/USBPWR is not used */
-                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        }
-                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                        else
-                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                        else
-                                v |= MXC_OTG_UCTRL_OPM_BIT;
-                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                }
-                break;
-        case 1: /* Host 1 */
-                /*Host ULPI */
-                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
-                else
-                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
-                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                        v |= MXC_H1_OC_POL_BIT;
-                else
-                        v &= ~MXC_H1_OC_POL_BIT;
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-                else
-                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                        /* Interrupt Threshold Control:Immediate (no threshold) */
-                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-                break;
-        case 2: /* Host 2 ULPI */
-                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
-                else
-                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-                break;
-        }
-
-error:
-        iounmap(usb_base);
-        return ret;
-}
-
diff --git a/arch/arm/mach-imx/ehci.h b/arch/arm/mach-imx/ehci.h
new file mode 100644
index 000000000000..0e060023db8b
--- /dev/null
+++ b/arch/arm/mach-imx/ehci.h
@@ -0,0 +1,43 @@
+#ifndef __MACH_IMX_EHCI_H
+#define __MACH_IMX_EHCI_H
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND  (1 << 23)
+#define MXC_EHCI_FORCE_FS               (1 << 24)
+#define MXC_EHCI_UTMI_8BIT              (0 << 28)
+#define MXC_EHCI_UTMI_16BIT             (1 << 28)
+#define MXC_EHCI_SERIAL                 (1 << 29)
+#define MXC_EHCI_MODE_UTMI              (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS           (1 << 30)
+#define MXC_EHCI_MODE_ULPI              (2 << 30)
+#define MXC_EHCI_MODE_SERIAL            (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI     (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI      (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI   (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI    (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK         (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH    (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW      (1 << 7)
+#define MXC_EHCI_TTL_ENABLED            (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY           (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN             (1 << 10)
+#define MXC_EHCI_IPPUE_UP               (1 << 11)
+#define MXC_EHCI_WAKEUP_ENABLED         (1 << 12)
+#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 13)
+
+#define MXC_USBCTRL_OFFSET              0
+#define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
+#define MXC_USB_PHY_CTR_FUNC2_OFFSET    0xc
+#define MXC_USBH2CTRL_OFFSET            0x14
+
+int mx25_initialize_usb_hw(int port, unsigned int flags);
+int mx31_initialize_usb_hw(int port, unsigned int flags);
+int mx35_initialize_usb_hw(int port, unsigned int flags);
+int mx27_initialize_usb_hw(int port, unsigned int flags);
+
+#endif /* __MACH_IMX_EHCI_H */
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 586e0171a652..82ea74e68482 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -27,13 +27,14 @@ static void __iomem *gpc_base;
 static u32 gpc_wake_irqs[IMR_NUM];
 static u32 gpc_saved_imrs[IMR_NUM];
 
-void imx_gpc_pre_suspend(void)
+void imx_gpc_pre_suspend(bool arm_power_off)
 {
         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
         int i;
 
         /* Tell GPC to power off ARM core when suspend */
-        writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+        if (arm_power_off)
+                writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
 
         for (i = 0; i < IMR_NUM; i++) {
                 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index abf43bb47eca..66b2b564c463 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -105,8 +105,6 @@
 
 #include "mxc.h"
 
-#include "mx51.h"
-#include "mx53.h"
 #include "mx3x.h"
 #include "mx31.h"
 #include "mx35.h"
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 42a65e067443..cf8032bae277 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -29,16 +29,10 @@ static const char * const imx25_dt_board_compat[] __initconst = {
         NULL
 };
 
-static void __init imx25_timer_init(void)
-{
-        mx25_clocks_init_dt();
-}
-
 DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
         .map_io         = mx25_map_io,
         .init_early     = imx25_init_early,
         .init_irq       = mx25_init_irq,
-        .init_time      = imx25_timer_init,
         .init_machine   = imx25_dt_init,
         .dt_compat      = imx25_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 17bd4058133d..080e66c6a1d0 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = {
         NULL
 };
 
-static void __init imx27_timer_init(void)
-{
-        mx27_clocks_init_dt();
-}
-
 DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
         .map_io         = mx27_map_io,
         .init_early     = imx27_init_early,
         .init_irq       = mx27_init_irq,
-        .init_time      = imx27_timer_init,
         .init_machine   = imx27_dt_init,
         .dt_compat      = imx27_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 581f4d6c9b8a..418dbc82adc4 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx31_dt_board_compat[] __initconst = {
+static const char * const imx31_dt_board_compat[] __initconst = {
         "fsl,imx31",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index a62854c59240..584fbe105579 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -34,7 +34,7 @@ static void __init imx35_irq_init(void)
         mx35_init_irq();
 }
 
-static const char *imx35_dt_board_compat[] __initconst = {
+static const char * const imx35_dt_board_compat[] __initconst = {
         "fsl,imx35",
         NULL
 };
diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
deleted file mode 100644
index 75bbcc4aa2d2..000000000000
--- a/arch/arm/mach-imx/iomux-mx51.h
+++ /dev/null
@@ -1,827 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX51_H__
-#define __MACH_IOMUX_MX51_H__
-
-#include "iomux-v3.h"
-#define __NA_   0x000
-
-
-/* Pad control groupings */
-#define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_ESDHC_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS | PAD_CTL_PUE)
-#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_HYS | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
-                                PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-
-#define MX51_PAD_CTRL_2         (PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_3         (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_CTRL_4         (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_5         (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
-/*
- * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* Raw pin modes without pad control */
-/*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
-
-/* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS             IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__AUD5_TXD              IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16               IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO2_0               IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D16__UART2_CTS             IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D16__USBH2_DATA0           IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__AUD5_RXD              IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17               IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO2_1               IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART2_RXD             IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART3_CTS             IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__USBH2_DATA1           IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__AUD5_TXC              IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18               IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO2_2               IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART2_TXD             IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART3_RTS             IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__USBH2_DATA2           IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD4_RXC              IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD5_TXFS             IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19               IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO2_3               IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D19__UART2_RTS             IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D19__USBH2_DATA3           IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__AUD4_TXD              IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20               IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO2_4               IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__USBH2_DATA4           IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__AUD4_RXD              IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21               IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO2_5               IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__USBH2_DATA5           IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__AUD4_TXC              IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22               IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO2_6               IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__USBH2_DATA6           IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__AUD4_TXFS             IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23               IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO2_7               IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__SPDIF_OUT1            IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__USBH2_DATA7           IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__AUD6_RXFS             IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24               IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__GPIO2_8               IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__I2C2_SDA              IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D24__USBOTG_DATA0          IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25               IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__KEY_COL6              IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__GPT_CMPOUT1           IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__GPT_CMPOUT2           IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__I2C2_SCL              IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D27__USBOTG_DATA3          IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__AUD6_TXD              IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__KEY_ROW4              IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__USBOTG_DATA4          IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__AUD6_RXD              IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__KEY_ROW5              IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__USBOTG_DATA5          IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__AUD6_TXC              IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__KEY_ROW6              IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__USBOTG_DATA6          IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__AUD6_TXFS             IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__KEY_ROW7              IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__USBOTG_DATA7          IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16               IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO2_10              IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17               IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO2_11              IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__BOOT_LPB0             IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18               IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO2_12              IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__BOOT_LPB1             IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19               IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO2_13              IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__EIM_A20               IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14              IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__EIM_A21               IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO2_15              IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22               IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO2_16              IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN           IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23               IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO2_17              IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24               IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO2_18              IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__USBH2_CLK             IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__DISP1_PIN4            IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25               IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO2_19              IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__USBH2_DIR             IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN          IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26               IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO2_20              IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__USBH2_STP             IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN          IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__DISP1_PIN1            IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27               IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO2_21              IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__USBH2_NXT             IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__AUD5_RXFS             IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__CSI1_D2               IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__EIM_EB2               IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO              (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
-                MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22              IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__AUD5_RXC              IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__CSI1_D3               IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__EIM_EB3               IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1            IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPIO2_23              IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__EIM_OE                 IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__GPIO2_24               IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0               IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO2_25              IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1               IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO2_26              IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__AUD5_TXD              IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__CSI1_D4               IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__EIM_CS2               IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2            IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO2_27              IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__USBOTG_STP            IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__AUD5_RXD              IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__CSI1_D5               IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__EIM_CS3               IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3            IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__GPIO2_28              IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__USBOTG_NXT            IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__AUD5_TXC              IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__CSI1_D6               IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__EIM_CS4               IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO2_29              IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__USBOTG_CLK            IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__AUD5_TXFS             IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__CSI1_D7               IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__EIM_CS5               IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO2_30              IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__USBOTG_DIR            IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__EIM_DTACK           IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31            IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA               IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO3_1               IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__CCM_CLKO             IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO3_4            IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR          IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO3_5             IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE           IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO3_6             IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE           IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B        IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO3_7            IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK         IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO3_8             IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0           IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ          IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI           IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2         IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3         IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__NANDF_CS0           IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO3_17            IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1           IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK           IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS2__GPIO3_18            IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__PATA_DA_0           IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__USBH3_STP           IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2          IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO3_21            IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__NANDF_CS5           IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__PATA_DA_1           IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__USBH3_DIR           IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__CSPI_SS3            IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3          IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO3_22            IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__NANDF_CS6           IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__PATA_DA_2           IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO3_23            IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__NANDF_CS7           IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__SD3_CLK             IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__PATA_DATA15         IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__SD3_DAT7            IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3          IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO3_26            IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14           IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__PATA_DATA14         IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__SD3_DAT6            IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2          IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO3_27            IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13           IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__PATA_DATA13         IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__SD3_DAT5            IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1          IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO3_28            IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12           IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__PATA_DATA12         IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__SD3_DAT4            IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV           IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO3_29            IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__NANDF_D11           IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__PATA_DATA11         IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__SD3_DATA3           IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO3_30            IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__NANDF_D10           IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__PATA_DATA10         IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__SD3_DATA2           IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__FEC_RDATA0           IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D9__GPIO3_31             IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__NANDF_D9             IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__PATA_DATA9           IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__SD3_DATA1            IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0           IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_D8__GPIO4_0              IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__NANDF_D8             IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__PATA_DATA8           IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__SD3_DATA0            IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO4_1              IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__NANDF_D7             IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__PATA_DATA7           IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__USBH3_DATA0          IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO4_2              IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6             IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__PATA_DATA6           IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__SD4_LCTL             IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__USBH3_DATA1          IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO4_3              IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5             IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__PATA_DATA5           IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__SD4_WP               IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__USBH3_DATA2          IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO4_4              IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4             IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__PATA_DATA4           IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__SD4_CD               IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__USBH3_DATA3          IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO4_5              IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3             IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__PATA_DATA3           IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__SD4_DAT4             IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__USBH3_DATA4          IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO4_6              IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2             IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__PATA_DATA2           IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__SD4_DAT5             IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__USBH3_DATA5          IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO4_7              IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1             IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__PATA_DATA1           IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__SD4_DAT6             IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__USBH3_DATA6          IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO4_8              IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0             IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__PATA_DATA0           IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__SD4_DAT7             IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__USBH3_DATA7          IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8               IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO3_12              IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9               IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO3_13              IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14           IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15           IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12             IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO4_9              IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13             IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO4_10             IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14             IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15             IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16             IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17             IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18             IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO4_11             IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19             IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO4_12             IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13           IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14           IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO4_16             IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK             IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO4_17             IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT             IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20           IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21           IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD          IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22           IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD           IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO4_23           IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC            IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO4_24            IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD            IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO4_25            IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO4_26            IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27           IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__GPIO4_28            IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__GPIO4_29            IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__PWM2_PWMO           IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__GPIO4_30            IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__GPIO4_31            IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__FIRI_TXD            IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__GPIO1_20            IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__FIRI_RXD            IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__GPIO1_21            IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__CSI1_D0             IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO1_22            IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART1_DTR           IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__CSI1_D1             IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO1_23            IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART1_DSR           IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO1_24           IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__PLL1_BYP             IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__PLL2_BYP             IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__PLL3_BYP             IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1           IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART1_RI             IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART1_DCD            IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK           IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__GPIO1_25            IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__I2C2_SCL            IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI           IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__GPIO1_26            IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__I2C2_SDA            IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__CSPI_RDY            IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO1_27            IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__UART3_RXD           IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__CSPI_MISO           IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__GPIO1_28            IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__UART3_TXD           IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__GPIO1_11          IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__UART2_CTS         IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__GPIO1_12          IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__UART2_RXD         IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__GPIO1_13          IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__UART2_TXD         IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__GPIO1_14          IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__UART2_RTS         IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0          IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__GPIO1_15          IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1          IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__GPIO1_16          IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3          IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__GPIO1_17          IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__GPIO1_18          IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11           IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO3_0             IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12           IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO3_1             IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13           IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO3_2             IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO3_3             IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4             IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK     IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN15__DI1_PIN15           IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO          IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER              IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS              IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC              IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO             IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI2_PIN15              IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN          IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP2_PIN1             IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2             IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__KEY_COL6           IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__UART3_RXD          IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK          IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__KEY_COL7           IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__UART3_TXD          IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR          IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL           IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7          IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC          IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__CSPI_MOSI             IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__CSPI_SCLK             IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__CSPI_MISO           IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__I2C1_SDA              IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__CSPI_MISO           IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD1_DAT4            IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__CCM_CLKO2             IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPT_CLKIN             IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPT_CAPIN1            IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CCM_CLKO              IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPT_CAPIN2            IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CCM_CLKO2             IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_CLKO              IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 39406b7e3228..a7e9bd26a552 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -50,6 +50,7 @@
 #include "common.h"
 #include "devices-imx31.h"
 #include "crmregs-imx3.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 75b7b6aa2720..e6d4b9929571 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -36,6 +36,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 1ffa27169045..62a6e02f4763 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -39,6 +39,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index e978dda1434c..b2ee6e009fe4 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -35,6 +35,7 @@
 
 #include "common.h"
 #include "devices-imx25.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index b61bd8ed5568..ede2bdbb5dd5 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -43,6 +43,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
deleted file mode 100644
index bb3ca0429680..000000000000
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "hardware.h"
-#include "common.h"
-#include "devices-imx27.h"
-#include "iomux-mx27.h"
-
-static const int mx27ipcam_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-};
-
-static void __init mx27ipcam_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
-                "mx27ipcam");
-
-        imx27_add_imx_uart0(NULL);
-        imx27_add_fec(NULL);
-        imx27_add_imx2_wdt();
-}
-
-static void __init mx27ipcam_timer_init(void)
-{
-        mx27_clocks_init(25000000);
-}
-
-MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
-        /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = mx27ipcam_timer_init,
-        .init_machine = mx27ipcam_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
deleted file mode 100644
index 9992089d3ad1..000000000000
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-static const int mx27lite_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init mx27lite_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
-                "imx27lite");
-        imx27_add_imx_uart0(&uart_pdata);
-        imx27_add_fec(NULL);
-}
-
-static void __init mx27lite_timer_init(void)
-{
-        mx27_clocks_init(26000000);
-}
-
-MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = mx27lite_timer_init,
-        .init_machine = mx27lite_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index b899c0b59afd..b1e56a94a382 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -23,14 +23,13 @@ static void __init imx50_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx50_dt_board_compat[] __initconst = {
+static const char * const imx50_dt_board_compat[] __initconst = {
         "fsl,imx50",
         NULL
 };
 
 DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
-        .map_io         = mx53_map_io,
-        .init_irq       = mx53_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx50_dt_init,
         .dt_compat      = imx50_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/mach-imx51.c
index b8cd968faa52..c77deb3f0893 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -10,6 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -17,27 +18,63 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "mx51.h"
+#include "hardware.h"
+
+static void __init imx51_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX51);
+}
+
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured for proper
+ * IPU support.
+ */
+#define MX51_MIPI_HSC_BASE 0x83fdc000
+static void __init imx51_ipu_mipi_setup(void)
+{
+        void __iomem *hsc_addr;
+
+        hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
+        WARN_ON(!hsc_addr);
+
+        /* setup MIPI module to legacy mode */
+        __raw_writel(0xf00, hsc_addr);
+
+        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
+                hsc_addr + 0x800);
+
+        iounmap(hsc_addr);
+}
 
 static void __init imx51_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
         mxc_arch_reset_init_dt();
+        imx51_ipu_mipi_setup();
+        imx_src_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         platform_device_register_full(&devinfo);
 }
 
-static const char *imx51_dt_board_compat[] __initconst = {
+static void __init imx51_init_late(void)
+{
+        mx51_neon_fixup();
+        imx51_pm_init();
+}
+
+static const char * const imx51_dt_board_compat[] __initconst = {
         "fsl,imx51",
         NULL
 };
 
 DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
-        .map_io         = mx51_map_io,
         .init_early     = imx51_init_early,
-        .init_irq       = mx51_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx51_dt_init,
         .init_late      = imx51_init_late,
         .dt_compat      = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 2bad387956c0..03dd6ea13acc 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -22,24 +22,35 @@
 
 #include "common.h"
 #include "hardware.h"
-#include "mx53.h"
+
+static void __init imx53_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX53);
+}
 
 static void __init imx53_dt_init(void)
 {
         mxc_arch_reset_init_dt();
+        imx_src_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+        imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
+}
+
+static void __init imx53_init_late(void)
+{
+        imx53_pm_init();
 }
 
-static const char *imx53_dt_board_compat[] __initconst = {
+static const char * const imx53_dt_board_compat[] __initconst = {
         "fsl,imx53",
         NULL
 };
 
 DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
-        .map_io         = mx53_map_io,
         .init_early     = imx53_init_early,
-        .init_irq       = mx53_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx53_dt_init,
         .init_late      = imx53_init_late,
         .dt_compat      = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index e60456d85c9d..d51c6e99a2e9 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -320,7 +320,7 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
         val >>= OCOTP_CFG3_SPEED_SHIFT;
         val &= 0x3;
 
-        if (val != OCOTP_CFG3_SPEED_1P2GHZ)
+        if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q())
                 if (dev_pm_opp_disable(cpu_dev, 1200000000))
                         pr_warn("failed to disable 1.2 GHz OPP\n");
         if (val < OCOTP_CFG3_SPEED_996MHZ)
@@ -396,7 +396,7 @@ static void __init imx6q_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6q_dt_compat[] __initconst = {
+static const char * const imx6q_dt_compat[] __initconst = {
         "fsl,imx6dl",
         "fsl,imx6q",
         NULL,
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index ad323385115c..ed263a21d928 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -70,7 +70,7 @@ static void __init imx6sl_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6sl_dt_compat[] __initconst = {
+static const char * const imx6sl_dt_compat[] __initconst = {
         "fsl,imx6sl",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 02fccf6033ac..673a734165ba 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -12,6 +12,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "cpuidle.h"
 
 static void __init imx6sx_init_machine(void)
 {
@@ -26,6 +27,7 @@ static void __init imx6sx_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
         imx_anatop_init();
+        imx6sx_pm_init();
 }
 
 static void __init imx6sx_init_irq(void)
@@ -37,7 +39,12 @@ static void __init imx6sx_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6sx_dt_compat[] __initconst = {
+static void __init imx6sx_init_late(void)
+{
+        imx6q_cpuidle_init();
+}
+
+static const char * const imx6sx_dt_compat[] __initconst = {
         "fsl,imx6sx",
         NULL,
 };
@@ -47,5 +54,6 @@ DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
         .init_irq       = imx6sx_init_irq,
         .init_machine   = imx6sx_init_machine,
         .dt_compat      = imx6sx_dt_compat,
+        .init_late      = imx6sx_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index ea1fa199c148..0d01e367b062 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -39,6 +39,7 @@
 
 #include "common.h"
 #include "devices-imx25.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx25.h"
 #include "mx25.h"
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 435a5428a678..9ef4640f3660 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -40,6 +40,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4217871a9653..453f41a2c5a9 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -40,6 +40,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index eee042fa2768..e9549a3c0223 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -45,6 +45,7 @@
 #include "board-mx31lilly.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index fa15d0b6118d..57eac6f45fab 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -42,6 +42,7 @@
 #include "board-mx31lite.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 08730f238449..bb6f8a52a6b8 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -47,6 +47,7 @@
 #include "board-mx31moboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -434,10 +435,8 @@ static int __init moboard_usbh2_init(void)
                 return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 static const struct gpio_led mx31moboard_leds[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 4e8b184d773b..72cd77d21f63 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -50,6 +50,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 12212378c672..2d1c50bd8bdf 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,6 +36,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 81b8affb9448..8eb1570f7851 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -45,6 +45,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "pcm037.h"
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 6c56fb5553c7..ee862ad6b6fc 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,6 +36,7 @@
 #include "board-pcm038.h"
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index c62b5d261345..b623bcaca76c 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -35,6 +35,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index c44602758120..ee7e57b752a7 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -20,7 +20,7 @@ static void __init vf610_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *vf610_dt_compat[] __initconst = {
+static const char * const vf610_dt_compat[] __initconst = {
         "fsl,vf610",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 872b3c6ba408..97836e94451c 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -34,6 +34,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
deleted file mode 100644
index 4c112021aa4e..000000000000
--- a/arch/arm/mach-imx/mm-imx5.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/of_address.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-
-/*
- * Define the MX51 memory map.
- */
-static struct map_desc mx51_io_desc[] __initdata = {
-        imx_map_entry(MX51, TZIC, MT_DEVICE),
-        imx_map_entry(MX51, IRAM, MT_DEVICE),
-        imx_map_entry(MX51, AIPS1, MT_DEVICE),
-        imx_map_entry(MX51, SPBA0, MT_DEVICE),
-        imx_map_entry(MX51, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX53 memory map.
- */
-static struct map_desc mx53_io_desc[] __initdata = {
-        imx_map_entry(MX53, TZIC, MT_DEVICE),
-        imx_map_entry(MX53, AIPS1, MT_DEVICE),
-        imx_map_entry(MX53, SPBA0, MT_DEVICE),
-        imx_map_entry(MX53, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx51_map_io(void)
-{
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
-}
-
-void __init mx53_map_io(void)
-{
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
-}
-
-/*
- * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
- * the Freescale marketing division. However this did not remove the
- * hardware from the chip which still needs to be configured for proper
- * IPU support.
- */
-static void __init imx51_ipu_mipi_setup(void)
-{
-        void __iomem *hsc_addr;
-        hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
-
-        /* setup MIPI module to legacy mode */
-        __raw_writel(0xf00, hsc_addr);
-
-        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
-        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
-                hsc_addr + 0x800);
-}
-
-void __init imx51_init_early(void)
-{
-        imx51_ipu_mipi_setup();
-        mxc_set_cpu_type(MXC_CPU_MX51);
-        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        imx_src_init();
-}
-
-void __init imx53_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX53);
-        imx_src_init();
-}
-
-void __init mx51_init_irq(void)
-{
-        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
-}
-
-void __init mx53_init_irq(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-
-        tzic_init_irq(base);
-}
-
-static struct sdma_platform_data imx51_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx51.bin",
-};
-
-static const struct resource imx51_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx51_soc_init(void)
-{
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        mxc_device_init();
-
-        /* i.mx51 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
-
-        pinctrl_provide_dummies();
-
-        /* i.mx51 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
-
-        /* i.mx51 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
-                                        ARRAY_SIZE(imx51_audmux_res));
-}
-
-void __init imx51_init_late(void)
-{
-        mx51_neon_fixup();
-        imx5_pm_init();
-}
-
-void __init imx53_init_late(void)
-{
-        imx5_pm_init();
-}
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
deleted file mode 100644
index fb38436ca67f..000000000000
--- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Exported ksyms of ARCH_MX1
- *
- * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <linux/platform_data/camera-mx1.h>
-
-/* IMX camera FIQ handler */
-EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
-EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
diff --git a/arch/arm/mach-imx/mx1-camera-fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
deleted file mode 100644
index 9c69aa65bf17..000000000000
--- a/arch/arm/mach-imx/mx1-camera-fiq.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- *  Based on linux/arch/arm/lib/floppydma.S
- *      Copyright (C) 1995, 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-                .text
-                .global mx1_camera_sof_fiq_end
-                .global mx1_camera_sof_fiq_start
-mx1_camera_sof_fiq_start:
-                @ enable dma
-                ldr     r12, [r9]
-                orr     r12, r12, #0x00000001
-                str     r12, [r9]
-                @ unmask DMA interrupt
-                ldr     r12, [r8]
-                bic     r12, r12, r13
-                str     r12, [r8]
-                @ disable SOF interrupt
-                ldr     r12, [r10]
-                bic     r12, r12, #0x00010000
-                str     r12, [r10]
-                @ clear SOF flag
-                mov     r12, #0x00010000
-                str     r12, [r11]
-                @ return from FIQ
-                subs    pc, lr, #4
-mx1_camera_sof_fiq_end:
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 52d5b1574721..1e91a0918e83 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -24,6 +24,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -213,10 +214,8 @@ static int __init devboard_usbh1_init(void)
         usbh1_pdata.otg = phy;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index a4f43e90f3c1..2e895a82a6eb 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -28,6 +28,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -327,10 +328,8 @@ static int __init marxbot_usbh1_init(void)
         usbh1_pdata.otg = phy;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 04ae45dbfaa7..89fc35a64448 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -28,6 +28,7 @@
 #include "board-mx31moboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -141,10 +142,8 @@ static int __init smartbot_otg_host_init(void)
                 return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 #else
 static inline int smartbot_otg_host_init(void) { return 0; }
diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h
deleted file mode 100644
index af844f76261a..000000000000
--- a/arch/arm/mach-imx/mx51.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __MACH_MX51_H__
-#define __MACH_MX51_H__
-
-/*
- * IROM
- */
-#define MX51_IROM_BASE_ADDR             0x0
-#define MX51_IROM_SIZE                  SZ_64K
-
-/*
- * IRAM
- */
-#define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
-#define MX51_IRAM_PARTITIONS            16
-#define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-#define MX51_GPU_BASE_ADDR              0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-
-/*
- * SPBA global module enabled #0
- */
-#define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_SIZE                 SZ_1M
-
-#define MX51_ESDHC1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x04000)
-#define MX51_ESDHC2_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x08000)
-#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_ECSPI1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x10000)
-#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x14000)
-#define MX51_ESDHC3_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x20000)
-#define MX51_ESDHC4_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x24000)
-#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x28000)
-#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x30000)
-#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x34000)
-#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x38000)
-#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR            0x73f00000
-#define MX51_AIPS1_SIZE                 SZ_1M
-
-#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
-#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
-#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
-#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
-#define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
-#define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
-#define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
-#define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
-#define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
-#define MX51_WDOG1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x98000)
-#define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
-#define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
-#define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
-#define MX51_IOMUXC_BASE_ADDR           (MX51_AIPS1_BASE_ADDR + 0xa8000)
-#define MX51_EPIT1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xac000)
-#define MX51_EPIT2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xb0000)
-#define MX51_PWM1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb4000)
-#define MX51_PWM2_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb8000)
-#define MX51_UART1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xbc000)
-#define MX51_UART2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xc0000)
-#define MX51_SRC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd0000)
-#define MX51_CCM_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd4000)
-#define MX51_GPC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd8000)
-
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR            0x83f00000
-#define MX51_AIPS2_SIZE                 SZ_1M
-
-#define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
-#define MX51_PLL2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x84000)
-#define MX51_PLL3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x88000)
-#define MX51_AHBMAX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0x94000)
-#define MX51_IIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x98000)
-#define MX51_CSU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x9c000)
-#define MX51_ARM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xa0000)
-#define MX51_OWIRE_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xa4000)
-#define MX51_FIRI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_ECSPI2_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xac000)
-#define MX51_SDMA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xb0000)
-#define MX51_SCC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xb4000)
-#define MX51_ROMCP_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xb8000)
-#define MX51_RTIC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc0000)
-#define MX51_I2C2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc4000)
-#define MX51_I2C1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc8000)
-#define MX51_SSI1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xcc000)
-#define MX51_AUDMUX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd0000)
-#define MX51_M4IF_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xd8000)
-#define MX51_ESDCTL_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd9000)
-#define MX51_WEIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xda000)
-#define MX51_NFC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdb000)
-#define MX51_EMI_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdbf00)
-#define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
-#define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
-#define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
-#define MX51_SSI3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe8000)
-#define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
-#define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
-#define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
-#define MX51_SAHARA_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xf8000)
-
-#define MX51_CSD0_BASE_ADDR             0x90000000
-#define MX51_CSD1_BASE_ADDR             0xa0000000
-#define MX51_CS0_BASE_ADDR              0xb0000000
-#define MX51_CS1_BASE_ADDR              0xb8000000
-#define MX51_CS2_BASE_ADDR              0xc0000000
-#define MX51_CS3_BASE_ADDR              0xc8000000
-#define MX51_CS4_BASE_ADDR              0xcc000000
-#define MX51_CS5_BASE_ADDR              0xce000000
-
-/*
- * NFC
- */
-#define MX51_NFC_AXI_BASE_ADDR          0xcfff0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE               SZ_64K
-
-#define MX51_GPU2D_BASE_ADDR            0xd0000000
-#define MX51_TZIC_BASE_ADDR             0xe0000000
-#define MX51_TZIC_SIZE                  SZ_16K
-
-#define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX51_SPBA_SDHC1 0x04
-#define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0c
-#define MX51_SPBA_CSPI1 0x10
-#define MX51_SPBA_SSI2  0x14
-#define MX51_SPBA_SDHC3 0x20
-#define MX51_SPBA_SDHC4 0x24
-#define MX51_SPBA_SPDIF 0x28
-#define MX51_SPBA_ATA   0x30
-#define MX51_SPBA_SLIM  0x34
-#define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL  0x3c
-
-/*
- * Defines for modules using static and dynamic DMA channels
- */
-#define MX51_MXC_DMA_CHANNEL_IRAM       30
-#define MX51_MXC_DMA_CHANNEL_SPDIF_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC1       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC2       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_RX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_TX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI2_RX    MXC_DMA_DYNAMIC_CHANNEL
-#ifdef CONFIG_SDMA_IRAM
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    (MX51_MXC_DMA_CHANNEL_IRAM + 1)
-#else                           /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    MXC_DMA_DYNAMIC_CHANNEL
-#endif                          /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_CSPI1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_RX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_TX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MEMORY     MXC_DMA_DYNAMIC_CHANNEL
-
-#define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
-
-/*
- * DMA request assignments
- */
-#define MX51_DMA_REQ_VPU                0
-#define MX51_DMA_REQ_GPC                1
-#define MX51_DMA_REQ_ATA_RX             2
-#define MX51_DMA_REQ_ATA_TX             3
-#define MX51_DMA_REQ_ATA_TX_END         4
-#define MX51_DMA_REQ_SLIM_B             5
-#define MX51_DMA_REQ_CSPI1_RX           6
-#define MX51_DMA_REQ_CSPI1_TX           7
-#define MX51_DMA_REQ_CSPI2_RX           8
-#define MX51_DMA_REQ_CSPI2_TX           9
-#define MX51_DMA_REQ_HS_I2C_TX          10
-#define MX51_DMA_REQ_HS_I2C_RX          11
-#define MX51_DMA_REQ_FIRI_RX            12
-#define MX51_DMA_REQ_FIRI_TX            13
-#define MX51_DMA_REQ_EXTREQ1            14
-#define MX51_DMA_REQ_GPU                15
-#define MX51_DMA_REQ_UART2_RX           16
-#define MX51_DMA_REQ_UART2_TX           17
-#define MX51_DMA_REQ_UART1_RX           18
-#define MX51_DMA_REQ_UART1_TX           19
-#define MX51_DMA_REQ_SDHC1              20
-#define MX51_DMA_REQ_SDHC2              21
-#define MX51_DMA_REQ_SSI2_RX1           22
-#define MX51_DMA_REQ_SSI2_TX1           23
-#define MX51_DMA_REQ_SSI2_RX0           24
-#define MX51_DMA_REQ_SSI2_TX0           25
-#define MX51_DMA_REQ_SSI1_RX1           26
-#define MX51_DMA_REQ_SSI1_TX1           27
-#define MX51_DMA_REQ_SSI1_RX0           28
-#define MX51_DMA_REQ_SSI1_TX0           29
-#define MX51_DMA_REQ_EMI_RD             30
-#define MX51_DMA_REQ_CTI2_0             31
-#define MX51_DMA_REQ_EMI_WR             32
-#define MX51_DMA_REQ_CTI2_1             33
-#define MX51_DMA_REQ_EPIT2              34
-#define MX51_DMA_REQ_SSI3_RX1           35
-#define MX51_DMA_REQ_IPU                36
-#define MX51_DMA_REQ_SSI3_TX1           37
-#define MX51_DMA_REQ_CSPI_RX            38
-#define MX51_DMA_REQ_CSPI_TX            39
-#define MX51_DMA_REQ_SDHC3              40
-#define MX51_DMA_REQ_SDHC4              41
-#define MX51_DMA_REQ_SLIM_B_TX          42
-#define MX51_DMA_REQ_UART3_RX           43
-#define MX51_DMA_REQ_UART3_TX           44
-#define MX51_DMA_REQ_SPDIF              45
-#define MX51_DMA_REQ_SSI3_RX0           46
-#define MX51_DMA_REQ_SSI3_TX0           47
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX51_INT_BASE                   (NR_IRQS_LEGACY + 0)
-#define MX51_INT_RESV0                  (NR_IRQS_LEGACY + 0)
-#define MX51_INT_ESDHC1                 (NR_IRQS_LEGACY + 1)
-#define MX51_INT_ESDHC2                 (NR_IRQS_LEGACY + 2)
-#define MX51_INT_ESDHC3                 (NR_IRQS_LEGACY + 3)
-#define MX51_INT_ESDHC4                 (NR_IRQS_LEGACY + 4)
-#define MX51_INT_RESV5                  (NR_IRQS_LEGACY + 5)
-#define MX51_INT_SDMA                   (NR_IRQS_LEGACY + 6)
-#define MX51_INT_IOMUX                  (NR_IRQS_LEGACY + 7)
-#define MX51_INT_NFC                    (NR_IRQS_LEGACY + 8)
-#define MX51_INT_VPU                    (NR_IRQS_LEGACY + 9)
-#define MX51_INT_IPU_ERR                (NR_IRQS_LEGACY + 10)
-#define MX51_INT_IPU_SYN                (NR_IRQS_LEGACY + 11)
-#define MX51_INT_GPU                    (NR_IRQS_LEGACY + 12)
-#define MX51_INT_RESV13                 (NR_IRQS_LEGACY + 13)
-#define MX51_INT_USB_HS1                (NR_IRQS_LEGACY + 14)
-#define MX51_INT_EMI                    (NR_IRQS_LEGACY + 15)
-#define MX51_INT_USB_HS2                (NR_IRQS_LEGACY + 16)
-#define MX51_INT_USB_HS3                (NR_IRQS_LEGACY + 17)
-#define MX51_INT_USB_OTG                (NR_IRQS_LEGACY + 18)
-#define MX51_INT_SAHARA_H0              (NR_IRQS_LEGACY + 19)
-#define MX51_INT_SAHARA_H1              (NR_IRQS_LEGACY + 20)
-#define MX51_INT_SCC_SMN                (NR_IRQS_LEGACY + 21)
-#define MX51_INT_SCC_STZ                (NR_IRQS_LEGACY + 22)
-#define MX51_INT_SCC_SCM                (NR_IRQS_LEGACY + 23)
-#define MX51_INT_SRTC_NTZ               (NR_IRQS_LEGACY + 24)
-#define MX51_INT_SRTC_TZ                (NR_IRQS_LEGACY + 25)
-#define MX51_INT_RTIC                   (NR_IRQS_LEGACY + 26)
-#define MX51_INT_CSU                    (NR_IRQS_LEGACY + 27)
-#define MX51_INT_SLIM_B                 (NR_IRQS_LEGACY + 28)
-#define MX51_INT_SSI1                   (NR_IRQS_LEGACY + 29)
-#define MX51_INT_SSI2                   (NR_IRQS_LEGACY + 30)
-#define MX51_INT_UART1                  (NR_IRQS_LEGACY + 31)
-#define MX51_INT_UART2                  (NR_IRQS_LEGACY + 32)
-#define MX51_INT_UART3                  (NR_IRQS_LEGACY + 33)
-#define MX51_INT_RESV34                 (NR_IRQS_LEGACY + 34)
-#define MX51_INT_RESV35                 (NR_IRQS_LEGACY + 35)
-#define MX51_INT_ECSPI1                 (NR_IRQS_LEGACY + 36)
-#define MX51_INT_ECSPI2                 (NR_IRQS_LEGACY + 37)
-#define MX51_INT_CSPI                   (NR_IRQS_LEGACY + 38)
-#define MX51_INT_GPT                    (NR_IRQS_LEGACY + 39)
-#define MX51_INT_EPIT1                  (NR_IRQS_LEGACY + 40)
-#define MX51_INT_EPIT2                  (NR_IRQS_LEGACY + 41)
-#define MX51_INT_GPIO1_INT7             (NR_IRQS_LEGACY + 42)
-#define MX51_INT_GPIO1_INT6             (NR_IRQS_LEGACY + 43)
-#define MX51_INT_GPIO1_INT5             (NR_IRQS_LEGACY + 44)
-#define MX51_INT_GPIO1_INT4             (NR_IRQS_LEGACY + 45)
-#define MX51_INT_GPIO1_INT3             (NR_IRQS_LEGACY + 46)
-#define MX51_INT_GPIO1_INT2             (NR_IRQS_LEGACY + 47)
-#define MX51_INT_GPIO1_INT1             (NR_IRQS_LEGACY + 48)
-#define MX51_INT_GPIO1_INT0             (NR_IRQS_LEGACY + 49)
-#define MX51_INT_GPIO1_LOW              (NR_IRQS_LEGACY + 50)
-#define MX51_INT_GPIO1_HIGH             (NR_IRQS_LEGACY + 51)
-#define MX51_INT_GPIO2_LOW              (NR_IRQS_LEGACY + 52)
-#define MX51_INT_GPIO2_HIGH             (NR_IRQS_LEGACY + 53)
-#define MX51_INT_GPIO3_LOW              (NR_IRQS_LEGACY + 54)
-#define MX51_INT_GPIO3_HIGH             (NR_IRQS_LEGACY + 55)
-#define MX51_INT_GPIO4_LOW              (NR_IRQS_LEGACY + 56)
-#define MX51_INT_GPIO4_HIGH             (NR_IRQS_LEGACY + 57)
-#define MX51_INT_WDOG1                  (NR_IRQS_LEGACY + 58)
-#define MX51_INT_WDOG2                  (NR_IRQS_LEGACY + 59)
-#define MX51_INT_KPP                    (NR_IRQS_LEGACY + 60)
-#define MX51_INT_PWM1                   (NR_IRQS_LEGACY + 61)
-#define MX51_INT_I2C1                   (NR_IRQS_LEGACY + 62)
-#define MX51_INT_I2C2                   (NR_IRQS_LEGACY + 63)
-#define MX51_INT_HS_I2C                 (NR_IRQS_LEGACY + 64)
-#define MX51_INT_RESV65                 (NR_IRQS_LEGACY + 65)
-#define MX51_INT_RESV66                 (NR_IRQS_LEGACY + 66)
-#define MX51_INT_SIM_IPB                (NR_IRQS_LEGACY + 67)
-#define MX51_INT_SIM_DAT                (NR_IRQS_LEGACY + 68)
-#define MX51_INT_IIM                    (NR_IRQS_LEGACY + 69)
-#define MX51_INT_ATA                    (NR_IRQS_LEGACY + 70)
-#define MX51_INT_CCM1                   (NR_IRQS_LEGACY + 71)
-#define MX51_INT_CCM2                   (NR_IRQS_LEGACY + 72)
-#define MX51_INT_GPC1                   (NR_IRQS_LEGACY + 73)
-#define MX51_INT_GPC2                   (NR_IRQS_LEGACY + 74)
-#define MX51_INT_SRC                    (NR_IRQS_LEGACY + 75)
-#define MX51_INT_NM                     (NR_IRQS_LEGACY + 76)
-#define MX51_INT_PMU                    (NR_IRQS_LEGACY + 77)
-#define MX51_INT_CTI_IRQ                (NR_IRQS_LEGACY + 78)
-#define MX51_INT_CTI1_TG0               (NR_IRQS_LEGACY + 79)
-#define MX51_INT_CTI1_TG1               (NR_IRQS_LEGACY + 80)
-#define MX51_INT_MCG_ERR                (NR_IRQS_LEGACY + 81)
-#define MX51_INT_MCG_TMR                (NR_IRQS_LEGACY + 82)
-#define MX51_INT_MCG_FUNC               (NR_IRQS_LEGACY + 83)
-#define MX51_INT_GPU2_IRQ               (NR_IRQS_LEGACY + 84)
-#define MX51_INT_GPU2_BUSY              (NR_IRQS_LEGACY + 85)
-#define MX51_INT_RESV86                 (NR_IRQS_LEGACY + 86)
-#define MX51_INT_FEC                    (NR_IRQS_LEGACY + 87)
-#define MX51_INT_OWIRE                  (NR_IRQS_LEGACY + 88)
-#define MX51_INT_CTI1_TG2               (NR_IRQS_LEGACY + 89)
-#define MX51_INT_SJC                    (NR_IRQS_LEGACY + 90)
-#define MX51_INT_SPDIF                  (NR_IRQS_LEGACY + 91)
-#define MX51_INT_TVE                    (NR_IRQS_LEGACY + 92)
-#define MX51_INT_FIRI                   (NR_IRQS_LEGACY + 93)
-#define MX51_INT_PWM2                   (NR_IRQS_LEGACY + 94)
-#define MX51_INT_SLIM_EXP               (NR_IRQS_LEGACY + 95)
-#define MX51_INT_SSI3                   (NR_IRQS_LEGACY + 96)
-#define MX51_INT_EMI_BOOT               (NR_IRQS_LEGACY + 97)
-#define MX51_INT_CTI1_TG3               (NR_IRQS_LEGACY + 98)
-#define MX51_INT_SMC_RX                 (NR_IRQS_LEGACY + 99)
-#define MX51_INT_VPU_IDLE               (NR_IRQS_LEGACY + 100)
-#define MX51_INT_EMI_NFC                (NR_IRQS_LEGACY + 101)
-#define MX51_INT_GPU_IDLE               (NR_IRQS_LEGACY + 102)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx51_revision(void);
-extern void mx51_display_revision(void);
-#endif
-
-#endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h
deleted file mode 100644
index f829d1c22501..000000000000
--- a/arch/arm/mach-imx/mx53.h
+++ /dev/null
@@ -1,342 +0,0 @@
-#ifndef __MACH_MX53_H__
-#define __MACH_MX53_H__
-
-/*
- * IROM
- */
-#define MX53_IROM_BASE_ADDR             0x0
-#define MX53_IROM_SIZE                  SZ_64K
-
-/* TZIC */
-#define MX53_TZIC_BASE_ADDR             0x0FFFC000
-#define MX53_TZIC_SIZE                  SZ_16K
-
-/*
- * AHCI SATA
- */
-#define MX53_SATA_BASE_ADDR             0x10000000
-
-/*
- * NFC
- */
-#define MX53_NFC_AXI_BASE_ADDR  0xF7FF0000      /* NAND flash AXI */
-#define MX53_NFC_AXI_SIZE               SZ_64K
-
-/*
- * IRAM
- */
-#define MX53_IRAM_BASE_ADDR     0xF8000000      /* internal ram */
-#define MX53_IRAM_PARTITIONS    16
-#define MX53_IRAM_SIZE          (MX53_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-/*
- * Graphics Memory of GPU
- */
-#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
-#define MX53_GPU2D_BASE_ADDR            0x20000000
-#define MX53_GPU_BASE_ADDR              0x30000000
-#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
-
-#define MX53_DEBUG_BASE_ADDR            0x40000000
-#define MX53_DEBUG_SIZE         SZ_1M
-#define MX53_ETB_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00001000)
-#define MX53_ETM_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00002000)
-#define MX53_TPIU_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00003000)
-#define MX53_CTI0_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00004000)
-#define MX53_CTI1_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00005000)
-#define MX53_CTI2_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00006000)
-#define MX53_CTI3_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00007000)
-#define MX53_CORTEX_DBG_BASE_ADDR       (MX53_DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX53_SPBA0_BASE_ADDR            0x50000000
-#define MX53_SPBA0_SIZE         SZ_1M
-
-#define MX53_ESDHC1_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_ESDHC2_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00008000)
-#define MX53_UART3_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_ECSPI1_BASE_ADDR           (MX53_SPBA0_BASE_ADDR + 0x00010000)
-#define MX53_SSI2_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_ESDHC3_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_ESDHC4_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00024000)
-#define MX53_SPDIF_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00028000)
-#define MX53_ASRC_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x0002C000)
-#define MX53_ATA_DMA_BASE_ADDR  (MX53_SPBA0_BASE_ADDR + 0x00030000)
-#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
-#define MX53_HSI2C_DMA_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00038000)
-#define MX53_SPBA_CTRL_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX53_AIPS1_BASE_ADDR    0x53F00000
-#define MX53_AIPS1_SIZE         SZ_1M
-
-#define MX53_OTG_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00080000)
-#define MX53_GPIO1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00084000)
-#define MX53_GPIO2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00088000)
-#define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
-#define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00098000)
-#define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX53_IOMUXC_BASE_ADDR   (MX53_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX53_EPIT1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX53_EPIT2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX53_PWM1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX53_PWM2_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX53_UART1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX53_UART2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX53_SRC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX53_CCM_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX53_GPC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX53_GPIO5_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX53_GPIO6_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX53_GPIO7_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E4000)
-#define MX53_ATA_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000E8000)
-#define MX53_I2C3_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX53_UART4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX53_AIPS2_BASE_ADDR            0x63F00000
-#define MX53_AIPS2_SIZE                 SZ_1M
-
-#define MX53_PLL1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00080000)
-#define MX53_PLL2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00084000)
-#define MX53_PLL3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00088000)
-#define MX53_PLL4_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x0008C000)
-#define MX53_UART5_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x00090000)
-#define MX53_AHBMAX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x00094000)
-#define MX53_IIM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x00098000)
-#define MX53_CSU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX53_ARM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX53_OWIRE_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX53_FIRI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_ECSPI2_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX53_SDMA_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX53_SCC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX53_ROMCP_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX53_RTIC_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX53_I2C2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX53_I2C1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX53_SSI1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX53_AUDMUX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX53_RTC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000D4000)
-#define MX53_M4IF_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX53_ESDCTL_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX53_WEIM_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX53_NFC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX53_EMI_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX53_MLB_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX53_SSI3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_FEC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX53_TVE_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX53_VPU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX53_SAHARA_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000F8000)
-#define MX53_PTP_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000FC000)
-
-/*
- * Memory regions and CS
- */
-#define MX53_CSD0_BASE_ADDR             0x70000000
-#define MX53_CSD1_BASE_ADDR             0xB0000000
-#define MX53_CS0_BASE_ADDR              0xF0000000
-#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
-#define MX53_CS1_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_96MB_BASE_ADDR         0xF6000000
-#define MX53_CS3_BASE_ADDR              0xF6000000
-
-#define MX53_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX53_IO_ADDRESS(x)              IOMEM(MX53_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX53_SPBA_SDHC1 0x04
-#define MX53_SPBA_SDHC2 0x08
-#define MX53_SPBA_UART3 0x0C
-#define MX53_SPBA_CSPI1 0x10
-#define MX53_SPBA_SSI2          0x14
-#define MX53_SPBA_SDHC3 0x20
-#define MX53_SPBA_SDHC4 0x24
-#define MX53_SPBA_SPDIF 0x28
-#define MX53_SPBA_ATA           0x30
-#define MX53_SPBA_SLIM          0x34
-#define MX53_SPBA_HSI2C 0x38
-#define MX53_SPBA_CTRL          0x3C
-
-/*
- * DMA request assignments
- */
-#define MX53_DMA_REQ_SSI3_TX0           47
-#define MX53_DMA_REQ_SSI3_RX0           46
-#define MX53_DMA_REQ_SSI3_TX1           45
-#define MX53_DMA_REQ_SSI3_RX1           44
-#define MX53_DMA_REQ_UART3_TX   43
-#define MX53_DMA_REQ_UART3_RX   42
-#define MX53_DMA_REQ_ESAI_TX            41
-#define MX53_DMA_REQ_ESAI_RX            40
-#define MX53_DMA_REQ_CSPI_TX            39
-#define MX53_DMA_REQ_CSPI_RX            38
-#define MX53_DMA_REQ_ASRC_DMA6  37
-#define MX53_DMA_REQ_ASRC_DMA5  36
-#define MX53_DMA_REQ_ASRC_DMA4  35
-#define MX53_DMA_REQ_ASRC_DMA3  34
-#define MX53_DMA_REQ_ASRC_DMA2  33
-#define MX53_DMA_REQ_ASRC_DMA1  32
-#define MX53_DMA_REQ_EMI_WR             31
-#define MX53_DMA_REQ_EMI_RD             30
-#define MX53_DMA_REQ_SSI1_TX0           29
-#define MX53_DMA_REQ_SSI1_RX0           28
-#define MX53_DMA_REQ_SSI1_TX1           27
-#define MX53_DMA_REQ_SSI1_RX1           26
-#define MX53_DMA_REQ_SSI2_TX0           25
-#define MX53_DMA_REQ_SSI2_RX0           24
-#define MX53_DMA_REQ_SSI2_TX1           23
-#define MX53_DMA_REQ_SSI2_RX1           22
-#define MX53_DMA_REQ_I2C2_SDHC2 21
-#define MX53_DMA_REQ_I2C1_SDHC1 20
-#define MX53_DMA_REQ_UART1_TX   19
-#define MX53_DMA_REQ_UART1_RX   18
-#define MX53_DMA_REQ_UART5_TX   17
-#define MX53_DMA_REQ_UART5_RX   16
-#define MX53_DMA_REQ_SPDIF_TX           15
-#define MX53_DMA_REQ_SPDIF_RX           14
-#define MX53_DMA_REQ_UART2_FIRI_TX      13
-#define MX53_DMA_REQ_UART2_FIRI_RX      12
-#define MX53_DMA_REQ_SDHC4              11
-#define MX53_DMA_REQ_I2C3_SDHC3 10
-#define MX53_DMA_REQ_CSPI2_TX           9
-#define MX53_DMA_REQ_CSPI2_RX           8
-#define MX53_DMA_REQ_CSPI1_TX           7
-#define MX53_DMA_REQ_CSPI1_RX           6
-#define MX53_DMA_REQ_IPU                5
-#define MX53_DMA_REQ_ATA_TX_END 4
-#define MX53_DMA_REQ_ATA_UART4_TX       3
-#define MX53_DMA_REQ_ATA_UART4_RX       2
-#define MX53_DMA_REQ_GPC                1
-#define MX53_DMA_REQ_VPU                0
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX53_INT_RESV0          (NR_IRQS_LEGACY + 0)
-#define MX53_INT_ESDHC1         (NR_IRQS_LEGACY + 1)
-#define MX53_INT_ESDHC2         (NR_IRQS_LEGACY + 2)
-#define MX53_INT_ESDHC3         (NR_IRQS_LEGACY + 3)
-#define MX53_INT_ESDHC4         (NR_IRQS_LEGACY + 4)
-#define MX53_INT_DAP            (NR_IRQS_LEGACY + 5)
-#define MX53_INT_SDMA           (NR_IRQS_LEGACY + 6)
-#define MX53_INT_IOMUX          (NR_IRQS_LEGACY + 7)
-#define MX53_INT_NFC            (NR_IRQS_LEGACY + 8)
-#define MX53_INT_VPU            (NR_IRQS_LEGACY + 9)
-#define MX53_INT_IPU_ERR        (NR_IRQS_LEGACY + 10)
-#define MX53_INT_IPU_SYN        (NR_IRQS_LEGACY + 11)
-#define MX53_INT_GPU            (NR_IRQS_LEGACY + 12)
-#define MX53_INT_UART4          (NR_IRQS_LEGACY + 13)
-#define MX53_INT_USB_H1         (NR_IRQS_LEGACY + 14)
-#define MX53_INT_EMI            (NR_IRQS_LEGACY + 15)
-#define MX53_INT_USB_H2         (NR_IRQS_LEGACY + 16)
-#define MX53_INT_USB_H3         (NR_IRQS_LEGACY + 17)
-#define MX53_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
-#define MX53_INT_SAHARA_H0      (NR_IRQS_LEGACY + 19)
-#define MX53_INT_SAHARA_H1      (NR_IRQS_LEGACY + 20)
-#define MX53_INT_SCC_SMN        (NR_IRQS_LEGACY + 21)
-#define MX53_INT_SCC_STZ        (NR_IRQS_LEGACY + 22)
-#define MX53_INT_SCC_SCM        (NR_IRQS_LEGACY + 23)
-#define MX53_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
-#define MX53_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
-#define MX53_INT_RTIC           (NR_IRQS_LEGACY + 26)
-#define MX53_INT_CSU            (NR_IRQS_LEGACY + 27)
-#define MX53_INT_SATA           (NR_IRQS_LEGACY + 28)
-#define MX53_INT_SSI1           (NR_IRQS_LEGACY + 29)
-#define MX53_INT_SSI2           (NR_IRQS_LEGACY + 30)
-#define MX53_INT_UART1          (NR_IRQS_LEGACY + 31)
-#define MX53_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX53_INT_UART3          (NR_IRQS_LEGACY + 33)
-#define MX53_INT_RTC            (NR_IRQS_LEGACY + 34)
-#define MX53_INT_PTP            (NR_IRQS_LEGACY + 35)
-#define MX53_INT_ECSPI1         (NR_IRQS_LEGACY + 36)
-#define MX53_INT_ECSPI2         (NR_IRQS_LEGACY + 37)
-#define MX53_INT_CSPI           (NR_IRQS_LEGACY + 38)
-#define MX53_INT_GPT            (NR_IRQS_LEGACY + 39)
-#define MX53_INT_EPIT1          (NR_IRQS_LEGACY + 40)
-#define MX53_INT_EPIT2          (NR_IRQS_LEGACY + 41)
-#define MX53_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
-#define MX53_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
-#define MX53_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
-#define MX53_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
-#define MX53_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
-#define MX53_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
-#define MX53_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
-#define MX53_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
-#define MX53_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
-#define MX53_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
-#define MX53_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
-#define MX53_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
-#define MX53_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
-#define MX53_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
-#define MX53_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
-#define MX53_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
-#define MX53_INT_WDOG1          (NR_IRQS_LEGACY + 58)
-#define MX53_INT_WDOG2          (NR_IRQS_LEGACY + 59)
-#define MX53_INT_KPP            (NR_IRQS_LEGACY + 60)
-#define MX53_INT_PWM1           (NR_IRQS_LEGACY + 61)
-#define MX53_INT_I2C1           (NR_IRQS_LEGACY + 62)
-#define MX53_INT_I2C2           (NR_IRQS_LEGACY + 63)
-#define MX53_INT_I2C3           (NR_IRQS_LEGACY + 64)
-#define MX53_INT_MLB            (NR_IRQS_LEGACY + 65)
-#define MX53_INT_ASRC           (NR_IRQS_LEGACY + 66)
-#define MX53_INT_SPDIF          (NR_IRQS_LEGACY + 67)
-#define MX53_INT_SIM_DAT        (NR_IRQS_LEGACY + 68)
-#define MX53_INT_IIM            (NR_IRQS_LEGACY + 69)
-#define MX53_INT_ATA            (NR_IRQS_LEGACY + 70)
-#define MX53_INT_CCM1           (NR_IRQS_LEGACY + 71)
-#define MX53_INT_CCM2           (NR_IRQS_LEGACY + 72)
-#define MX53_INT_GPC1           (NR_IRQS_LEGACY + 73)
-#define MX53_INT_GPC2           (NR_IRQS_LEGACY + 74)
-#define MX53_INT_SRC            (NR_IRQS_LEGACY + 75)
-#define MX53_INT_NM             (NR_IRQS_LEGACY + 76)
-#define MX53_INT_PMU            (NR_IRQS_LEGACY + 77)
-#define MX53_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
-#define MX53_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
-#define MX53_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
-#define MX53_INT_ESAI           (NR_IRQS_LEGACY + 81)
-#define MX53_INT_CAN1           (NR_IRQS_LEGACY + 82)
-#define MX53_INT_CAN2           (NR_IRQS_LEGACY + 83)
-#define MX53_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
-#define MX53_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
-#define MX53_INT_UART5          (NR_IRQS_LEGACY + 86)
-#define MX53_INT_FEC            (NR_IRQS_LEGACY + 87)
-#define MX53_INT_OWIRE          (NR_IRQS_LEGACY + 88)
-#define MX53_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
-#define MX53_INT_SJC            (NR_IRQS_LEGACY + 90)
-#define MX53_INT_TVE            (NR_IRQS_LEGACY + 92)
-#define MX53_INT_FIRI           (NR_IRQS_LEGACY + 93)
-#define MX53_INT_PWM2           (NR_IRQS_LEGACY + 94)
-#define MX53_INT_SLIM_EXP       (NR_IRQS_LEGACY + 95)
-#define MX53_INT_SSI3           (NR_IRQS_LEGACY + 96)
-#define MX53_INT_EMI_BOOT       (NR_IRQS_LEGACY + 97)
-#define MX53_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
-#define MX53_INT_SMC_RX         (NR_IRQS_LEGACY + 99)
-#define MX53_INT_VPU_IDLE       (NR_IRQS_LEGACY + 100)
-#define MX53_INT_EMI_NFC        (NR_IRQS_LEGACY + 101)
-#define MX53_INT_GPU_IDLE       (NR_IRQS_LEGACY + 102)
-#define MX53_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
-#define MX53_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
-#define MX53_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
-#define MX53_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
-#define MX53_INT_GPIO7_LOW      (NR_IRQS_LEGACY + 107)
-#define MX53_INT_GPIO7_HIGH     (NR_IRQS_LEGACY + 108)
-
-#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 75d6a37e1ae4..a39b69ef4301 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -154,10 +154,17 @@ extern unsigned int __mxc_cpu_type;
 #endif
 
 #ifndef __ASSEMBLY__
+#ifdef CONFIG_SOC_IMX6SL
 static inline bool cpu_is_imx6sl(void)
 {
         return __mxc_cpu_type == MXC_CPU_IMX6SL;
 }
+#else
+static inline bool cpu_is_imx6sl(void)
+{
+        return false;
+}
+#endif
 
 static inline bool cpu_is_imx6dl(void)
 {
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 58aeaf5baaf6..f1f80ab73e69 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -19,9 +19,26 @@
 
 #include "common.h"
 #include "cpuidle.h"
-#include "crm-regs-imx5.h"
 #include "hardware.h"
 
+#define MXC_CCM_CLPCR                   0x54
+#define MXC_CCM_CLPCR_LPM_OFFSET        0
+#define MXC_CCM_CLPCR_LPM_MASK          0x3
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
+#define MXC_CCM_CLPCR_VSTBY             (0x1 << 8)
+#define MXC_CCM_CLPCR_SBYOS             (0x1 << 6)
+
+#define MXC_CORTEXA8_PLAT_LPC           0xc
+#define MXC_CORTEXA8_PLAT_LPC_DSM       (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM   (1 << 1)
+
+#define MXC_SRPG_NEON_SRPGCR            0x280
+#define MXC_SRPG_ARM_SRPGCR             0x2a0
+#define MXC_SRPG_EMPGC0_SRPGCR          0x2c0
+#define MXC_SRPG_EMPGC1_SRPGCR          0x2d0
+
+#define MXC_SRPGCR_PCR                  1
+
 /*
  * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
  * This is also the lowest power state possible without affecting
@@ -32,6 +49,30 @@
  */
 #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
 
+struct imx5_pm_data {
+        phys_addr_t cortex_addr;
+        phys_addr_t gpc_addr;
+};
+
+static const struct imx5_pm_data imx51_pm_data __initconst = {
+        .cortex_addr = 0x83fa0000,
+        .gpc_addr = 0x73fd8000,
+};
+
+static const struct imx5_pm_data imx53_pm_data __initconst = {
+        .cortex_addr = 0x63fa0000,
+        .gpc_addr = 0x53fd8000,
+};
+
+static void __iomem *ccm_base;
+static void __iomem *cortex_base;
+static void __iomem *gpc_base;
+
+void __init imx5_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+
 /*
  * set cpu low power mode before WFI instruction. This function is called
  * mx5 because it can be used for mx51, and mx53.
@@ -43,12 +84,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
         int stop_mode = 0;
 
         /* always allow platform to issue a deep sleep mode request */
-        plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+        plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
             ~(MXC_CORTEXA8_PLAT_LPC_DSM);
-        ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
-        arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+        ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
+                    ~(MXC_CCM_CLPCR_LPM_MASK);
+        arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
+                     ~(MXC_SRPGCR_PCR);
+        empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
+                 ~(MXC_SRPGCR_PCR);
+        empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
+                 ~(MXC_SRPGCR_PCR);
 
         switch (mode) {
         case WAIT_CLOCKED:
@@ -82,17 +127,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                 return;
         }
 
-        __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
-        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
-        __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-        __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+        __raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
+        __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
+        __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
+        __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
 
         if (stop_mode) {
                 empgc0 |= MXC_SRPGCR_PCR;
                 empgc1 |= MXC_SRPGCR_PCR;
 
-                __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
+                __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
         }
 }
 
@@ -114,8 +159,8 @@ static int mx5_suspend_enter(suspend_state_t state)
                 flush_cache_all();
 
                 /*clear the EMPGC0/1 bits */
-                __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+                __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
         }
         cpu_do_idle();
 
@@ -149,7 +194,7 @@ static void imx5_pm_idle(void)
         imx5_cpu_do_idle();
 }
 
-static int __init imx5_pm_common_init(void)
+static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
 {
         int ret;
         struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
@@ -163,15 +208,28 @@ static int __init imx5_pm_common_init(void)
 
         arm_pm_idle = imx5_pm_idle;
 
+        cortex_base = ioremap(data->cortex_addr, SZ_16K);
+        gpc_base = ioremap(data->gpc_addr, SZ_16K);
+        WARN_ON(!ccm_base || !cortex_base || !gpc_base);
+
         /* Set the registers to the default cpu idle state. */
         mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
 
-        return imx5_cpuidle_init();
+        ret = imx5_cpuidle_init();
+        if (ret)
+                pr_warn("%s: cpuidle init failed %d\n", __func__, ret);
+
+        suspend_set_ops(&mx5_suspend_ops);
+
+        return 0;
+}
+
+void __init imx51_pm_init(void)
+{
+        imx5_pm_common_init(&imx51_pm_data);
 }
 
-void __init imx5_pm_init(void)
+void __init imx53_pm_init(void)
 {
-        int ret = imx5_pm_common_init();
-        if (!ret)
-                suspend_set_ops(&mx5_suspend_ops);
+        imx5_pm_common_init(&imx53_pm_data);
 }
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 9392a8f4ef24..5c3af8f993d0 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -129,6 +129,14 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = {
         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 };
 
+static const u32 imx6sx_mmdc_io_offset[] __initconst = {
+        0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
+        0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
+        0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+        0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
+};
+
 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
         .cpu_type = MXC_CPU_IMX6Q,
         .mmdc_compat = "fsl,imx6q-mmdc",
@@ -159,6 +167,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 };
 
+static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6SX,
+        .mmdc_compat = "fsl,imx6sx-mmdc",
+        .src_compat = "fsl,imx6sx-src",
+        .iomuxc_compat = "fsl,imx6sx-iomuxc",
+        .gpc_compat = "fsl,imx6sx-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
+        .mmdc_io_offset = imx6sx_mmdc_io_offset,
+};
+
 /*
  * This structure is for passing necessary data for low level ocram
  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@@ -181,11 +199,13 @@ struct imx6_cpu_pm_info {
         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 } __aligned(8);
 
-void imx6q_set_int_mem_clk_lpm(void)
+void imx6q_set_int_mem_clk_lpm(bool enable)
 {
         u32 val = readl_relaxed(ccm_base + CGPR);
 
-        val |= BM_CGPR_INT_MEM_CLK_LPM;
+        val &= ~BM_CGPR_INT_MEM_CLK_LPM;
+        if (enable)
+                val |= BM_CGPR_INT_MEM_CLK_LPM;
         writel_relaxed(val, ccm_base + CGPR);
 }
 
@@ -254,6 +274,14 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                 break;
         case STOP_POWER_ON:
                 val |= 0x2 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl())
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                if (cpu_is_imx6sl() || cpu_is_imx6sx())
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                else
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
                 break;
         case WAIT_UNCLOCKED_POWER_OFF:
                 val |= 0x1 << BP_CLPCR_LPM;
@@ -265,12 +293,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
                 val |= BM_CLPCR_VSTBY;
                 val |= BM_CLPCR_SBYOS;
-                if (cpu_is_imx6sl()) {
+                if (cpu_is_imx6sl())
                         val |= BM_CLPCR_BYPASS_PMIC_READY;
+                if (cpu_is_imx6sl() || cpu_is_imx6sx())
                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-                } else {
+                else
                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-                }
                 break;
         default:
                 return -EINVAL;
@@ -314,8 +342,22 @@ static int imx6q_suspend_finish(unsigned long val)
 static int imx6q_pm_enter(suspend_state_t state)
 {
         switch (state) {
+        case PM_SUSPEND_STANDBY:
+                imx6q_set_lpm(STOP_POWER_ON);
+                imx6q_set_int_mem_clk_lpm(true);
+                imx_gpc_pre_suspend(false);
+                if (cpu_is_imx6sl())
+                        imx6sl_set_wait_clk(true);
+                /* Zzz ... */
+                cpu_do_idle();
+                if (cpu_is_imx6sl())
+                        imx6sl_set_wait_clk(false);
+                imx_gpc_post_resume();
+                imx6q_set_lpm(WAIT_CLOCKED);
+                break;
         case PM_SUSPEND_MEM:
                 imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_set_int_mem_clk_lpm(false);
                 imx6q_enable_wb(true);
                 /*
                  * For suspend into ocram, asm code already take care of
@@ -323,7 +365,7 @@ static int imx6q_pm_enter(suspend_state_t state)
                  */
                 if (!imx6_suspend_in_ocram_fn)
                         imx6q_enable_rbc(true);
-                imx_gpc_pre_suspend();
+                imx_gpc_pre_suspend(true);
                 imx_anatop_pre_suspend();
                 imx_set_cpu_jump(0, v7_cpu_resume);
                 /* Zzz ... */
@@ -334,6 +376,7 @@ static int imx6q_pm_enter(suspend_state_t state)
                 imx_gpc_post_resume();
                 imx6q_enable_rbc(false);
                 imx6q_enable_wb(false);
+                imx6q_set_int_mem_clk_lpm(true);
                 imx6q_set_lpm(WAIT_CLOCKED);
                 break;
         default:
@@ -343,9 +386,14 @@ static int imx6q_pm_enter(suspend_state_t state)
         return 0;
 }
 
+static int imx6q_pm_valid(suspend_state_t state)
+{
+        return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
+}
+
 static const struct platform_suspend_ops imx6q_pm_ops = {
         .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
+        .valid = imx6q_pm_valid,
 };
 
 void __init imx6q_pm_set_ccm_base(void __iomem *base)
@@ -549,3 +597,8 @@ void __init imx6sl_pm_init(void)
 {
         imx6_pm_common_init(&imx6sl_pm_data);
 }
+
+void __init imx6sx_pm_init(void)
+{
+        imx6_pm_common_init(&imx6sx_pm_data);
+}
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 3b0733edb68c..d14c33fd6b03 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -42,7 +42,10 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
-        if (wdog_clk)
+        if (!wdog_base)
+                goto reset_fallback;
+
+        if (!IS_ERR(wdog_clk))
                 clk_enable(wdog_clk);
 
         if (cpu_is_mx1())
@@ -70,6 +73,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
         /* delay to allow the serial port to show the message */
         mdelay(50);
 
+reset_fallback:
         /* we'll take a jump through zero as a poor second */
         soft_restart(0);
 }
@@ -79,13 +83,10 @@ void __init mxc_arch_reset_init(void __iomem *base)
         wdog_base = base;
 
         wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
-        if (IS_ERR(wdog_clk)) {
+        if (IS_ERR(wdog_clk))
                 pr_warn("%s: failed to get wdog clock\n", __func__);
-                wdog_clk = NULL;
-                return;
-        }
-
-        clk_prepare(wdog_clk);
+        else
+                clk_prepare(wdog_clk);
 }
 
 void __init mxc_arch_reset_init_dt(void)
@@ -97,13 +98,10 @@ void __init mxc_arch_reset_init_dt(void)
         WARN_ON(!wdog_base);
 
         wdog_clk = of_clk_get(np, 0);
-        if (IS_ERR(wdog_clk)) {
+        if (IS_ERR(wdog_clk))
                 pr_warn("%s: failed to get wdog clock\n", __func__);
-                wdog_clk = NULL;
-                return;
-        }
-
-        clk_prepare(wdog_clk);
+        else
+                clk_prepare(wdog_clk);
 }
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bed081e58262..bf92e5a351c0 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxc_timer_init(void __iomem *base, int irq)
+static void __init _mxc_timer_init(int irq,
+                                   struct clk *clk_per, struct clk *clk_ipg)
 {
         uint32_t tctl_val;
-        struct clk *timer_clk;
-        struct clk *timer_ipg_clk;
 
-        timer_clk = clk_get_sys("imx-gpt.0", "per");
-        if (IS_ERR(timer_clk)) {
+        if (IS_ERR(clk_per)) {
                 pr_err("i.MX timer: unable to get clk\n");
                 return;
         }
 
-        timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
-        if (!IS_ERR(timer_ipg_clk))
-                clk_prepare_enable(timer_ipg_clk);
-
-        clk_prepare_enable(timer_clk);
+        if (!IS_ERR(clk_ipg))
+                clk_prepare_enable(clk_ipg);
 
-        timer_base = base;
+        clk_prepare_enable(clk_per);
 
         /*
          * Initialise to a known state (all timers off, and timing reset)
@@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq)
         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 
         /* init and register the timer to the framework */
-        mxc_clocksource_init(timer_clk);
-        mxc_clockevent_init(timer_clk);
+        mxc_clocksource_init(clk_per);
+        mxc_clockevent_init(clk_per);
 
         /* Make irqs happen */
         setup_irq(irq, &mxc_timer_irq);
 }
 
-void __init mxc_timer_init_dt(struct device_node *np)
+void __init mxc_timer_init(void __iomem *base, int irq)
 {
-        void __iomem *base;
+        struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
+        struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
+
+        timer_base = base;
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
+}
+
+static void __init mxc_timer_init_dt(struct device_node *np)
+{
+        struct clk *clk_per, *clk_ipg;
         int irq;
 
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
+        if (timer_base)
+                return;
+
+        timer_base = of_iomap(np, 0);
+        WARN_ON(!timer_base);
         irq = irq_of_parse_and_map(np, 0);
 
-        mxc_timer_init(base, irq);
+        clk_per = of_clk_get_by_name(np, "per");
+        clk_ipg = of_clk_get_by_name(np, "ipg");
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
 }
+CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 7828af4b2022..1d4f384ca773 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
@@ -153,13 +154,16 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
  */
-void __init tzic_init_irq(void __iomem *irqbase)
+void __init tzic_init_irq(void)
 {
         struct device_node *np;
         int irq_base;
         int i;
 
-        tzic_base = irqbase;
+        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
+        tzic_base = of_iomap(np, 0);
+        WARN_ON(!tzic_base);
+
         /* put the TZIC into the reset value with
          * all interrupts disabled
          */
@@ -181,7 +185,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
         irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
         WARN_ON(irq_base < 0);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
         domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
                                        &irq_domain_simple_ops, NULL);
         WARN_ON(!domain);
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 660ca6feff40..8ca290b479b1 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,7 +31,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/irqchip/versatile-fpga.h>
+#include <linux/irqchip.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
@@ -439,15 +439,10 @@ static void __init ap_of_timer_init(void)
         integrator_clockevent_init(rate, base, irq);
 }
 
-static const struct of_device_id fpga_irq_of_match[] __initconst = {
-        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
-        { /* Sentinel */ }
-};
-
 static void __init ap_init_irq_of(void)
 {
         cm_init();
-        of_irq_init(fpga_irq_of_match);
+        irqchip_init();
 }
 
 /* For the Device Tree, add in the UART callbacks as AUXDATA */
@@ -558,7 +553,6 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
         .map_io         = ap_map_io,
         .init_early     = ap_init_early,
         .init_irq       = ap_init_irq_of,
-        .handle_irq     = fpga_handle_irq,
         .init_time      = ap_of_timer_init,
         .init_machine   = ap_init_of,
         .restart        = integrator_restart,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index e39097068cf9..cca02eb75eb5 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -21,7 +21,7 @@
 #include <linux/platform_data/video-clcd-versatile.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
-#include <linux/irqchip/versatile-fpga.h>
+#include <linux/irqchip.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/of_irq.h>
@@ -234,15 +234,10 @@ static void __init intcp_init_early(void)
         sched_clock_register(intcp_read_sched_clock, 32, 24000000);
 }
 
-static const struct of_device_id fpga_irq_of_match[] __initconst = {
-        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
-        { /* Sentinel */ }
-};
-
 static void __init intcp_init_irq_of(void)
 {
         cm_init();
-        of_irq_init(fpga_irq_of_match);
+        irqchip_init();
 }
 
 /*
@@ -328,7 +323,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .map_io         = intcp_map_io,
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq_of,
-        .handle_irq     = fpga_handle_irq,
         .init_machine   = intcp_init_of,
         .restart        = integrator_restart,
         .dt_compat      = intcp_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
deleted file mode 100644
index df4b26340ae4..000000000000
--- a/arch/arm/mach-kirkwood/Kconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-if ARCH_KIRKWOOD
-
-menu "Marvell Kirkwood Implementations"
-
-config KIRKWOOD_LEGACY
-        bool
-
-config MACH_D2NET_V2
-        bool "LaCie d2 Network v2 NAS Board"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie d2 Network v2 NAS.
-
-config MACH_NET2BIG_V2
-        bool "LaCie 2Big Network v2 NAS Board"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie 2Big Network v2 NAS.
-
-config MACH_NET5BIG_V2
-        bool "LaCie 5Big Network v2 NAS Board"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie 5Big Network v2 NAS.
-
-config MACH_OPENRD
-        select KIRKWOOD_LEGACY
-        bool
-
-config MACH_OPENRD_BASE
-        bool "Marvell OpenRD Base Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Base Board.
-
-config MACH_OPENRD_CLIENT
-        bool "Marvell OpenRD Client Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Client Board.
-
-config MACH_OPENRD_ULTIMATE
-        bool "Marvell OpenRD Ultimate Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Ultimate Board.
-
-config MACH_RD88F6192_NAS
-        bool "Marvell RD-88F6192-NAS Reference Board"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6192-NAS Reference Board.
-
-config MACH_RD88F6281
-        bool "Marvell RD-88F6281 Reference Board"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6281 Reference Board.
-
-config MACH_T5325
-        bool "HP t5325 Thin Client"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          HP t5325 Thin Client.
-
-config MACH_TS219
-        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
-          TS-219P+ Turbo NAS devices.
-
-config MACH_TS41X
-        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
-        select KIRKWOOD_LEGACY
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
-          NAS devices.
-
-comment "Device tree entries"
-
-config ARCH_KIRKWOOD_DT
-        bool "Marvell Kirkwood Flattened Device Tree"
-        select KIRKWOOD_CLK
-        select OF_IRQ
-        select ORION_IRQCHIP
-        select ORION_TIMER
-        select POWER_SUPPLY
-        select POWER_RESET
-        select POWER_RESET_GPIO
-        select REGULATOR
-        select REGULATOR_FIXED_VOLTAGE
-        select USE_OF
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell Kirkwood using flattened device tree.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
deleted file mode 100644
index 3a72c5c6e747..000000000000
--- a/arch/arm/mach-kirkwood/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o common.o pcie.o
-obj-$(CONFIG_PM)                += pm.o
-
-obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
-obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
-obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
-obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
-
-obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
deleted file mode 100644
index 760a0efe7580..000000000000
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y   += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
deleted file mode 100644
index ff18ff20f71f..000000000000
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
- *
- * arch/arm/mach-kirkwood/board-dt.c
- *
- * Flattened Device Tree board initialization
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_net.h>
-#include <linux/of_platform.h>
-#include <linux/dma-mapping.h>
-#include <linux/irqchip.h>
-#include <asm/hardware/cache-feroceon-l2.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/bridge-regs.h>
-#include <plat/common.h>
-#include <plat/pcie.h>
-#include "pm.h"
-
-static struct map_desc kirkwood_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
-                .length         = KIRKWOOD_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-static void __init kirkwood_map_io(void)
-{
-        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
-}
-
-static struct resource kirkwood_cpufreq_resources[] = {
-        [0] = {
-                .start  = CPU_CONTROL_PHYS,
-                .end    = CPU_CONTROL_PHYS + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_cpufreq_device = {
-        .name           = "kirkwood-cpufreq",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
-        .resource       = kirkwood_cpufreq_resources,
-};
-
-static void __init kirkwood_cpufreq_init(void)
-{
-        platform_device_register(&kirkwood_cpufreq_device);
-}
-
-static struct resource kirkwood_cpuidle_resource[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-                .start  = DDR_OPERATION_BASE,
-                .end    = DDR_OPERATION_BASE + 3,
-        },
-};
-
-static struct platform_device kirkwood_cpuidle = {
-        .name           = "kirkwood_cpuidle",
-        .id             = -1,
-        .resource       = kirkwood_cpuidle_resource,
-        .num_resources  = 1,
-};
-
-static void __init kirkwood_cpuidle_init(void)
-{
-        platform_device_register(&kirkwood_cpuidle);
-}
-
-/* Temporary here since mach-mvebu has a function we can use */
-static void kirkwood_restart(enum reboot_mode mode, const char *cmd)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
-        while (1)
-                ;
-}
-
-#define MV643XX_ETH_MAC_ADDR_LOW        0x0414
-#define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
-
-static void __init kirkwood_dt_eth_fixup(void)
-{
-        struct device_node *np;
-
-        /*
-         * The ethernet interfaces forget the MAC address assigned by u-boot
-         * if the clocks are turned off. Usually, u-boot on kirkwood boards
-         * has no DT support to properly set local-mac-address property.
-         * As a workaround, we get the MAC address from mv643xx_eth registers
-         * and update the port device node if no valid MAC address is set.
-         */
-        for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") {
-                struct device_node *pnp = of_get_parent(np);
-                struct clk *clk;
-                struct property *pmac;
-                void __iomem *io;
-                u8 *macaddr;
-                u32 reg;
-
-                if (!pnp)
-                        continue;
-
-                /* skip disabled nodes or nodes with valid MAC address*/
-                if (!of_device_is_available(pnp) || of_get_mac_address(np))
-                        goto eth_fixup_skip;
-
-                clk = of_clk_get(pnp, 0);
-                if (IS_ERR(clk))
-                        goto eth_fixup_skip;
-
-                io = of_iomap(pnp, 0);
-                if (!io)
-                        goto eth_fixup_no_map;
-
-                /* ensure port clock is not gated to not hang CPU */
-                clk_prepare_enable(clk);
-
-                /* store MAC address register contents in local-mac-address */
-                pr_err(FW_INFO "%s: local-mac-address is not set\n",
-                       np->full_name);
-
-                pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
-                if (!pmac)
-                        goto eth_fixup_no_mem;
-
-                pmac->value = pmac + 1;
-                pmac->length = 6;
-                pmac->name = kstrdup("local-mac-address", GFP_KERNEL);
-                if (!pmac->name) {
-                        kfree(pmac);
-                        goto eth_fixup_no_mem;
-                }
-
-                macaddr = pmac->value;
-                reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH);
-                macaddr[0] = (reg >> 24) & 0xff;
-                macaddr[1] = (reg >> 16) & 0xff;
-                macaddr[2] = (reg >> 8) & 0xff;
-                macaddr[3] = reg & 0xff;
-
-                reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW);
-                macaddr[4] = (reg >> 8) & 0xff;
-                macaddr[5] = reg & 0xff;
-
-                of_update_property(np, pmac);
-
-eth_fixup_no_mem:
-                iounmap(io);
-                clk_disable_unprepare(clk);
-eth_fixup_no_map:
-                clk_put(clk);
-eth_fixup_skip:
-                of_node_put(pnp);
-        }
-}
-
-/*
- * Disable propagation of mbus errors to the CPU local bus, as this
- * causes mbus errors (which can occur for example for PCI aborts) to
- * throw CPU aborts, which we're not set up to deal with.
- */
-static void __init kirkwood_disable_mbus_error_propagation(void)
-{
-        void __iomem *cpu_config;
-
-        cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
-        writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
-        iounmap(cpu_config);
-}
-
-static void __init kirkwood_dt_init(void)
-{
-        kirkwood_disable_mbus_error_propagation();
-
-        BUG_ON(mvebu_mbus_dt_init(false));
-
-#ifdef CONFIG_CACHE_FEROCEON_L2
-        feroceon_of_init();
-#endif
-        kirkwood_cpufreq_init();
-        kirkwood_cpuidle_init();
-
-        kirkwood_pm_init();
-        kirkwood_dt_eth_fixup();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const kirkwood_dt_board_compat[] = {
-        "marvell,kirkwood",
-        NULL
-};
-
-DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
-        /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
-        .map_io         = kirkwood_map_io,
-        .init_machine   = kirkwood_dt_init,
-        .restart        = kirkwood_restart,
-        .dt_compat      = kirkwood_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
deleted file mode 100644
index 255f33a3903c..000000000000
--- a/arch/arm/mach-kirkwood/common.c
+++ /dev/null
@@ -1,746 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/common.c
- *
- * Core functions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/ata_platform.h>
-#include <linux/mtd/nand.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk-provider.h>
-#include <linux/spinlock.h>
-#include <linux/mv643xx_i2c.h>
-#include <linux/timex.h>
-#include <linux/kexec.h>
-#include <linux/reboot.h>
-#include <net/dsa.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/cache-feroceon-l2.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
-#include <linux/platform_data/asoc-kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include <linux/platform_data/mtd-orion_nand.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <plat/common.h>
-#include <plat/time.h>
-#include <linux/platform_data/dma-mv_xor.h>
-#include "common.h"
-#include "pm.h"
-
-/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
-#define KIRKWOOD_MBUS_NAND_TARGET 0x01
-#define KIRKWOOD_MBUS_NAND_ATTR   0x2f
-#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
-#define KIRKWOOD_MBUS_SRAM_ATTR   0x01
-
-/*****************************************************************************
- * I/O Address Mapping
- ****************************************************************************/
-static struct map_desc kirkwood_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
-                .length         = KIRKWOOD_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-void __init kirkwood_map_io(void)
-{
-        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
-}
-
-/*****************************************************************************
- * CLK tree
- ****************************************************************************/
-
-static void enable_sata0(void)
-{
-        /* Enable PLL and IVREF */
-        writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
-        /* Enable PHY */
-        writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
-}
-
-static void disable_sata0(void)
-{
-        /* Disable PLL and IVREF */
-        writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
-        /* Disable PHY */
-        writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
-}
-
-static void enable_sata1(void)
-{
-        /* Enable PLL and IVREF */
-        writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
-        /* Enable PHY */
-        writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
-}
-
-static void disable_sata1(void)
-{
-        /* Disable PLL and IVREF */
-        writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
-        /* Disable PHY */
-        writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
-}
-
-static void disable_pcie0(void)
-{
-        writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
-        while (1)
-                if (readl(PCIE_STATUS) & 0x1)
-                        break;
-        writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
-}
-
-static void disable_pcie1(void)
-{
-        u32 dev, rev;
-
-        kirkwood_pcie_id(&dev, &rev);
-
-        if (dev == MV88F6282_DEV_ID) {
-                writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
-                while (1)
-                        if (readl(PCIE1_STATUS) & 0x1)
-                                break;
-                writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
-        }
-}
-
-/* An extended version of the gated clk. This calls fn_en()/fn_dis
- * before enabling/disabling the clock.  We use this to turn on/off
- * PHYs etc.  */
-struct clk_gate_fn {
-        struct clk_gate gate;
-        void (*fn_en)(void);
-        void (*fn_dis)(void);
-};
-
-#define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static int clk_gate_fn_enable(struct clk_hw *hw)
-{
-        struct clk_gate *gate = to_clk_gate(hw);
-        struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
-        int ret;
-
-        ret = clk_gate_ops.enable(hw);
-        if (!ret && gate_fn->fn_en)
-                gate_fn->fn_en();
-
-        return ret;
-}
-
-static void clk_gate_fn_disable(struct clk_hw *hw)
-{
-        struct clk_gate *gate = to_clk_gate(hw);
-        struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
-
-        if (gate_fn->fn_dis)
-                gate_fn->fn_dis();
-
-        clk_gate_ops.disable(hw);
-}
-
-static struct clk_ops clk_gate_fn_ops;
-
-static struct clk __init *clk_register_gate_fn(struct device *dev,
-                const char *name,
-                const char *parent_name, unsigned long flags,
-                void __iomem *reg, u8 bit_idx,
-                u8 clk_gate_flags, spinlock_t *lock,
-                void (*fn_en)(void), void (*fn_dis)(void))
-{
-        struct clk_gate_fn *gate_fn;
-        struct clk *clk;
-        struct clk_init_data init;
-
-        gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
-        if (!gate_fn) {
-                pr_err("%s: could not allocate gated clk\n", __func__);
-                return ERR_PTR(-ENOMEM);
-        }
-
-        init.name = name;
-        init.ops = &clk_gate_fn_ops;
-        init.flags = flags;
-        init.parent_names = (parent_name ? &parent_name : NULL);
-        init.num_parents = (parent_name ? 1 : 0);
-
-        /* struct clk_gate assignments */
-        gate_fn->gate.reg = reg;
-        gate_fn->gate.bit_idx = bit_idx;
-        gate_fn->gate.flags = clk_gate_flags;
-        gate_fn->gate.lock = lock;
-        gate_fn->gate.hw.init = &init;
-        gate_fn->fn_en = fn_en;
-        gate_fn->fn_dis = fn_dis;
-
-        /* ops is the gate ops, but with our enable/disable functions */
-        if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
-            clk_gate_fn_ops.disable != clk_gate_fn_disable) {
-                clk_gate_fn_ops = clk_gate_ops;
-                clk_gate_fn_ops.enable = clk_gate_fn_enable;
-                clk_gate_fn_ops.disable = clk_gate_fn_disable;
-        }
-
-        clk = clk_register(dev, &gate_fn->gate.hw);
-
-        if (IS_ERR(clk))
-                kfree(gate_fn);
-
-        return clk;
-}
-
-static DEFINE_SPINLOCK(gating_lock);
-static struct clk *tclk;
-
-static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
-{
-        return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
-                                 bit_idx, 0, &gating_lock);
-}
-
-static struct clk __init *kirkwood_register_gate_fn(const char *name,
-                                                    u8 bit_idx,
-                                                    void (*fn_en)(void),
-                                                    void (*fn_dis)(void))
-{
-        return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
-                                    bit_idx, 0, &gating_lock, fn_en, fn_dis);
-}
-
-static struct clk *ge0, *ge1;
-
-void __init kirkwood_clk_init(void)
-{
-        struct clk *runit, *sata0, *sata1, *usb0, *sdio;
-        struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
-
-        tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
-                                       CLK_IS_ROOT, kirkwood_tclk);
-
-        runit = kirkwood_register_gate("runit",  CGC_BIT_RUNIT);
-        ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
-        ge1 = kirkwood_register_gate("ge1",    CGC_BIT_GE1);
-        sata0 = kirkwood_register_gate_fn("sata0",  CGC_BIT_SATA0,
-                                          enable_sata0, disable_sata0);
-        sata1 = kirkwood_register_gate_fn("sata1",  CGC_BIT_SATA1,
-                                          enable_sata1, disable_sata1);
-        usb0 = kirkwood_register_gate("usb0",   CGC_BIT_USB0);
-        sdio = kirkwood_register_gate("sdio",   CGC_BIT_SDIO);
-        crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
-        xor0 = kirkwood_register_gate("xor0",   CGC_BIT_XOR0);
-        xor1 = kirkwood_register_gate("xor1",   CGC_BIT_XOR1);
-        pex0 = kirkwood_register_gate_fn("pex0",   CGC_BIT_PEX0,
-                                         NULL, disable_pcie0);
-        pex1 = kirkwood_register_gate_fn("pex1",   CGC_BIT_PEX1,
-                                         NULL, disable_pcie1);
-        audio = kirkwood_register_gate("audio",  CGC_BIT_AUDIO);
-        kirkwood_register_gate("tdm",    CGC_BIT_TDM);
-        kirkwood_register_gate("tsu",    CGC_BIT_TSU);
-
-        /* clkdev entries, mapping clks to devices */
-        orion_clkdev_add(NULL, "orion_spi.0", runit);
-        orion_clkdev_add(NULL, "orion_spi.1", runit);
-        orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
-        orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
-        orion_clkdev_add(NULL, "orion_wdt", tclk);
-        orion_clkdev_add("0", "sata_mv.0", sata0);
-        orion_clkdev_add("1", "sata_mv.0", sata1);
-        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
-        orion_clkdev_add(NULL, "orion_nand", runit);
-        orion_clkdev_add(NULL, "mvsdio", sdio);
-        orion_clkdev_add(NULL, "mv_crypto", crypto);
-        orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
-        orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
-        orion_clkdev_add("0", "pcie", pex0);
-        orion_clkdev_add("1", "pcie", pex1);
-        orion_clkdev_add(NULL, "mvebu-audio", audio);
-        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
-        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".1", runit);
-
-        /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
-         * so should never be gated.
-         */
-        clk_prepare_enable(runit);
-}
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-void __init kirkwood_ehci_init(void)
-{
-        orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
-}
-
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
-{
-        orion_ge00_init(eth_data,
-                        GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
-                        IRQ_KIRKWOOD_GE00_ERR, 1600);
-        /* The interface forgets the MAC address assigned by u-boot if
-        the clock is turned off, so claim the clk now. */
-        clk_prepare_enable(ge0);
-}
-
-
-/*****************************************************************************
- * GE01
- ****************************************************************************/
-void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
-{
-        orion_ge01_init(eth_data,
-                        GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
-                        IRQ_KIRKWOOD_GE01_ERR, 1600);
-        clk_prepare_enable(ge1);
-}
-
-
-/*****************************************************************************
- * Ethernet switch
- ****************************************************************************/
-void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
-{
-        orion_ge00_switch_init(d, irq);
-}
-
-
-/*****************************************************************************
- * NAND flash
- ****************************************************************************/
-static struct resource kirkwood_nand_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
-        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
-                                KIRKWOOD_NAND_MEM_SIZE - 1,
-};
-
-static struct orion_nand_data kirkwood_nand_data = {
-        .cle            = 0,
-        .ale            = 1,
-        .width          = 8,
-};
-
-static struct platform_device kirkwood_nand_flash = {
-        .name           = "orion_nand",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &kirkwood_nand_data,
-        },
-        .resource       = &kirkwood_nand_resource,
-        .num_resources  = 1,
-};
-
-void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
-                               int chip_delay)
-{
-        kirkwood_nand_data.parts = parts;
-        kirkwood_nand_data.nr_parts = nr_parts;
-        kirkwood_nand_data.chip_delay = chip_delay;
-        platform_device_register(&kirkwood_nand_flash);
-}
-
-void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
-                                   int (*dev_ready)(struct mtd_info *))
-{
-        kirkwood_nand_data.parts = parts;
-        kirkwood_nand_data.nr_parts = nr_parts;
-        kirkwood_nand_data.dev_ready = dev_ready;
-        platform_device_register(&kirkwood_nand_flash);
-}
-
-/*****************************************************************************
- * SoC RTC
- ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
-{
-        orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
-}
-
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
-{
-        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
-}
-
-
-/*****************************************************************************
- * SD/SDIO/MMC
- ****************************************************************************/
-static struct resource mvsdio_resources[] = {
-        [0] = {
-                .start  = SDIO_PHYS_BASE,
-                .end    = SDIO_PHYS_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_KIRKWOOD_SDIO,
-                .end    = IRQ_KIRKWOOD_SDIO,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device kirkwood_sdio = {
-        .name           = "mvsdio",
-        .id             = -1,
-        .dev            = {
-                .dma_mask = &mvsdio_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(mvsdio_resources),
-        .resource       = mvsdio_resources,
-};
-
-void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
-{
-        u32 dev, rev;
-
-        kirkwood_pcie_id(&dev, &rev);
-        if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
-                mvsdio_data->clock = 100000000;
-        else
-                mvsdio_data->clock = 200000000;
-        kirkwood_sdio.dev.platform_data = mvsdio_data;
-        platform_device_register(&kirkwood_sdio);
-}
-
-
-/*****************************************************************************
- * SPI
- ****************************************************************************/
-void __init kirkwood_spi_init(void)
-{
-        orion_spi_init(SPI_PHYS_BASE);
-}
-
-
-/*****************************************************************************
- * I2C
- ****************************************************************************/
-void __init kirkwood_i2c_init(void)
-{
-        orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
-}
-
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-
-void __init kirkwood_uart0_init(void)
-{
-        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
-                         IRQ_KIRKWOOD_UART_0, tclk);
-}
-
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-void __init kirkwood_uart1_init(void)
-{
-        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
-                         IRQ_KIRKWOOD_UART_1, tclk);
-}
-
-/*****************************************************************************
- * Cryptographic Engines and Security Accelerator (CESA)
- ****************************************************************************/
-void __init kirkwood_crypto_init(void)
-{
-        orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
-                          KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
-}
-
-
-/*****************************************************************************
- * XOR0
- ****************************************************************************/
-void __init kirkwood_xor0_init(void)
-{
-        orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
-                        IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
-}
-
-
-/*****************************************************************************
- * XOR1
- ****************************************************************************/
-void __init kirkwood_xor1_init(void)
-{
-        orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
-                        IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
-}
-
-
-/*****************************************************************************
- * Watchdog
- ****************************************************************************/
-void __init kirkwood_wdt_init(void)
-{
-        orion_wdt_init();
-}
-
-/*****************************************************************************
- * CPU idle
- ****************************************************************************/
-static struct resource kirkwood_cpuidle_resource[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-                .start  = DDR_OPERATION_BASE,
-                .end    = DDR_OPERATION_BASE + 3,
-        },
-};
-
-static struct platform_device kirkwood_cpuidle = {
-        .name           = "kirkwood_cpuidle",
-        .id             = -1,
-        .resource       = kirkwood_cpuidle_resource,
-        .num_resources  = 1,
-};
-
-void __init kirkwood_cpuidle_init(void)
-{
-        platform_device_register(&kirkwood_cpuidle);
-}
-
-/*****************************************************************************
- * Time handling
- ****************************************************************************/
-void __init kirkwood_init_early(void)
-{
-        orion_time_set_base(TIMER_VIRT_BASE);
-}
-
-int kirkwood_tclk;
-
-static int __init kirkwood_find_tclk(void)
-{
-        u32 dev, rev;
-
-        kirkwood_pcie_id(&dev, &rev);
-
-        if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
-                if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
-                        return 200000000;
-
-        return 166666667;
-}
-
-void __init kirkwood_timer_init(void)
-{
-        kirkwood_tclk = kirkwood_find_tclk();
-
-        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-                        IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
-
-/*****************************************************************************
- * Audio
- ****************************************************************************/
-static struct resource kirkwood_audio_resources[] = {
-        [0] = {
-                .start  = AUDIO_PHYS_BASE,
-                .end    = AUDIO_PHYS_BASE + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_KIRKWOOD_I2S,
-                .end    = IRQ_KIRKWOOD_I2S,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct kirkwood_asoc_platform_data kirkwood_audio_data = {
-        .burst       = 128,
-};
-
-static struct platform_device kirkwood_audio_device = {
-        .name           = "mvebu-audio",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(kirkwood_audio_resources),
-        .resource       = kirkwood_audio_resources,
-        .dev            = {
-                .platform_data  = &kirkwood_audio_data,
-        },
-};
-
-void __init kirkwood_audio_init(void)
-{
-        platform_device_register(&kirkwood_audio_device);
-}
-
-/*****************************************************************************
- * CPU Frequency
- ****************************************************************************/
-static struct resource kirkwood_cpufreq_resources[] = {
-        [0] = {
-                .start  = CPU_CONTROL_PHYS,
-                .end    = CPU_CONTROL_PHYS + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_cpufreq_device = {
-        .name           = "kirkwood-cpufreq",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
-        .resource       = kirkwood_cpufreq_resources,
-};
-
-void __init kirkwood_cpufreq_init(void)
-{
-        platform_device_register(&kirkwood_cpufreq_device);
-}
-
-/*****************************************************************************
- * General
- ****************************************************************************/
-/*
- * Identify device ID and revision.
- */
-char * __init kirkwood_id(void)
-{
-        u32 dev, rev;
-
-        kirkwood_pcie_id(&dev, &rev);
-
-        if (dev == MV88F6281_DEV_ID) {
-                if (rev == MV88F6281_REV_Z0)
-                        return "MV88F6281-Z0";
-                else if (rev == MV88F6281_REV_A0)
-                        return "MV88F6281-A0";
-                else if (rev == MV88F6281_REV_A1)
-                        return "MV88F6281-A1";
-                else
-                        return "MV88F6281-Rev-Unsupported";
-        } else if (dev == MV88F6192_DEV_ID) {
-                if (rev == MV88F6192_REV_Z0)
-                        return "MV88F6192-Z0";
-                else if (rev == MV88F6192_REV_A0)
-                        return "MV88F6192-A0";
-                else if (rev == MV88F6192_REV_A1)
-                        return "MV88F6192-A1";
-                else
-                        return "MV88F6192-Rev-Unsupported";
-        } else if (dev == MV88F6180_DEV_ID) {
-                if (rev == MV88F6180_REV_A0)
-                        return "MV88F6180-Rev-A0";
-                else if (rev == MV88F6180_REV_A1)
-                        return "MV88F6180-Rev-A1";
-                else
-                        return "MV88F6180-Rev-Unsupported";
-        } else if (dev == MV88F6282_DEV_ID) {
-                if (rev == MV88F6282_REV_A0)
-                        return "MV88F6282-Rev-A0";
-                else if (rev == MV88F6282_REV_A1)
-                        return "MV88F6282-Rev-A1";
-                else
-                        return "MV88F6282-Rev-Unsupported";
-        } else {
-                return "Device-Unknown";
-        }
-}
-
-void __init kirkwood_setup_wins(void)
-{
-        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
-                                    KIRKWOOD_MBUS_NAND_ATTR,
-                                    KIRKWOOD_NAND_MEM_PHYS_BASE,
-                                    KIRKWOOD_NAND_MEM_SIZE);
-        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
-                                    KIRKWOOD_MBUS_SRAM_ATTR,
-                                    KIRKWOOD_SRAM_PHYS_BASE,
-                                    KIRKWOOD_SRAM_SIZE);
-}
-
-void __init kirkwood_l2_init(void)
-{
-#ifdef CONFIG_CACHE_FEROCEON_L2
-#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
-        writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
-        feroceon_l2_init(1);
-#else
-        writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
-        feroceon_l2_init(0);
-#endif
-#endif
-}
-
-void __init kirkwood_init(void)
-{
-        pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
-
-        /*
-         * Disable propagation of mbus errors to the CPU local bus,
-         * as this causes mbus errors (which can occur for example
-         * for PCI aborts) to throw CPU aborts, which we're not set
-         * up to deal with.
-         */
-        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-
-        BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
-                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
-
-        kirkwood_setup_wins();
-
-        kirkwood_l2_init();
-
-        /* Setup root of clk tree */
-        kirkwood_clk_init();
-
-        /* internal devices that every board has */
-        kirkwood_rtc_init();
-        kirkwood_wdt_init();
-        kirkwood_xor0_init();
-        kirkwood_xor1_init();
-        kirkwood_crypto_init();
-
-        kirkwood_pm_init();
-        kirkwood_cpuidle_init();
-#ifdef CONFIG_KEXEC
-        kexec_reinit = kirkwood_enable_pcie;
-#endif
-}
-
-void kirkwood_restart(enum reboot_mode mode, const char *cmd)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
-        while (1)
-                ;
-}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
deleted file mode 100644
index 832a4e2ab8d7..000000000000
--- a/arch/arm/mach-kirkwood/common.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/common.h
- *
- * Core functions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ARCH_KIRKWOOD_COMMON_H
-#define __ARCH_KIRKWOOD_COMMON_H
-
-#include <linux/reboot.h>
-
-struct dsa_platform_data;
-struct mv643xx_eth_platform_data;
-struct mv_sata_platform_data;
-struct mvsdio_platform_data;
-struct mtd_partition;
-struct mtd_info;
-struct kirkwood_asoc_platform_data;
-
-#define KW_PCIE0        (1 << 0)
-#define KW_PCIE1        (1 << 1)
-
-/*
- * Basic Kirkwood init functions used early by machine-setup.
- */
-void kirkwood_map_io(void);
-void kirkwood_init(void);
-void kirkwood_init_early(void);
-void kirkwood_init_irq(void);
-
-void kirkwood_setup_wins(void);
-
-void kirkwood_enable_pcie(void);
-void kirkwood_pcie_id(u32 *dev, u32 *rev);
-
-void kirkwood_ehci_init(void);
-void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
-void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
-void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(unsigned int portmask);
-void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
-void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
-void kirkwood_spi_init(void);
-void kirkwood_i2c_init(void);
-void kirkwood_uart0_init(void);
-void kirkwood_uart1_init(void);
-void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
-void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
-                            int (*dev_ready)(struct mtd_info *));
-void kirkwood_audio_init(void);
-void kirkwood_cpuidle_init(void);
-void kirkwood_cpufreq_init(void);
-
-void kirkwood_restart(enum reboot_mode, const char *);
-void kirkwood_clk_init(void);
-
-/* early init functions not converted to fdt yet */
-char *kirkwood_id(void);
-void kirkwood_l2_init(void);
-void kirkwood_wdt_init(void);
-void kirkwood_xor0_init(void);
-void kirkwood_xor1_init(void);
-void kirkwood_crypto_init(void);
-
-extern int kirkwood_tclk;
-extern void kirkwood_timer_init(void);
-
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-
-#endif
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
deleted file mode 100644
index 453418063c1e..000000000000
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/d2net_v2-setup.c
- *
- * LaCie d2 Network Space v2 Board Setup
- *
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/leds-kirkwood-ns2.h>
-#include "common.h"
-#include "mpp.h"
-#include "lacie_v2-common.h"
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-
-static struct mv_sata_platform_data d2net_v2_sata_data = {
-        .n_ports        = 2,
-};
-
-/*****************************************************************************
- * GPIO keys
- ****************************************************************************/
-
-#define D2NET_V2_GPIO_PUSH_BUTTON          34
-#define D2NET_V2_GPIO_POWER_SWITCH_ON      13
-#define D2NET_V2_GPIO_POWER_SWITCH_OFF     15
-
-#define D2NET_V2_SWITCH_POWER_ON           0x1
-#define D2NET_V2_SWITCH_POWER_OFF          0x2
-
-static struct gpio_keys_button d2net_v2_buttons[] = {
-        [0] = {
-                .type           = EV_SW,
-                .code           = D2NET_V2_SWITCH_POWER_ON,
-                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_ON,
-                .desc           = "Back power switch (on|auto)",
-                .active_low     = 0,
-        },
-        [1] = {
-                .type           = EV_SW,
-                .code           = D2NET_V2_SWITCH_POWER_OFF,
-                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_OFF,
-                .desc           = "Back power switch (auto|off)",
-                .active_low     = 0,
-        },
-        [2] = {
-                .code           = KEY_POWER,
-                .gpio           = D2NET_V2_GPIO_PUSH_BUTTON,
-                .desc           = "Front Push Button",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data d2net_v2_button_data = {
-        .buttons        = d2net_v2_buttons,
-        .nbuttons       = ARRAY_SIZE(d2net_v2_buttons),
-};
-
-static struct platform_device d2net_v2_gpio_buttons = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &d2net_v2_button_data,
-        },
-};
-
-/*****************************************************************************
- * GPIO LEDs
- ****************************************************************************/
-
-#define D2NET_V2_GPIO_RED_LED           12
-
-static struct gpio_led d2net_v2_gpio_led_pins[] = {
-        {
-                .name   = "d2net_v2:red:fail",
-                .gpio   = D2NET_V2_GPIO_RED_LED,
-        },
-};
-
-static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
-        .num_leds       = ARRAY_SIZE(d2net_v2_gpio_led_pins),
-        .leds           = d2net_v2_gpio_led_pins,
-};
-
-static struct platform_device d2net_v2_gpio_leds = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &d2net_v2_gpio_leds_data,
-        },
-};
-
-/*****************************************************************************
- * Dual-GPIO CPLD LEDs
- ****************************************************************************/
-
-#define D2NET_V2_GPIO_BLUE_LED_SLOW     29
-#define D2NET_V2_GPIO_BLUE_LED_CMD      30
-
-static struct ns2_led d2net_v2_led_pins[] = {
-        {
-                .name   = "d2net_v2:blue:sata",
-                .cmd    = D2NET_V2_GPIO_BLUE_LED_CMD,
-                .slow   = D2NET_V2_GPIO_BLUE_LED_SLOW,
-        },
-};
-
-static struct ns2_led_platform_data d2net_v2_leds_data = {
-        .num_leds       = ARRAY_SIZE(d2net_v2_led_pins),
-        .leds           = d2net_v2_led_pins,
-};
-
-static struct platform_device d2net_v2_leds = {
-        .name           = "leds-ns2",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &d2net_v2_leds_data,
-        },
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-static unsigned int d2net_v2_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP6_SYSRST_OUTn,
-        MPP7_GPO,               /* Request power-off */
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP12_GPO,              /* Red led */
-        MPP13_GPIO,             /* Rear power switch (on|auto) */
-        MPP14_GPIO,             /* USB fuse */
-        MPP15_GPIO,             /* Rear power switch (auto|off) */
-        MPP16_GPIO,             /* SATA 0 power */
-        MPP21_SATA0_ACTn,
-        MPP24_GPIO,             /* USB mode select */
-        MPP26_GPIO,             /* USB device vbus */
-        MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* Blue led (slow register) */
-        MPP30_GPIO,             /* Blue led (command register) */
-        MPP34_GPIO,             /* Power button (1 = Released, 0 = Pushed) */
-        MPP35_GPIO,             /* Inhibit power-off */
-        0
-};
-
-#define D2NET_V2_GPIO_POWER_OFF         7
-
-static void d2net_v2_power_off(void)
-{
-        gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
-}
-
-static void __init d2net_v2_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(d2net_v2_mpp_config);
-
-        lacie_v2_hdd_power_init(1);
-
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&d2net_v2_ge00_data);
-        kirkwood_sata_init(&d2net_v2_sata_data);
-        kirkwood_uart0_init();
-        lacie_v2_register_flash();
-        lacie_v2_register_i2c_devices();
-
-        platform_device_register(&d2net_v2_leds);
-        platform_device_register(&d2net_v2_gpio_leds);
-        platform_device_register(&d2net_v2_gpio_buttons);
-
-        if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
-            gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
-                pm_power_off = d2net_v2_power_off;
-        else
-                pr_err("d2net_v2: failed to configure power-off GPIO\n");
-}
-
-MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
-        .atag_offset    = 0x100,
-        .init_machine   = d2net_v2_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
deleted file mode 100644
index 1c37082c8b39..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/bridge-regs.h
- *
- * Mbus-L to Mbus Bridge Registers
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_BRIDGE_REGS_H
-#define __ASM_ARCH_BRIDGE_REGS_H
-
-#include <mach/kirkwood.h>
-
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
-#define CPU_CONFIG_PHYS         (BRIDGE_PHYS_BASE + 0x0100)
-#define CPU_CONFIG_ERROR_PROP   0x00000004
-
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
-#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
-#define CPU_RESET               0x00000002
-
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
-#define RSTOUTn_MASK_PHYS       (BRIDGE_PHYS_BASE + 0x0108)
-#define SOFT_RESET_OUT_EN       0x00000004
-
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
-#define SOFT_RESET              0x00000001
-
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
-
-#define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
-#define IRQ_CAUSE_LOW_OFF       0x0000
-#define IRQ_MASK_LOW_OFF        0x0004
-#define IRQ_CAUSE_HIGH_OFF      0x0010
-#define IRQ_MASK_HIGH_OFF       0x0014
-
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
-
-#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
-#define L2_WRITETHROUGH         0x00000010
-
-#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
-#define CGC_BIT_GE0             (0)
-#define CGC_BIT_PEX0            (2)
-#define CGC_BIT_USB0            (3)
-#define CGC_BIT_SDIO            (4)
-#define CGC_BIT_TSU             (5)
-#define CGC_BIT_DUNIT           (6)
-#define CGC_BIT_RUNIT           (7)
-#define CGC_BIT_XOR0            (8)
-#define CGC_BIT_AUDIO           (9)
-#define CGC_BIT_SATA0           (14)
-#define CGC_BIT_SATA1           (15)
-#define CGC_BIT_XOR1            (16)
-#define CGC_BIT_CRYPTO          (17)
-#define CGC_BIT_PEX1            (18)
-#define CGC_BIT_GE1             (19)
-#define CGC_BIT_TDM             (20)
-#define CGC_GE0                 (1 << 0)
-#define CGC_PEX0                (1 << 2)
-#define CGC_USB0                (1 << 3)
-#define CGC_SDIO                (1 << 4)
-#define CGC_TSU                 (1 << 5)
-#define CGC_DUNIT               (1 << 6)
-#define CGC_RUNIT               (1 << 7)
-#define CGC_XOR0                (1 << 8)
-#define CGC_AUDIO               (1 << 9)
-#define CGC_POWERSAVE           (1 << 11)
-#define CGC_SATA0               (1 << 14)
-#define CGC_SATA1               (1 << 15)
-#define CGC_XOR1                (1 << 16)
-#define CGC_CRYPTO              (1 << 17)
-#define CGC_PEX1                (1 << 18)
-#define CGC_GE1                 (1 << 19)
-#define CGC_TDM                 (1 << 20)
-#define CGC_RESERVED            (0x6 << 21)
-
-#define MEMORY_PM_CTRL          (BRIDGE_VIRT_BASE + 0x118)
-#define MEMORY_PM_CTRL_PHYS     (BRIDGE_PHYS_BASE + 0x118)
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/entry-macro.S b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
deleted file mode 100644
index 82db29f7af8f..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/entry-macro.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell Kirkwood platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/bridge-regs.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IRQ_VIRT_BASE
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check low interrupts
-        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
-        mov     \irqnr, #31
-        ands    \irqstat, \irqstat, \tmp
-        bne     1001f
-
-        @ if no low interrupts set, check high interrupts
-        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-        mov     \irqnr, #63
-        ands    \irqstat, \irqstat, \tmp
-
-        @ find first active interrupt source
-1001:   clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/mach-kirkwood/include/mach/hardware.h b/arch/arm/mach-kirkwood/include/mach/hardware.h
deleted file mode 100644
index 742b74f43e41..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/hardware.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/hardware.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "kirkwood.h"
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
deleted file mode 100644
index 2bf8161e3b51..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/irqs.h
- *
- * IRQ definitions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/*
- * Low Interrupt Controller
- */
-#define IRQ_KIRKWOOD_HIGH_SUM   0
-#define IRQ_KIRKWOOD_BRIDGE     1
-#define IRQ_KIRKWOOD_HOST2CPU   2
-#define IRQ_KIRKWOOD_CPU2HOST   3
-#define IRQ_KIRKWOOD_XOR_00     5
-#define IRQ_KIRKWOOD_XOR_01     6
-#define IRQ_KIRKWOOD_XOR_10     7
-#define IRQ_KIRKWOOD_XOR_11     8
-#define IRQ_KIRKWOOD_PCIE       9
-#define IRQ_KIRKWOOD_PCIE1      10
-#define IRQ_KIRKWOOD_GE00_SUM   11
-#define IRQ_KIRKWOOD_GE01_SUM   15
-#define IRQ_KIRKWOOD_USB        19
-#define IRQ_KIRKWOOD_SATA       21
-#define IRQ_KIRKWOOD_CRYPTO     22
-#define IRQ_KIRKWOOD_SPI        23
-#define IRQ_KIRKWOOD_I2S        24
-#define IRQ_KIRKWOOD_TS_0       26
-#define IRQ_KIRKWOOD_SDIO       28
-#define IRQ_KIRKWOOD_TWSI       29
-#define IRQ_KIRKWOOD_AVB        30
-#define IRQ_KIRKWOOD_TDMI       31
-
-/*
- * High Interrupt Controller
- */
-#define IRQ_KIRKWOOD_UART_0     33
-#define IRQ_KIRKWOOD_UART_1     34
-#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
-#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
-#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
-#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
-#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
-#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
-#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
-#define IRQ_KIRKWOOD_GE00_ERR   46
-#define IRQ_KIRKWOOD_GE01_ERR   47
-#define IRQ_KIRKWOOD_RTC        53
-
-/*
- * KIRKWOOD General Purpose Pins
- */
-#define IRQ_KIRKWOOD_GPIO_START 64
-#define NR_GPIO_IRQS            50
-
-#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
deleted file mode 100644
index 92976cef3910..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/kirkwood.h
- *
- * Generic definitions for Marvell Kirkwood SoC flavors:
- *  88F6180, 88F6192 and 88F6281.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_KIRKWOOD_H
-#define __ASM_ARCH_KIRKWOOD_H
-
-/*
- * Marvell Kirkwood address maps.
- *
- * phys
- * e0000000     PCIe #0 Memory space
- * e8000000     PCIe #1 Memory space
- * f1000000     on-chip peripheral registers
- * f2000000     PCIe #0 I/O space
- * f3000000     PCIe #1 I/O space
- * f4000000     NAND controller address window
- * f5000000     Security Accelerator SRAM
- *
- * virt         phys            size
- * fed00000     f1000000        1M      on-chip peripheral registers
- * fee00000     f2000000        1M      PCIe #0 I/O space
- * fef00000     f3000000        1M      PCIe #1 I/O space
- */
-
-#define KIRKWOOD_SRAM_PHYS_BASE         0xf5000000
-#define KIRKWOOD_SRAM_SIZE              SZ_2K
-
-#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf4000000
-#define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
-
-#define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00010000
-#define KIRKWOOD_PCIE1_IO_SIZE          SZ_64K
-
-#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
-
-#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
-#define KIRKWOOD_REGS_SIZE              SZ_1M
-
-#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
-#define KIRKWOOD_PCIE_MEM_BUS_BASE      0xe0000000
-#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
-
-#define KIRKWOOD_PCIE1_MEM_PHYS_BASE    0xe8000000
-#define KIRKWOOD_PCIE1_MEM_BUS_BASE     0xe8000000
-#define KIRKWOOD_PCIE1_MEM_SIZE         SZ_128M
-
-/*
- * Register Map
- */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
-#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_PHYS_BASE + 0x1500)
-#define  DDR_WINDOW_CPU_SZ      (0x20)
-#define DDR_OPERATION_BASE      (DDR_PHYS_BASE + 0x1418)
-
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
-#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
-#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
-#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
-
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
-#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
-#define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
-#define  BRIDGE_WINS_SZ         (0x80)
-
-#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
-
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
-#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
-#define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
-#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
-#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
-#define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
-
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
-
-#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
-#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
-#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
-#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
-#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
-#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
-#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
-#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
-
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
-
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
-#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
-#define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
-#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
-#define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
-#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
-
-#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
-
-#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
-#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
-
-/*
- * Supported devices and revisions.
- */
-#define MV88F6281_DEV_ID        0x6281
-#define MV88F6281_REV_Z0        0
-#define MV88F6281_REV_A0        2
-#define MV88F6281_REV_A1        3
-
-#define MV88F6192_DEV_ID        0x6192
-#define MV88F6192_REV_Z0        0
-#define MV88F6192_REV_A0        2
-#define MV88F6192_REV_A1        3
-
-#define MV88F6180_DEV_ID        0x6180
-#define MV88F6180_REV_A0        2
-#define MV88F6180_REV_A1        3
-
-#define MV88F6282_DEV_ID        0x6282
-#define MV88F6282_REV_A0        0
-#define MV88F6282_REV_A1        1
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/uncompress.h b/arch/arm/mach-kirkwood/include/mach/uncompress.h
deleted file mode 100644
index 5bca5534021f..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/uncompress.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <mach/kirkwood.h>
-
-#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
-        unsigned char *base = SERIAL_BASE;
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                if (base[UART_LSR << 2] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
-        unsigned char *base = SERIAL_BASE;
-        unsigned char mask;
-        int i;
-
-        mask = UART_LSR_TEMT | UART_LSR_THRE;
-
-        for (i = 0; i < 0x1000; i++) {
-                if ((base[UART_LSR << 2] & mask) == mask)
-                        break;
-                barrier();
-        }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
deleted file mode 100644
index 2c47a8ad0e27..000000000000
--- a/arch/arm/mach-kirkwood/irq.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/irq.c
- *
- * Kirkwood IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/exception.h>
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/bridge-regs.h>
-#include <plat/orion-gpio.h>
-#include <plat/irq.h>
-#include "common.h"
-
-static int __initdata gpio0_irqs[4] = {
-        IRQ_KIRKWOOD_GPIO_LOW_0_7,
-        IRQ_KIRKWOOD_GPIO_LOW_8_15,
-        IRQ_KIRKWOOD_GPIO_LOW_16_23,
-        IRQ_KIRKWOOD_GPIO_LOW_24_31,
-};
-
-static int __initdata gpio1_irqs[4] = {
-        IRQ_KIRKWOOD_GPIO_HIGH_0_7,
-        IRQ_KIRKWOOD_GPIO_HIGH_8_15,
-        IRQ_KIRKWOOD_GPIO_HIGH_16_23,
-        0,
-};
-
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-/*
- * Compiling with both non-DT and DT support enabled, will
- * break asm irq handler used by non-DT boards. Therefore,
- * we provide a C-style irq handler even for non-DT boards,
- * if MULTI_IRQ_HANDLER is set.
- */
-
-static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE;
-
-asmlinkage void
-__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs)
-{
-        u32 stat;
-
-        stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF);
-        stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF);
-        if (stat) {
-                unsigned int hwirq = __fls(stat);
-                handle_IRQ(hwirq, regs);
-                return;
-        }
-        stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF);
-        stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF);
-        if (stat) {
-                unsigned int hwirq = 32 + __fls(stat);
-                handle_IRQ(hwirq, regs);
-                return;
-        }
-}
-#endif
-
-void __init kirkwood_init_irq(void)
-{
-        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
-        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
-
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-        set_handle_irq(kirkwood_legacy_handle_irq);
-#endif
-
-        /*
-         * Initialize gpiolib for GPIOs 0-49.
-         */
-        orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
-                        IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
-                        IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
-}
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
deleted file mode 100644
index 8e3e4331c380..000000000000
--- a/arch/arm/mach-kirkwood/lacie_v2-common.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/lacie_v2-common.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
-#include <linux/gpio.h>
-#include <asm/mach/time.h>
-#include <mach/kirkwood.h>
-#include <mach/irqs.h>
-#include <plat/time.h>
-#include "common.h"
-#include "lacie_v2-common.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition lacie_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data lacie_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = lacie_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(lacie_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &lacie_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
-
-void __init lacie_v2_register_flash(void)
-{
-        spi_register_board_info(lacie_v2_spi_slave_info,
-                                ARRAY_SIZE(lacie_v2_spi_slave_info));
-        kirkwood_spi_init();
-}
-
-/*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-void __init lacie_v2_register_i2c_devices(void)
-{
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, lacie_v2_i2c_info,
-                                ARRAY_SIZE(lacie_v2_i2c_info));
-}
-
-/*****************************************************************************
- * Hard Disk power
- ****************************************************************************/
-
-static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
-
-void __init lacie_v2_hdd_power_init(int hdd_num)
-{
-        int i;
-        int err;
-
-        /* Power up all hard disks. */
-        for (i = 0; i < hdd_num; i++) {
-                err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        lacie_v2_gpio_hdd_power[i], 1);
-                        /* Free the HDD power GPIOs. This allow user-space to
-                         * configure them via the gpiolib sysfs interface. */
-                        gpio_free(lacie_v2_gpio_hdd_power[i]);
-                }
-                if (err)
-                        pr_err("Failed to power up HDD%d\n", i + 1);
-        }
-}
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
deleted file mode 100644
index fc64f578536e..000000000000
--- a/arch/arm/mach-kirkwood/lacie_v2-common.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/lacie_v2-common.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
-#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
-
-void lacie_v2_register_flash(void);
-void lacie_v2_register_i2c_devices(void);
-void lacie_v2_hdd_power_init(int hdd_num);
-
-#endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
deleted file mode 100644
index e96fd71abd76..000000000000
--- a/arch/arm/mach-kirkwood/mpp.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/mpp.c
- *
- * MPP functions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <plat/mpp.h>
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int __init kirkwood_variant(void)
-{
-        u32 dev, rev;
-
-        kirkwood_pcie_id(&dev, &rev);
-
-        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
-                return MPP_F6281_MASK;
-        if (dev == MV88F6282_DEV_ID)
-                return MPP_F6282_MASK;
-        if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
-                return MPP_F6192_MASK;
-        if (dev == MV88F6180_DEV_ID)
-                return MPP_F6180_MASK;
-
-        pr_err("MPP setup: unknown kirkwood variant (dev %#x rev %#x)\n",
-               dev, rev);
-        return 0;
-}
-
-void __init kirkwood_mpp_conf(unsigned int *mpp_list)
-{
-        orion_mpp_conf(mpp_list, kirkwood_variant(),
-                       MPP_MAX, DEV_BUS_VIRT_BASE);
-}
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
deleted file mode 100644
index d5a0d1da2e0e..000000000000
--- a/arch/arm/mach-kirkwood/mpp.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
- *
- * Copyright 2009: Marvell Technology Group Ltd.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __KIRKWOOD_MPP_H
-#define __KIRKWOOD_MPP_H
-
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
-        /* MPP number */                ((_num) & 0xff) | \
-        /* MPP select value */          (((_sel) & 0xf) << 8) | \
-        /* may be input signal */       ((!!(_in)) << 12) | \
-        /* may be output signal */      ((!!(_out)) << 13) | \
-        /* available on F6180 */        ((!!(_F6180)) << 14) | \
-        /* available on F6190 */        ((!!(_F6190)) << 15) | \
-        /* available on F6192 */        ((!!(_F6192)) << 16) | \
-        /* available on F6281 */        ((!!(_F6281)) << 17) | \
-        /* available on F6282 */        ((!!(_F6282)) << 18))
-
-                                /*   num sel  i  o  6180 6190 6192 6281 6282 */
-
-#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
-#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
-#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
-#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
-#define MPP_F6282_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP0_NF_IO2             MPP(  0, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP1_NF_IO3             MPP(  1, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP2_NF_IO4             MPP(  2, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP3_NF_IO5             MPP(  3, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP3_SPI_MISO           MPP(  3, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP4_NF_IO6             MPP(  4, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP4_UART0_RXD          MPP(  4, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP4_LCD_VGA_HSYNC      MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP4_PTP_CLK            MPP(  4, 0xd, 0, 0, 1,   1,   1,   1,   0 )
-
-#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP5_NF_IO7             MPP(  5, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP5_LCD_VGA_VSYNC      MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 0, 1,   1,   1,   1,   0 )
-
-#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP8_TW0_SDA            MPP(  8, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_MII0_RXERR         MPP(  8, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP8_PTP_CLK            MPP(  8, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP8_MII0_COL           MPP(  8, 0xd, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP9_TW0_SCK            MPP(  9, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_UART0_CTS          MPP(  9, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_UART1_CTS          MPP(  9, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP9_MII0_CRS           MPP(  9, 0xd, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-
-#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP11_SPI_MISO          MPP( 11, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP11_UART0_RXD         MPP( 11, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_PTP_CLK           MPP( 11, 0xd, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-
-#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP12_GPIO              MPP( 12, 0x0, 1, 1, 0,   0,   0,   1,   0 )
-#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP12_TW1_SDA           MPP( 12, 0xd, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP13_SD_CMD            MPP( 13, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP13_LCDPWM            MPP( 13, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP14_SD_D0             MPP( 14, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP14_UART1_RXD         MPP( 14, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP14_AU_SPDIFI         MPP( 14, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP14_AU_I2SDI          MPP( 14, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP14_MII0_COL          MPP( 14, 0xd, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP15_SD_D1             MPP( 15, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP16_SD_D2             MPP( 16, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_UART0_CTS         MPP( 16, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_UART1_RXD         MPP( 16, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP16_MII0_CRS          MPP( 16, 0xd, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP17_SD_D3             MPP( 17, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP17_TW1_SCK           MPP( 17, 0xd, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP18_NF_IO0            MPP( 18, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP19_NF_IO1            MPP( 19, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP20_TSMP0             MPP( 20, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_GE1_TXD0          MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP20_AU_SPDIFI         MPP( 20, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_LCD_D0            MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP21_TSMP1             MPP( 21, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP21_GE1_TXD1          MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP21_LCD_D1            MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP22_TSMP2             MPP( 22, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_GE1_TXD2          MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_LCD_D2            MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP23_TSMP3             MPP( 23, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP23_GE1_TXD3          MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP23_LCD_D3            MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP24_TSMP4             MPP( 24, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP24_GE1_RXD0          MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP24_LCD_D4            MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP25_TSMP5             MPP( 25, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP25_GE1_RXD1          MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP25_LCD_D5            MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP26_TSMP6             MPP( 26, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP26_GE1_RXD2          MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP26_LCD_D6            MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP27_TSMP7             MPP( 27, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP27_GE1_RXD3          MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP27_AU_I2SDI          MPP( 27, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP27_LCD_D7            MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP28_TSMP8             MPP( 28, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP28_GE1_COL           MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP28_AU_EXTCLK         MPP( 28, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP28_LCD_D8            MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP29_TSMP9             MPP( 29, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP29_GE1_TCLK          MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP29_LCD_D9            MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP30_TSMP10            MPP( 30, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP30_TDM_PCLK          MPP( 30, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP30_GE1_RXCTL         MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP30_LCD_D10           MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP31_TSMP11            MPP( 31, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP31_TDM_FS            MPP( 31, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP31_GE1_RXCLK         MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP31_LCD_D11           MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP32_TSMP12            MPP( 32, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP32_TDM_DRX           MPP( 32, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP32_GE1_TCLKOUT       MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP32_LCD_D12           MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP33_GPO               MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
-#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP33_GE1_TXCTL         MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP33_LCD_D13           MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP34_GE1_TXEN          MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP34_LCD_D14           MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP35_GE1_RXERR         MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP35_LCD_D15           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP35_MII0_RXERR        MPP( 35, 0xc, 0, 0, 1,   1,   1,   1,   1 )
-
-#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP36_TSMP0             MPP( 36, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP36_AU_SPDIFI         MPP( 36, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP36_TW1_SDA           MPP( 36, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP37_TSMP1             MPP( 37, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP37_TW1_SCK           MPP( 37, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP38_TSMP2             MPP( 38, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP38_LCD_D18           MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP39_TSMP3             MPP( 39, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP39_LCD_D19           MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP40_TSMP4             MPP( 40, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP40_LCD_D20           MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP41_TSMP5             MPP( 41, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP41_LCD_D21           MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP42_TSMP6             MPP( 42, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP42_LCD_D22           MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP43_TSMP7             MPP( 43, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP43_AU_I2SDI          MPP( 43, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP43_LCD_D23           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP44_TSMP8             MPP( 44, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP44_AU_EXTCLK         MPP( 44, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP44_LCD_CLK           MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP45_TSMP9             MPP( 45, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP45_TDM_PCLK          MPP( 45, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP245_LCD_E            MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP46_TSMP10            MPP( 46, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP46_TDM_FS            MPP( 46, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP46_LCD_HSYNC         MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP47_TSMP11            MPP( 47, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP47_TDM_DRX           MPP( 47, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP47_LCD_VSYNC         MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP48_TSMP12            MPP( 48, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP48_LCD_D16           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
-#define MPP49_GPO               MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
-#define MPP49_TSMP9             MPP( 49, 0x1, 0, 0, 0,   0,   0,   1,   0 )
-#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP49_PTP_CLK           MPP( 49, 0x5, 0, 0, 0,   0,   0,   1,   0 )
-#define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP49_LCD_D17           MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-
-#define MPP_MAX                 49
-
-void kirkwood_mpp_conf(unsigned int *mpp_list);
-
-#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
deleted file mode 100644
index 913d032cdb19..000000000000
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/netxbig_v2-setup.c
- *
- * LaCie 2Big and 5Big Network v2 board setup
- *
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/leds-kirkwood-netxbig.h>
-#include "common.h"
-#include "mpp.h"
-#include "lacie_v2-common.h"
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data netxbig_v2_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-
-static struct mv_sata_platform_data netxbig_v2_sata_data = {
-        .n_ports        = 2,
-};
-
-/*****************************************************************************
- * GPIO keys
- ****************************************************************************/
-
-#define NETXBIG_V2_GPIO_SWITCH_POWER_ON         13
-#define NETXBIG_V2_GPIO_SWITCH_POWER_OFF        15
-#define NETXBIG_V2_GPIO_FUNC_BUTTON             34
-
-#define NETXBIG_V2_SWITCH_POWER_ON              0x1
-#define NETXBIG_V2_SWITCH_POWER_OFF             0x2
-
-static struct gpio_keys_button netxbig_v2_buttons[] = {
-        [0] = {
-                .type           = EV_SW,
-                .code           = NETXBIG_V2_SWITCH_POWER_ON,
-                .gpio           = NETXBIG_V2_GPIO_SWITCH_POWER_ON,
-                .desc           = "Back power switch (on|auto)",
-                .active_low     = 1,
-        },
-        [1] = {
-                .type           = EV_SW,
-                .code           = NETXBIG_V2_SWITCH_POWER_OFF,
-                .gpio           = NETXBIG_V2_GPIO_SWITCH_POWER_OFF,
-                .desc           = "Back power switch (auto|off)",
-                .active_low     = 1,
-        },
-        [2] = {
-                .code           = KEY_OPTION,
-                .gpio           = NETXBIG_V2_GPIO_FUNC_BUTTON,
-                .desc           = "Function button",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data netxbig_v2_button_data = {
-        .buttons        = netxbig_v2_buttons,
-        .nbuttons       = ARRAY_SIZE(netxbig_v2_buttons),
-};
-
-static struct platform_device netxbig_v2_gpio_buttons = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &netxbig_v2_button_data,
-        },
-};
-
-/*****************************************************************************
- * GPIO extension LEDs
- ****************************************************************************/
-
-/*
- * The LEDs are controlled by a CPLD and can be configured through a GPIO
- * extension bus:
- *
- * - address register : bit [0-2] -> GPIO [47-49]
- * - data register    : bit [0-2] -> GPIO [44-46]
- * - enable register  : GPIO 29
- */
-
-static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
-static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
-
-static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
-        .addr           = netxbig_v2_gpio_ext_addr,
-        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
-        .data           = netxbig_v2_gpio_ext_data,
-        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
-        .enable         = 29,
-};
-
-/*
- * Address register selection:
- *
- * addr | register
- * ----------------------------
- *   0  | front LED
- *   1  | front LED brightness
- *   2  | SATA LED brightness
- *   3  | SATA0 LED
- *   4  | SATA1 LED
- *   5  | SATA2 LED
- *   6  | SATA3 LED
- *   7  | SATA4 LED
- *
- * Data register configuration:
- *
- * data | LED brightness
- * -------------------------------------------------
- *   0  | min (off)
- *   -  | -
- *   7  | max
- *
- * data | front LED mode
- * -------------------------------------------------
- *   0  | fix off
- *   1  | fix blue on
- *   2  | fix red on
- *   3  | blink blue on=1 sec and blue off=1 sec
- *   4  | blink red on=1 sec and red off=1 sec
- *   5  | blink blue on=2.5 sec and red on=0.5 sec
- *   6  | blink blue on=1 sec and red on=1 sec
- *   7  | blink blue on=0.5 sec and blue off=2.5 sec
- *
- * data | SATA LED mode
- * -------------------------------------------------
- *   0  | fix off
- *   1  | SATA activity blink
- *   2  | fix red on
- *   3  | blink blue on=1 sec and blue off=1 sec
- *   4  | blink red on=1 sec and red off=1 sec
- *   5  | blink blue on=2.5 sec and red on=0.5 sec
- *   6  | blink blue on=1 sec and red on=1 sec
- *   7  | fix blue on
- */
-
-static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
-        [NETXBIG_LED_OFF]       = 0,
-        [NETXBIG_LED_ON]        = 2,
-        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
-        [NETXBIG_LED_TIMER1]    = 4,
-        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
-};
-
-static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
-        [NETXBIG_LED_OFF]       = 0,
-        [NETXBIG_LED_ON]        = 1,
-        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
-        [NETXBIG_LED_TIMER1]    = 3,
-        [NETXBIG_LED_TIMER2]    = 7,
-};
-
-static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
-        [NETXBIG_LED_OFF]       = 0,
-        [NETXBIG_LED_ON]        = 7,
-        [NETXBIG_LED_SATA]      = 1,
-        [NETXBIG_LED_TIMER1]    = 3,
-        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
-};
-
-static struct netxbig_led_timer netxbig_v2_led_timer[] = {
-        [0] = {
-                .delay_on       = 500,
-                .delay_off      = 500,
-                .mode           = NETXBIG_LED_TIMER1,
-        },
-        [1] = {
-                .delay_on       = 500,
-                .delay_off      = 1000,
-                .mode           = NETXBIG_LED_TIMER2,
-        },
-};
-
-#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
-        { .name         = _name,                                \
-          .mode_addr    = maddr,                                \
-          .mode_val     = mval,                                 \
-          .bright_addr  = baddr }
-
-static struct netxbig_led net2big_v2_leds_ctrl[] = {
-        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
-        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
-        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
-        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
-};
-
-static struct netxbig_led_platform_data net2big_v2_leds_data = {
-        .gpio_ext       = &netxbig_v2_gpio_ext,
-        .timer          = netxbig_v2_led_timer,
-        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
-        .leds           = net2big_v2_leds_ctrl,
-        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
-};
-
-static struct netxbig_led net5big_v2_leds_ctrl[] = {
-        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
-        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
-        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
-        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
-        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
-        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
-        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
-        NETXBIG_LED("net5big-v2:red:sata5",  7, netxbig_v2_red_mled,       2),
-};
-
-static struct netxbig_led_platform_data net5big_v2_leds_data = {
-        .gpio_ext       = &netxbig_v2_gpio_ext,
-        .timer          = netxbig_v2_led_timer,
-        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
-        .leds           = net5big_v2_leds_ctrl,
-        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
-};
-
-static struct platform_device netxbig_v2_leds = {
-        .name           = "leds-netxbig",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &net2big_v2_leds_data,
-        },
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-static unsigned int net2big_v2_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP6_SYSRST_OUTn,
-        MPP7_GPO,               /* Request power-off */
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_GPIO,             /* Rear power switch (on|auto) */
-        MPP14_GPIO,             /* USB fuse alarm */
-        MPP15_GPIO,             /* Rear power switch (auto|off) */
-        MPP16_GPIO,             /* SATA HDD1 power */
-        MPP17_GPIO,             /* SATA HDD2 power */
-        MPP20_SATA1_ACTn,
-        MPP21_SATA0_ACTn,
-        MPP24_GPIO,             /* USB mode select */
-        MPP26_GPIO,             /* USB device vbus */
-        MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* GPIO extension ALE */
-        MPP34_GPIO,             /* Rear Push button */
-        MPP35_GPIO,             /* Inhibit switch power-off */
-        MPP36_GPIO,             /* SATA HDD1 presence */
-        MPP37_GPIO,             /* SATA HDD2 presence */
-        MPP40_GPIO,             /* eSATA presence */
-        MPP44_GPIO,             /* GPIO extension (data 0) */
-        MPP45_GPIO,             /* GPIO extension (data 1) */
-        MPP46_GPIO,             /* GPIO extension (data 2) */
-        MPP47_GPIO,             /* GPIO extension (addr 0) */
-        MPP48_GPIO,             /* GPIO extension (addr 1) */
-        MPP49_GPIO,             /* GPIO extension (addr 2) */
-        0
-};
-
-static unsigned int net5big_v2_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP6_SYSRST_OUTn,
-        MPP7_GPO,               /* Request power-off */
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_GPIO,             /* Rear power switch (on|auto) */
-        MPP14_GPIO,             /* USB fuse alarm */
-        MPP15_GPIO,             /* Rear power switch (auto|off) */
-        MPP16_GPIO,             /* SATA HDD1 power */
-        MPP17_GPIO,             /* SATA HDD2 power */
-        MPP20_GE1_TXD0,
-        MPP21_GE1_TXD1,
-        MPP22_GE1_TXD2,
-        MPP23_GE1_TXD3,
-        MPP24_GE1_RXD0,
-        MPP25_GE1_RXD1,
-        MPP26_GE1_RXD2,
-        MPP27_GE1_RXD3,
-        MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* GPIO extension ALE */
-        MPP30_GE1_RXCTL,
-        MPP31_GE1_RXCLK,
-        MPP32_GE1_TCLKOUT,
-        MPP33_GE1_TXCTL,
-        MPP34_GPIO,             /* Rear Push button */
-        MPP35_GPIO,             /* Inhibit switch power-off */
-        MPP36_GPIO,             /* SATA HDD1 presence */
-        MPP37_GPIO,             /* SATA HDD2 presence */
-        MPP38_GPIO,             /* SATA HDD3 presence */
-        MPP39_GPIO,             /* SATA HDD4 presence */
-        MPP40_GPIO,             /* SATA HDD5 presence */
-        MPP41_GPIO,             /* SATA HDD3 power */
-        MPP42_GPIO,             /* SATA HDD4 power */
-        MPP43_GPIO,             /* SATA HDD5 power */
-        MPP44_GPIO,             /* GPIO extension (data 0) */
-        MPP45_GPIO,             /* GPIO extension (data 1) */
-        MPP46_GPIO,             /* GPIO extension (data 2) */
-        MPP47_GPIO,             /* GPIO extension (addr 0) */
-        MPP48_GPIO,             /* GPIO extension (addr 1) */
-        MPP49_GPIO,             /* GPIO extension (addr 2) */
-        0
-};
-
-#define NETXBIG_V2_GPIO_POWER_OFF               7
-
-static void netxbig_v2_power_off(void)
-{
-        gpio_set_value(NETXBIG_V2_GPIO_POWER_OFF, 1);
-}
-
-static void __init netxbig_v2_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        if (machine_is_net2big_v2())
-                kirkwood_mpp_conf(net2big_v2_mpp_config);
-        else
-                kirkwood_mpp_conf(net5big_v2_mpp_config);
-
-        if (machine_is_net2big_v2())
-                lacie_v2_hdd_power_init(2);
-        else
-                lacie_v2_hdd_power_init(5);
-
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&netxbig_v2_ge00_data);
-        if (machine_is_net5big_v2())
-                kirkwood_ge01_init(&netxbig_v2_ge01_data);
-        kirkwood_sata_init(&netxbig_v2_sata_data);
-        kirkwood_uart0_init();
-        lacie_v2_register_flash();
-        lacie_v2_register_i2c_devices();
-
-        if (machine_is_net5big_v2())
-                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
-        platform_device_register(&netxbig_v2_leds);
-        platform_device_register(&netxbig_v2_gpio_buttons);
-
-        if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
-            gpio_direction_output(NETXBIG_V2_GPIO_POWER_OFF, 0) == 0)
-                pm_power_off = netxbig_v2_power_off;
-        else
-                pr_err("netxbig_v2: failed to configure power-off GPIO\n");
-}
-
-#ifdef CONFIG_MACH_NET2BIG_V2
-MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
-        .atag_offset    = 0x100,
-        .init_machine   = netxbig_v2_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG_V2
-MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
-        .atag_offset    = 0x100,
-        .init_machine   = netxbig_v2_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
deleted file mode 100644
index e5cf84103583..000000000000
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/openrd-setup.c
- *
- * Marvell OpenRD (Base|Client|Ultimate) Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition openrd_nand_parts[] = {
-        {
-                .name           = "u-boot",
-                .offset         = 0,
-                .size           = SZ_1M,
-                .mask_flags     = MTD_WRITEABLE
-        }, {
-                .name           = "uImage",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_4M
-        }, {
-                .name           = "root",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = MTDPART_SIZ_FULL
-        },
-};
-
-static struct mv643xx_eth_platform_data openrd_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data openrd_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(24),
-};
-
-static struct mv_sata_platform_data openrd_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct mvsdio_platform_data openrd_mvsdio_data = {
-        .gpio_card_detect = 29, /* MPP29 used as SD card detect */
-        .gpio_write_protect = -1,
-};
-
-static unsigned int openrd_mpp_config[] __initdata = {
-        MPP12_SD_CLK,
-        MPP13_SD_CMD,
-        MPP14_SD_D0,
-        MPP15_SD_D1,
-        MPP16_SD_D2,
-        MPP17_SD_D3,
-        MPP28_GPIO,
-        MPP29_GPIO,
-        MPP34_GPIO,
-        0
-};
-
-/* Configure MPP for UART1 */
-static unsigned int openrd_uart1_mpp_config[] __initdata = {
-        MPP13_UART1_TXD,
-        MPP14_UART1_RXD,
-        0
-};
-
-static struct i2c_board_info i2c_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("cs42l51", 0x4a),
-        },
-};
-
-static struct platform_device openrd_client_audio_device = {
-        .name           = "openrd-client-audio",
-        .id             = -1,
-};
-
-static int __initdata uart1;
-
-static int __init sd_uart_selection(char *str)
-{
-        uart1 = -EINVAL;
-
-        /* Default is SD. Change if required, for UART */
-        if (!str)
-                return 0;
-
-        if (!strncmp(str, "232", 3)) {
-                uart1 = 232;
-        } else if (!strncmp(str, "485", 3)) {
-                /* OpenRD-Base doesn't have RS485. Treat is as an
-                 * unknown argument & just have default setting -
-                 * which is SD */
-                if (machine_is_openrd_base()) {
-                        uart1 = -ENODEV;
-                        return 1;
-                }
-
-                uart1 = 485;
-        }
-        return 1;
-}
-/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
-__setup("kw_openrd_init_uart1=", sd_uart_selection);
-
-static int __init uart1_mpp_config(void)
-{
-        kirkwood_mpp_conf(openrd_uart1_mpp_config);
-
-        if (gpio_request(34, "SD_UART1_SEL")) {
-                pr_err("GPIO request 34 failed for SD/UART1 selection\n");
-                return -EIO;
-        }
-
-        if (gpio_request(28, "RS232_RS485_SEL")) {
-                pr_err("GPIO request 28 failed for RS232/RS485 selection\n");
-                gpio_free(34);
-                return -EIO;
-        }
-
-        /* Select UART1
-         * Pin # 34: 0 => UART1, 1 => SD */
-        gpio_direction_output(34, 0);
-
-        /* Select RS232 OR RS485
-         * Pin # 28: 0 => RS232, 1 => RS485 */
-        if (uart1 == 232)
-                gpio_direction_output(28, 0);
-        else
-                gpio_direction_output(28, 1);
-
-        gpio_free(34);
-        gpio_free(28);
-
-        return 0;
-}
-
-static void __init openrd_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(openrd_mpp_config);
-
-        kirkwood_uart0_init();
-        kirkwood_nand_init(openrd_nand_parts, ARRAY_SIZE(openrd_nand_parts),
-                           25);
-
-        kirkwood_ehci_init();
-
-        if (machine_is_openrd_ultimate()) {
-                openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-                openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
-        }
-
-        kirkwood_ge00_init(&openrd_ge00_data);
-        if (!machine_is_openrd_base())
-                kirkwood_ge01_init(&openrd_ge01_data);
-
-        kirkwood_sata_init(&openrd_sata_data);
-
-        kirkwood_i2c_init();
-
-        if (machine_is_openrd_client() || machine_is_openrd_ultimate()) {
-                platform_device_register(&openrd_client_audio_device);
-                i2c_register_board_info(0, i2c_board_info,
-                        ARRAY_SIZE(i2c_board_info));
-                kirkwood_audio_init();
-        }
-
-        if (uart1 <= 0) {
-                if (uart1 < 0)
-                        pr_err("Invalid kernel parameter to select UART1. Defaulting to SD. ERROR CODE: %d\n",
-                               uart1);
-
-                /* Select SD
-                 * Pin # 34: 0 => UART1, 1 => SD */
-                if (gpio_request(34, "SD_UART1_SEL")) {
-                        pr_err("GPIO request 34 failed for SD/UART1 selection\n");
-                } else {
-
-                        gpio_direction_output(34, 1);
-                        gpio_free(34);
-                        kirkwood_sdio_init(&openrd_mvsdio_data);
-                }
-        } else {
-                if (!uart1_mpp_config())
-                        kirkwood_uart1_init();
-        }
-}
-
-static int __init openrd_pci_init(void)
-{
-        if (machine_is_openrd_base() ||
-            machine_is_openrd_client() ||
-            machine_is_openrd_ultimate())
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(openrd_pci_init);
-
-#ifdef CONFIG_MACH_OPENRD_BASE
-MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
-        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = openrd_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_CLIENT
-MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
-        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = openrd_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_ULTIMATE
-MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
-        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = openrd_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
deleted file mode 100644
index 12d86f39f380..000000000000
--- a/arch/arm/mach-kirkwood/pcie.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/pcie.c
- *
- * PCIe functions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/mbus.h>
-#include <video/vga.h>
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <plat/pcie.h>
-#include <mach/bridge-regs.h>
-#include "common.h"
-
-/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
-#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET    0x4
-#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR      0xe8
-#define KIRKWOOD_MBUS_PCIE0_IO_TARGET     0x4
-#define KIRKWOOD_MBUS_PCIE0_IO_ATTR       0xe0
-#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET    0x4
-#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR      0xd8
-#define KIRKWOOD_MBUS_PCIE1_IO_TARGET     0x4
-#define KIRKWOOD_MBUS_PCIE1_IO_ATTR       0xd0
-
-static void kirkwood_enable_pcie_clk(const char *port)
-{
-        struct clk *clk;
-
-        clk = clk_get_sys("pcie", port);
-        if (IS_ERR(clk)) {
-                pr_err("PCIE clock %s missing\n", port);
-                return;
-        }
-        clk_prepare_enable(clk);
-        clk_put(clk);
-}
-
-/* This function is called very early in the boot when probing the
-   hardware to determine what we actually are, and what rate tclk is
-   ticking at. Hence calling kirkwood_enable_pcie_clk() is not
-   possible since the clk tree has not been created yet. */
-void kirkwood_enable_pcie(void)
-{
-        u32 curr = readl(CLOCK_GATING_CTRL);
-        if (!(curr & CGC_PEX0))
-                writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
-}
-
-void kirkwood_pcie_id(u32 *dev, u32 *rev)
-{
-        kirkwood_enable_pcie();
-        *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
-        *rev = orion_pcie_rev(PCIE_VIRT_BASE);
-}
-
-struct pcie_port {
-        u8                      root_bus_nr;
-        void __iomem            *base;
-        spinlock_t              conf_lock;
-        int                     irq;
-        struct resource         res;
-};
-
-static int pcie_port_map[2];
-static int num_pcie_ports;
-
-static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
-{
-        /*
-         * Don't go out when trying to access --
-         * 1. nonexisting device on local bus
-         * 2. where there's no device connected (no link)
-         */
-        if (bus == pp->root_bus_nr && dev == 0)
-                return 1;
-
-        if (!orion_pcie_link_up(pp->base))
-                return 0;
-
-        if (bus == pp->root_bus_nr && dev != 1)
-                return 0;
-
-        return 1;
-}
-
-
-/*
- * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
- * and then reading the PCIE_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-
-static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-                        int size, u32 *val)
-{
-        struct pci_sys_data *sys = bus->sysdata;
-        struct pcie_port *pp = sys->private_data;
-        unsigned long flags;
-        int ret;
-
-        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
-                *val = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-
-        spin_lock_irqsave(&pp->conf_lock, flags);
-        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&pp->conf_lock, flags);
-
-        return ret;
-}
-
-static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
-                        int where, int size, u32 val)
-{
-        struct pci_sys_data *sys = bus->sysdata;
-        struct pcie_port *pp = sys->private_data;
-        unsigned long flags;
-        int ret;
-
-        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        spin_lock_irqsave(&pp->conf_lock, flags);
-        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&pp->conf_lock, flags);
-
-        return ret;
-}
-
-static struct pci_ops pcie_ops = {
-        .read = pcie_rd_conf,
-        .write = pcie_wr_conf,
-};
-
-static void __init pcie0_ioresources_init(struct pcie_port *pp)
-{
-        pp->base = PCIE_VIRT_BASE;
-        pp->irq = IRQ_KIRKWOOD_PCIE;
-
-        /*
-         * IORESOURCE_MEM
-         */
-        pp->res.name = "PCIe 0 MEM";
-        pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
-        pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-        pp->res.flags = IORESOURCE_MEM;
-}
-
-static void __init pcie1_ioresources_init(struct pcie_port *pp)
-{
-        pp->base = PCIE1_VIRT_BASE;
-        pp->irq = IRQ_KIRKWOOD_PCIE1;
-
-        /*
-         * IORESOURCE_MEM
-         */
-        pp->res.name = "PCIe 1 MEM";
-        pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
-        pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
-        pp->res.flags = IORESOURCE_MEM;
-}
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-        struct pcie_port *pp;
-        int index;
-
-        if (nr >= num_pcie_ports)
-                return 0;
-
-        index = pcie_port_map[nr];
-        pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
-
-        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
-        if (!pp)
-                panic("PCIe: failed to allocate pcie_port data");
-        sys->private_data = pp;
-        pp->root_bus_nr = sys->busnr;
-        spin_lock_init(&pp->conf_lock);
-
-        switch (index) {
-        case 0:
-                kirkwood_enable_pcie_clk("0");
-                pcie0_ioresources_init(pp);
-                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
-                break;
-        case 1:
-                kirkwood_enable_pcie_clk("1");
-                pcie1_ioresources_init(pp);
-                pci_ioremap_io(SZ_64K * sys->busnr,
-                               KIRKWOOD_PCIE1_IO_PHYS_BASE);
-                break;
-        default:
-                panic("PCIe setup: invalid controller %d", index);
-        }
-
-        if (request_resource(&iomem_resource, &pp->res))
-                panic("Request PCIe%d Memory resource failed\n", index);
-
-        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
-
-        /*
-         * Generic PCIe unit setup.
-         */
-        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-
-        orion_pcie_setup(pp->base);
-
-        return 1;
-}
-
-/*
- * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
- * is operating as a root complex this needs to be switched to
- * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
- * the device. Decoding setup is handled by the orion code.
- */
-static void rc_pci_fixup(struct pci_dev *dev)
-{
-        if (dev->bus->parent == NULL && dev->devfn == 0) {
-                int i;
-
-                dev->class &= 0xff;
-                dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
-                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-                        dev->resource[i].start = 0;
-                        dev->resource[i].end   = 0;
-                        dev->resource[i].flags = 0;
-                }
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
-
-static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
-        u8 pin)
-{
-        struct pci_sys_data *sys = dev->sysdata;
-        struct pcie_port *pp = sys->private_data;
-
-        return pp->irq;
-}
-
-static struct hw_pci kirkwood_pci __initdata = {
-        .setup          = kirkwood_pcie_setup,
-        .map_irq        = kirkwood_pcie_map_irq,
-        .ops            = &pcie_ops,
-};
-
-static void __init add_pcie_port(int index, void __iomem *base)
-{
-        pcie_port_map[num_pcie_ports++] = index;
-        pr_info("Kirkwood PCIe port %d: link %s\n", index,
-                orion_pcie_link_up(base) ? "up" : "down");
-}
-
-void __init kirkwood_pcie_init(unsigned int portmask)
-{
-        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
-                                          KIRKWOOD_MBUS_PCIE0_IO_ATTR,
-                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE);
-        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
-                                    KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
-                                    KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                    KIRKWOOD_PCIE_MEM_SIZE);
-        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
-                                          KIRKWOOD_MBUS_PCIE1_IO_ATTR,
-                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE);
-        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
-                                    KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
-                                    KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                    KIRKWOOD_PCIE1_MEM_SIZE);
-
-        vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
-
-        if (portmask & KW_PCIE0)
-                add_pcie_port(0, PCIE_VIRT_BASE);
-
-        if (portmask & KW_PCIE1)
-                add_pcie_port(1, PCIE1_VIRT_BASE);
-
-        kirkwood_pci.nr_controllers = num_pcie_ports;
-        pci_common_init(&kirkwood_pci);
-}
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
deleted file mode 100644
index 8e5e0329d04c..000000000000
--- a/arch/arm/mach-kirkwood/pm.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Power Management driver for Marvell Kirkwood SoCs
- *
- * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License,
- * version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <mach/bridge-regs.h>
-#include "common.h"
-
-static void __iomem *ddr_operation_base;
-static void __iomem *memory_pm_ctrl;
-
-static void kirkwood_low_power(void)
-{
-        u32 mem_pm_ctrl;
-
-        mem_pm_ctrl = readl(memory_pm_ctrl);
-
-        /* Set peripherals to low-power mode */
-        writel_relaxed(~0, memory_pm_ctrl);
-
-        /* Set DDR in self-refresh */
-        writel_relaxed(0x7, ddr_operation_base);
-
-        /*
-         * Set CPU in wait-for-interrupt state.
-         * This disables the CPU core clocks,
-         * the array clocks, and also the L2 controller.
-         */
-        cpu_do_idle();
-
-        writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
-}
-
-static int kirkwood_suspend_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-                kirkwood_low_power();
-                break;
-        default:
-                return -EINVAL;
-        }
-        return 0;
-}
-
-static int kirkwood_pm_valid_standby(suspend_state_t state)
-{
-        return state == PM_SUSPEND_STANDBY;
-}
-
-static const struct platform_suspend_ops kirkwood_suspend_ops = {
-        .enter = kirkwood_suspend_enter,
-        .valid = kirkwood_pm_valid_standby,
-};
-
-void __init kirkwood_pm_init(void)
-{
-        ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
-        memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
-
-        suspend_set_ops(&kirkwood_suspend_ops);
-}
diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h
deleted file mode 100644
index 21e7530f368b..000000000000
--- a/arch/arm/mach-kirkwood/pm.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Power Management driver for Marvell Kirkwood SoCs
- *
- * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License,
- * version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_KIRKWOOD_PM_H
-#define __ARCH_KIRKWOOD_PM_H
-
-#ifdef CONFIG_PM
-void kirkwood_pm_init(void);
-#else
-static inline void kirkwood_pm_init(void) {};
-#endif
-
-#endif
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
deleted file mode 100644
index e4fd3129d36f..000000000000
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
- *
- * Marvell RD-88F6192-NAS Reference Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <plat/orion-gpio.h>
-#include "common.h"
-
-#define RD88F6192_GPIO_USB_VBUS         10
-
-static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data rd88f6192_sata_data = {
-        .n_ports        = 2,
-};
-
-static const struct flash_platform_data rd88F6192_spi_slave_data = {
-        .type           = "m25p128",
-};
-
-static struct spi_board_info __initdata rd88F6192_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &rd88F6192_spi_slave_data,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
-
-static void __init rd88f6192_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-
-        orion_gpio_set_valid(RD88F6192_GPIO_USB_VBUS, 1);
-        if (gpio_request(RD88F6192_GPIO_USB_VBUS, "USB VBUS") != 0 ||
-            gpio_direction_output(RD88F6192_GPIO_USB_VBUS, 1) != 0)
-                pr_err("RD-88F6192-NAS: failed to setup USB VBUS GPIO\n");
-
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&rd88f6192_ge00_data);
-        kirkwood_sata_init(&rd88f6192_sata_data);
-        spi_register_board_info(rd88F6192_spi_slave_info,
-                                ARRAY_SIZE(rd88F6192_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_uart0_init();
-}
-
-static int __init rd88f6192_pci_init(void)
-{
-        if (machine_is_rd88f6192_nas())
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(rd88f6192_pci_init);
-
-MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
-        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = rd88f6192_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
deleted file mode 100644
index 5154bd2a3ad3..000000000000
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/rd88f6281-setup.c
- *
- * Marvell RD-88F6281 Reference Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition rd88f6281_nand_parts[] = {
-        {
-                .name = "u-boot",
-                .offset = 0,
-                .size = SZ_1M
-        }, {
-                .name = "uImage",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = SZ_2M
-        }, {
-                .name = "root",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = MTDPART_SIZ_FULL
-        },
-};
-
-static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_NONE,
-        .speed          = SPEED_1000,
-        .duplex         = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data rd88f6281_switch_chip_data = {
-        .port_names[0]  = "lan1",
-        .port_names[1]  = "lan2",
-        .port_names[2]  = "lan3",
-        .port_names[3]  = "lan4",
-        .port_names[5]  = "cpu",
-};
-
-static struct dsa_platform_data rd88f6281_switch_plat_data = {
-        .nr_chips       = 1,
-        .chip           = &rd88f6281_switch_chip_data,
-};
-
-static struct mv643xx_eth_platform_data rd88f6281_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
-};
-
-static struct mv_sata_platform_data rd88f6281_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
-        .gpio_card_detect = 28,
-        .gpio_write_protect = -1,
-};
-
-static unsigned int rd88f6281_mpp_config[] __initdata = {
-        MPP28_GPIO,
-        0
-};
-
-static void __init rd88f6281_init(void)
-{
-        u32 dev, rev;
-
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(rd88f6281_mpp_config);
-
-        kirkwood_nand_init(rd88f6281_nand_parts,
-                           ARRAY_SIZE(rd88f6281_nand_parts),
-                           25);
-        kirkwood_ehci_init();
-
-        kirkwood_ge00_init(&rd88f6281_ge00_data);
-        kirkwood_pcie_id(&dev, &rev);
-        if (rev == MV88F6281_REV_A0) {
-                rd88f6281_switch_chip_data.sw_addr = 10;
-                kirkwood_ge01_init(&rd88f6281_ge01_data);
-        } else {
-                rd88f6281_switch_chip_data.port_names[4] = "wan";
-        }
-        kirkwood_ge00_switch_init(&rd88f6281_switch_plat_data, NO_IRQ);
-
-        kirkwood_sata_init(&rd88f6281_sata_data);
-        kirkwood_sdio_init(&rd88f6281_mvsdio_data);
-        kirkwood_uart0_init();
-}
-
-static int __init rd88f6281_pci_init(void)
-{
-        if (machine_is_rd88f6281())
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(rd88f6281_pci_init);
-
-MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
-        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = rd88f6281_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
deleted file mode 100644
index 8736f8c97518..000000000000
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- *
- * HP t5325 Thin Client setup
- *
- * Copyright (C) 2010  Martin Michlmayr <tbm@cyrius.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <sound/alc5623.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition hp_t5325_partitions[] = {
-        {
-                .name           = "u-boot env",
-                .size           = SZ_64K,
-                .offset         = SZ_512K + SZ_256K,
-        },
-        {
-                .name           = "permanent u-boot env",
-                .size           = SZ_64K,
-                .offset         = MTDPART_OFS_APPEND,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "HP env",
-                .size           = SZ_64K,
-                .offset         = MTDPART_OFS_APPEND,
-        },
-        {
-                .name           = "u-boot",
-                .size           = SZ_512K,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "SSD firmware",
-                .size           = SZ_256K,
-                .offset         = SZ_512K,
-        },
-};
-
-static const struct flash_platform_data hp_t5325_flash = {
-        .type           = "mx25l8005",
-        .name           = "spi_flash",
-        .parts          = hp_t5325_partitions,
-        .nr_parts       = ARRAY_SIZE(hp_t5325_partitions),
-};
-
-static struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &hp_t5325_flash,
-                .irq            = -1,
-        },
-};
-
-static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data hp_t5325_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct gpio_keys_button hp_t5325_buttons[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = 45,
-                .desc           = "Power",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data hp_t5325_button_data = {
-        .buttons        = hp_t5325_buttons,
-        .nbuttons       = ARRAY_SIZE(hp_t5325_buttons),
-};
-
-static struct platform_device hp_t5325_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &hp_t5325_button_data,
-        }
-};
-
-static struct platform_device hp_t5325_audio_device = {
-        .name           = "t5325-audio",
-        .id             = -1,
-};
-
-static unsigned int hp_t5325_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP6_SYSRST_OUTn,
-        MPP7_SPI_SCn,
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP12_SD_CLK,
-        MPP13_GPIO,
-        MPP14_GPIO,
-        MPP15_GPIO,
-        MPP16_GPIO,
-        MPP17_GPIO,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP20_GPIO,
-        MPP21_GPIO,
-        MPP22_GPIO,
-        MPP23_GPIO,
-        MPP32_GPIO,
-        MPP33_GE1_TXCTL,
-        MPP39_AU_I2SBCLK,
-        MPP40_AU_I2SDO,
-        MPP43_AU_I2SDI,
-        MPP41_AU_I2SLRCLK,
-        MPP42_AU_I2SMCLK,
-        MPP45_GPIO,             /* Power button */
-        MPP48_GPIO,             /* Board power off */
-        0
-};
-
-static struct alc5623_platform_data alc5621_data = {
-        .add_ctrl = 0x3700,
-        .jack_det_ctrl = 0x4810,
-};
-
-static struct i2c_board_info i2c_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("alc5621", 0x1a),
-                .platform_data = &alc5621_data,
-        },
-};
-
-#define HP_T5325_GPIO_POWER_OFF         48
-
-static void hp_t5325_power_off(void)
-{
-        gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
-}
-
-static void __init hp_t5325_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(hp_t5325_mpp_config);
-
-        kirkwood_uart0_init();
-        spi_register_board_info(hp_t5325_spi_slave_info,
-                                ARRAY_SIZE(hp_t5325_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        kirkwood_ge00_init(&hp_t5325_ge00_data);
-        kirkwood_sata_init(&hp_t5325_sata_data);
-        kirkwood_ehci_init();
-        platform_device_register(&hp_t5325_button_device);
-        platform_device_register(&hp_t5325_audio_device);
-
-        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
-        kirkwood_audio_init();
-
-        if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
-            gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
-                pm_power_off = hp_t5325_power_off;
-        else
-                pr_err("t5325: failed to configure power-off GPIO\n");
-}
-
-static int __init hp_t5325_pci_init(void)
-{
-        if (machine_is_t5325())
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(hp_t5325_pci_init);
-
-MACHINE_START(T5325, "HP t5325 Thin Client")
-        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = hp_t5325_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
deleted file mode 100644
index e1267d6b468f..000000000000
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- *
- * QNAP TS-11x/TS-21x Turbo NAS Board Setup
- *
- * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
- * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-#include "mpp.h"
-#include "tsx1x-common.h"
-
-static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = {
-        I2C_BOARD_INFO("s35390a", 0x30),
-};
-
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data qnap_ts219_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct gpio_keys_button qnap_ts219_buttons[] = {
-        {
-                .code           = KEY_COPY,
-                .gpio           = 15,
-                .desc           = "USB Copy",
-                .active_low     = 1,
-        },
-        {
-                .code           = KEY_RESTART,
-                .gpio           = 16,
-                .desc           = "Reset",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data qnap_ts219_button_data = {
-        .buttons        = qnap_ts219_buttons,
-        .nbuttons       = ARRAY_SIZE(qnap_ts219_buttons),
-};
-
-static struct platform_device qnap_ts219_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &qnap_ts219_button_data,
-        }
-};
-
-static unsigned int qnap_ts219_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP4_SATA1_ACTn,
-        MPP5_SATA0_ACTn,
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_UART1_TXD,        /* PIC controller */
-        MPP14_UART1_RXD,        /* PIC controller */
-        MPP15_GPIO,             /* USB Copy button (on devices with 88F6281) */
-        MPP16_GPIO,             /* Reset button (on devices with 88F6281) */
-        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
-        MPP37_GPIO,             /* Reset button (on devices with 88F6282) */
-        MPP43_GPIO,             /* USB Copy button (on devices with 88F6282) */
-        MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
-        0
-};
-
-static void __init qnap_ts219_init(void)
-{
-        u32 dev, rev;
-
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(qnap_ts219_mpp_config);
-
-        kirkwood_uart0_init();
-        kirkwood_uart1_init(); /* A PIC controller is connected here. */
-        qnap_tsx1x_register_flash();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
-
-        kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6282_DEV_ID) {
-                qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
-                qnap_ts219_buttons[1].gpio = 37; /* Reset button */
-                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-        }
-
-        kirkwood_ge00_init(&qnap_ts219_ge00_data);
-        kirkwood_sata_init(&qnap_ts219_sata_data);
-        kirkwood_ehci_init();
-        platform_device_register(&qnap_ts219_button_device);
-
-        pm_power_off = qnap_tsx1x_power_off;
-
-}
-
-static int __init ts219_pci_init(void)
-{
-        if (machine_is_ts219())
-                kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(ts219_pci_init);
-
-MACHINE_START(TS219, "QNAP TS-119/TS-219")
-        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = qnap_ts219_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
deleted file mode 100644
index 81d585806b2f..000000000000
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *
- * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
- *
- * Copyright (C) 2009-2010  Martin Michlmayr <tbm@cyrius.com>
- * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-#include "mpp.h"
-#include "tsx1x-common.h"
-
-/* for the PCIe reset workaround */
-#include <plat/pcie.h>
-
-
-#define QNAP_TS41X_JUMPER_JP1   45
-
-static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
-        I2C_BOARD_INFO("s35390a", 0x30),
-};
-
-static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv_sata_platform_data qnap_ts41x_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct gpio_keys_button qnap_ts41x_buttons[] = {
-        {
-                .code           = KEY_COPY,
-                .gpio           = 43,
-                .desc           = "USB Copy",
-                .active_low     = 1,
-        },
-        {
-                .code           = KEY_RESTART,
-                .gpio           = 37,
-                .desc           = "Reset",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data qnap_ts41x_button_data = {
-        .buttons        = qnap_ts41x_buttons,
-        .nbuttons       = ARRAY_SIZE(qnap_ts41x_buttons),
-};
-
-static struct platform_device qnap_ts41x_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &qnap_ts41x_button_data,
-        }
-};
-
-static unsigned int qnap_ts41x_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP6_SYSRST_OUTn,
-        MPP7_PEX_RST_OUTn,
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_UART1_TXD,        /* PIC controller */
-        MPP14_UART1_RXD,        /* PIC controller */
-        MPP15_SATA0_ACTn,
-        MPP16_SATA1_ACTn,
-        MPP20_GE1_TXD0,
-        MPP21_GE1_TXD1,
-        MPP22_GE1_TXD2,
-        MPP23_GE1_TXD3,
-        MPP24_GE1_RXD0,
-        MPP25_GE1_RXD1,
-        MPP26_GE1_RXD2,
-        MPP27_GE1_RXD3,
-        MPP30_GE1_RXCTL,
-        MPP31_GE1_RXCLK,
-        MPP32_GE1_TCLKOUT,
-        MPP33_GE1_TXCTL,
-        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
-        MPP37_GPIO,             /* Reset button */
-        MPP43_GPIO,             /* USB Copy button */
-        MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
-        MPP45_GPIO,             /* JP1: 0: LCD, 1: serial console */
-        MPP46_GPIO,             /* External SATA HDD1 error indicator */
-        MPP47_GPIO,             /* External SATA HDD2 error indicator */
-        MPP48_GPIO,             /* External SATA HDD3 error indicator */
-        MPP49_GPIO,             /* External SATA HDD4 error indicator */
-        0
-};
-
-static void __init qnap_ts41x_init(void)
-{
-        u32 dev, rev;
-
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(qnap_ts41x_mpp_config);
-
-        kirkwood_uart0_init();
-        kirkwood_uart1_init(); /* A PIC controller is connected here. */
-        qnap_tsx1x_register_flash();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
-
-        kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6282_DEV_ID) {
-                qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-                qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
-        }
-        kirkwood_ge00_init(&qnap_ts41x_ge00_data);
-        kirkwood_ge01_init(&qnap_ts41x_ge01_data);
-
-        kirkwood_sata_init(&qnap_ts41x_sata_data);
-        kirkwood_ehci_init();
-        platform_device_register(&qnap_ts41x_button_device);
-
-        pm_power_off = qnap_tsx1x_power_off;
-
-        if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
-                gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
-}
-
-static int __init ts41x_pci_init(void)
-{
-        if (machine_is_ts41x()) {
-                u32 dev, rev;
-
-                /*
-                 * Without this explicit reset, the PCIe SATA controller
-                 * (Marvell 88sx7042/sata_mv) is known to stop working
-                 * after a few minutes.
-                 */
-                orion_pcie_reset(PCIE_VIRT_BASE);
-
-                kirkwood_pcie_id(&dev, &rev);
-                if (dev == MV88F6282_DEV_ID)
-                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-                else
-                        kirkwood_pcie_init(KW_PCIE0);
-        }
-        return 0;
-}
-subsys_initcall(ts41x_pci_init);
-
-MACHINE_START(TS41X, "QNAP TS-41x")
-        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = qnap_ts41x_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
deleted file mode 100644
index cec87cef76ca..000000000000
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ /dev/null
@@ -1,113 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/serial_reg.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-#include "tsx1x-common.h"
-
-/*
- * QNAP TS-x1x Boards flash
- */
-
-/****************************************************************************
- * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatibility with
- *     the QNAP firmware.
- * Layout as used by QNAP:
- *  0x00000000-0x00080000 : "U-Boot"
- *  0x00200000-0x00400000 : "Kernel"
- *  0x00400000-0x00d00000 : "RootFS"
- *  0x00d00000-0x01000000 : "RootFS2"
- *  0x00080000-0x000c0000 : "U-Boot Config"
- *  0x000c0000-0x00200000 : "NAS Config"
- *
- * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
- * used by the QNAP TS-109/TS-209.
- *
- ***************************************************************************/
-
-static struct mtd_partition qnap_tsx1x_partitions[] = {
-        {
-                .name           = "U-Boot",
-                .size           = 0x00080000,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,
-        }, {
-                .name           = "Kernel",
-                .size           = 0x00200000,
-                .offset         = 0x00200000,
-        }, {
-                .name           = "RootFS1",
-                .size           = 0x00900000,
-                .offset         = 0x00400000,
-        }, {
-                .name           = "RootFS2",
-                .size           = 0x00300000,
-                .offset         = 0x00d00000,
-        }, {
-                .name           = "U-Boot Config",
-                .size           = 0x00040000,
-                .offset         = 0x00080000,
-        }, {
-                .name           = "NAS Config",
-                .size           = 0x00140000,
-                .offset         = 0x000c0000,
-        },
-};
-
-static const struct flash_platform_data qnap_tsx1x_flash = {
-        .type           = "m25p128",
-        .name           = "spi_flash",
-        .parts          = qnap_tsx1x_partitions,
-        .nr_parts       = ARRAY_SIZE(qnap_tsx1x_partitions),
-};
-
-static struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &qnap_tsx1x_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
-
-void __init qnap_tsx1x_register_flash(void)
-{
-        spi_register_board_info(qnap_tsx1x_spi_slave_info,
-                                ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
-        kirkwood_spi_init();
-}
-
-
-/*****************************************************************************
- * QNAP TS-x1x specific power off method via UART1-attached PIC
- ****************************************************************************/
-
-#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-void qnap_tsx1x_power_off(void)
-{
-        /* 19200 baud divisor */
-        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
-
-        pr_info("%s: triggering power-off...\n", __func__);
-
-        /* hijack UART1 and reset into sane state (19200,8n1) */
-        writel(0x83, UART1_REG(LCR));
-        writel(divisor & 0xff, UART1_REG(DLL));
-        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
-        writel(0x03, UART1_REG(LCR));
-        writel(0x00, UART1_REG(IER));
-        writel(0x00, UART1_REG(FCR));
-        writel(0x00, UART1_REG(MCR));
-
-        /* send the power-off command 'A' to PIC */
-        writel('A', UART1_REG(TX));
-}
-
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
deleted file mode 100644
index 7fa037361b55..000000000000
--- a/arch/arm/mach-kirkwood/tsx1x-common.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
-#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
-
-extern void __init qnap_tsx1x_register_flash(void);
-extern void qnap_tsx1x_power_off(void);
-
-#endif
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
new file mode 100644
index 000000000000..2c043a210db0
--- /dev/null
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -0,0 +1,6 @@
+config ARCH_MEDIATEK
+        bool "Mediatek MT6589 SoC" if ARCH_MULTI_V7
+        select ARM_GIC
+        select MTK_TIMER
+        help
+          Support for Mediatek Cortex-A7 Quad-Core-SoC MT6589.
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
new file mode 100644
index 000000000000..43e619f56172
--- /dev/null
+++ b/arch/arm/mach-mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-mediatek/mediatek.c
index 201842a3769e..f2acf075350d 100644
--- a/arch/arm/mach-s5pv210/include/mach/dma.h
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -1,6 +1,8 @@
 /*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
+ * Device Tree support for Mediatek SoCs
+ *
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <matthias.bgg@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -11,16 +13,15 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
+#include <linux/init.h>
+#include <asm/mach/arch.h>
 
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* This platform uses the common DMA API driver for PL330 */
-#include <plat/dma-pl330.h>
+static const char * const mediatek_board_dt_compat[] = {
+        "mediatek,mt6589",
+        NULL,
+};
 
-#endif /* __MACH_DMA_H */
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+        .dt_compat      = mediatek_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index b9bc599a5fd0..c1e4567a5ab3 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -14,11 +14,15 @@ menuconfig ARCH_MVEBU
 
 if ARCH_MVEBU
 
+config MACH_MVEBU_ANY
+        bool
+
 config MACH_MVEBU_V7
         bool
         select ARMADA_370_XP_TIMER
         select CACHE_L2X0
         select ARM_CPU_SUSPEND
+        select MACH_MVEBU_ANY
 
 config MACH_ARMADA_370
         bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
@@ -75,6 +79,7 @@ config MACH_DOVE
         select CACHE_L2X0
         select CPU_PJ4
         select DOVE_CLK
+        select MACH_MVEBU_ANY
         select ORION_IRQCHIP
         select ORION_TIMER
         select PINCTRL_DOVE
@@ -87,6 +92,7 @@ config MACH_KIRKWOOD
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select KIRKWOOD_CLK
+        select MACH_MVEBU_ANY
         select ORION_IRQCHIP
         select ORION_TIMER
         select PCI
@@ -96,4 +102,11 @@ config MACH_KIRKWOOD
           Say 'Y' here if you want your kernel to support boards based
           on the Marvell Kirkwood device tree.
 
+config MACH_NETXBIG
+        bool "LaCie 2Big and 5Big Network v2"
+        depends on MACH_KIRKWOOD
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big and 5Big Network v2
+
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 1636cdbef01a..e24136b42765 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -4,13 +4,13 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
 CFLAGS_pmsu.o                   := -march=armv7-a
 
-obj-y                            += system-controller.o mvebu-soc-id.o
+obj-$(CONFIG_MACH_MVEBU_ANY)     += system-controller.o mvebu-soc-id.o
 
 ifeq ($(CONFIG_MACH_MVEBU_V7),y)
 obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
-obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
 endif
 
 obj-$(CONFIG_MACH_DOVE)          += dove.o
 obj-$(CONFIG_MACH_KIRKWOOD)      += kirkwood.o kirkwood-pm.o
+obj-$(CONFIG_MACH_NETXBIG)       += netxbig.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c3465f5b1250..84cd90d9b860 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -24,4 +24,6 @@ void armada_xp_secondary_startup(void);
 extern struct smp_operations armada_xp_smp_ops;
 #endif
 
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
+
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index b2524d689f21..6478626e3ff6 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -34,14 +34,14 @@
 #include "coherency.h"
 #include "mvebu-soc-id.h"
 
+static void __iomem *scu_base;
+
 /*
  * Enables the SCU when available. Obviously, this is only useful on
  * Cortex-A based SOCs, not on PJ4B based ones.
  */
 static void __init mvebu_scu_enable(void)
 {
-        void __iomem *scu_base;
-
         struct device_node *np =
                 of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
         if (np) {
@@ -51,6 +51,11 @@ static void __init mvebu_scu_enable(void)
         }
 }
 
+void __iomem *mvebu_get_scu_base(void)
+{
+        return scu_base;
+}
+
 /*
  * Early versions of Armada 375 SoC have a bug where the BootROM
  * leaves an external data abort pending. The kernel is hit by this
@@ -125,8 +130,16 @@ static void __init thermal_quirk(void)
 {
         struct device_node *np;
         u32 dev, rev;
+        int res;
 
-        if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
+        /*
+         * The early SoC Z1 revision needs a quirk to be applied in order
+         * for the thermal controller to work properly. This quirk breaks
+         * the thermal support if applied on a SoC that doesn't need it,
+         * so we enforce the SoC revision to be known.
+         */
+        res = mvebu_get_soc_id(&dev, &rev);
+        if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
                 return;
 
         for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
@@ -160,7 +173,8 @@ static void __init thermal_quirk(void)
 
                 /*
                  * The thermal controller needs some quirk too, so let's change
-                 * the compatible string to reflect this.
+                 * the compatible string to reflect this and allow the driver
+                 * the take the necessary action.
                  */
                 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
                 prop->name = kstrdup("compatible", GFP_KERNEL);
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
index 9c7bb4386f8b..98e32cc2ef3d 100644
--- a/arch/arm/mach-mvebu/board.h
+++ b/arch/arm/mach-mvebu/board.h
@@ -13,4 +13,9 @@
 #ifndef __ARCH_MVEBU_BOARD_H
 #define __ARCH_MVEBU_BOARD_H
 
+#ifdef CONFIG_MACH_NETXBIG
+void netxbig_init(void);
+#else
+static inline void netxbig_init(void) {};
+#endif
 #endif
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index b67fb7a10d8b..3ccb40c3bf94 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,7 +21,8 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd);
 int mvebu_cpu_reset_deassert(int cpu);
 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr);
 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr);
+int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
 
-void armada_xp_cpu_die(unsigned int cpu);
+void __iomem *mvebu_get_scu_base(void);
 
 #endif
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
index 4a8f9eebebea..60fb53787004 100644
--- a/arch/arm/mach-mvebu/cpu-reset.c
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -67,7 +67,7 @@ static int mvebu_cpu_reset_map(struct device_node *np, int res_idx)
         return 0;
 }
 
-int __init mvebu_cpu_reset_init(void)
+static int __init mvebu_cpu_reset_init(void)
 {
         struct device_node *np;
         int res_idx;
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 2c3c7fc65e28..be51c998c0cd 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -18,21 +18,6 @@
 #include <asm/assembler.h>
 
         __CPUINIT
-#define CPU_RESUME_ADDR_REG 0xf10182d4
-
-.global armada_375_smp_cpu1_enable_code_start
-.global armada_375_smp_cpu1_enable_code_end
-
-armada_375_smp_cpu1_enable_code_start:
-ARM_BE8(setend  be)
-        adr     r0, 1f
-        ldr     r0, [r0]
-        ldr     r1, [r0]
-ARM_BE8(rev     r1, r1)
-        ret     r1
-1:
-        .word   CPU_RESUME_ADDR_REG
-armada_375_smp_cpu1_enable_code_end:
 
 ENTRY(mvebu_cortex_a9_secondary_startup)
 ARM_BE8(setend  be)
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
deleted file mode 100644
index d95e91047168..000000000000
--- a/arch/arm/mach-mvebu/hotplug.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Symmetric Multi Processing (SMP) support for Armada XP
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <asm/proc-fns.h>
-#include "common.h"
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref armada_xp_cpu_die(unsigned int cpu)
-{
-        cpu_do_idle();
-
-        /* We should never return from idle */
-        panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
-}
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 46f105913c84..6b5310828eb2 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -180,6 +180,9 @@ static void __init kirkwood_dt_init(void)
         kirkwood_pm_init();
         kirkwood_dt_eth_fixup();
 
+        if (of_machine_is_compatible("lacie,netxbig"))
+                netxbig_init();
+
         of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
 
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index d0f35b4d4a23..a99434bcee84 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -25,6 +25,7 @@
 #include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
+#include "common.h"
 #include "mvebu-soc-id.h"
 
 #define PCIE_DEV_ID_OFF         0x0
@@ -51,10 +52,10 @@ int mvebu_get_soc_id(u32 *dev, u32 *rev)
                 *rev = soc_rev;
                 return 0;
         } else
-                return -1;
+                return -ENODEV;
 }
 
-static int __init mvebu_soc_id_init(void)
+static int __init get_soc_id_by_pci(void)
 {
         struct device_node *np;
         int ret = 0;
@@ -129,6 +130,22 @@ clk_err:
 
         return ret;
 }
+
+static int __init mvebu_soc_id_init(void)
+{
+
+        /*
+         * First try to get the ID and the revision by the system
+         * register and use PCI registers only if it is not possible
+         */
+        if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev)) {
+                is_id_valid = true;
+                pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
+                return 0;
+        }
+
+        return get_soc_id_by_pci();
+}
 early_initcall(mvebu_soc_id_init);
 
 static int __init mvebu_soc_device(void)
diff --git a/arch/arm/mach-mvebu/netxbig.c b/arch/arm/mach-mvebu/netxbig.c
new file mode 100644
index 000000000000..94b11b6585a4
--- /dev/null
+++ b/arch/arm/mach-mvebu/netxbig.c
@@ -0,0 +1,191 @@
+/*
+ * arch/arm/mach-mvbu/board-netxbig.c
+ *
+ * LaCie 2Big and 5Big Network v2 board setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/leds-kirkwood-netxbig.h>
+#include "common.h"
+
+/*****************************************************************************
+ * GPIO extension LEDs
+ ****************************************************************************/
+
+/*
+ * The LEDs are controlled by a CPLD and can be configured through a GPIO
+ * extension bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+
+static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
+static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
+
+static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
+        .addr           = netxbig_v2_gpio_ext_addr,
+        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
+        .data           = netxbig_v2_gpio_ext_data,
+        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
+        .enable         = 29,
+};
+
+/*
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+
+static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 2,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 4,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 1,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = 7,
+};
+
+static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 7,
+        [NETXBIG_LED_SATA]      = 1,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static struct netxbig_led_timer netxbig_v2_led_timer[] = {
+        [0] = {
+                .delay_on       = 500,
+                .delay_off      = 500,
+                .mode           = NETXBIG_LED_TIMER1,
+        },
+        [1] = {
+                .delay_on       = 500,
+                .delay_off      = 1000,
+                .mode           = NETXBIG_LED_TIMER2,
+        },
+};
+
+#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
+        { .name         = _name,                                \
+          .mode_addr    = maddr,                                \
+          .mode_val     = mval,                                 \
+          .bright_addr  = baddr }
+
+static struct netxbig_led net2big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net2big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net2big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
+};
+
+static struct netxbig_led net5big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata4",  7, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net5big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net5big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
+};
+
+static struct platform_device netxbig_v2_leds = {
+        .name           = "leds-netxbig",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_v2_leds_data,
+        },
+};
+
+void __init netxbig_init(void)
+{
+
+        if (of_machine_is_compatible("lacie,net5big_v2"))
+                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
+        platform_device_register(&netxbig_v2_leds);
+}
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 96c2c59e34b6..47a71a924b96 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -20,33 +20,8 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 #include "common.h"
-#include "mvebu-soc-id.h"
 #include "pmsu.h"
 
-#define CRYPT0_ENG_ID   41
-#define CRYPT0_ENG_ATTR 0x1
-#define SRAM_PHYS_BASE  0xFFFF0000
-
-#define BOOTROM_BASE    0xFFF00000
-#define BOOTROM_SIZE    0x100000
-
-extern unsigned char armada_375_smp_cpu1_enable_code_end;
-extern unsigned char armada_375_smp_cpu1_enable_code_start;
-
-void armada_375_smp_cpu1_enable_wa(void)
-{
-        void __iomem *sram_virt_base;
-
-        mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
-        mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
-                                SRAM_PHYS_BASE, SZ_64K);
-        sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
-
-        memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
-               &armada_375_smp_cpu1_enable_code_end
-               - &armada_375_smp_cpu1_enable_code_start);
-}
-
 extern void mvebu_cortex_a9_secondary_startup(void);
 
 static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
@@ -63,21 +38,10 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
          * address.
          */
         hw_cpu = cpu_logical_map(cpu);
-
-        if (of_machine_is_compatible("marvell,armada375")) {
-                u32 dev, rev;
-
-                if (mvebu_get_soc_id(&dev, &rev) == 0 &&
-                    rev == ARMADA_375_Z1_REV)
-                        armada_375_smp_cpu1_enable_wa();
-
+        if (of_machine_is_compatible("marvell,armada375"))
                 mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
-        }
-        else {
-                mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
-                                             mvebu_cortex_a9_secondary_startup);
-        }
-
+        else
+                mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
         smp_wmb();
         ret = mvebu_cpu_reset_deassert(hw_cpu);
         if (ret) {
@@ -91,9 +55,6 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
 
 static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
         .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = armada_xp_cpu_die,
-#endif
 };
 
 CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 88b976b31719..895dc373c8a1 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -67,6 +67,7 @@ static void __init set_secondary_cpus_clock(void)
                 if (!cpu_clk)
                         return;
                 clk_set_rate(cpu_clk, rate);
+                clk_prepare_enable(cpu_clk);
         }
 }
 
@@ -78,6 +79,17 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         hw_cpu = cpu_logical_map(cpu);
         mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
+
+        /*
+         * This is needed to wake up CPUs in the offline state after
+         * using CPU hotplug.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        /*
+         * This is needed to take secondary CPUs out of reset on the
+         * initial boot.
+         */
         ret = mvebu_cpu_reset_deassert(hw_cpu);
         if (ret) {
                 pr_warn("unable to boot CPU: %d\n", ret);
@@ -87,6 +99,19 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
         return 0;
 }
 
+/*
+ * When a CPU is brought back online, either through CPU hotplug, or
+ * because of the boot of a kexec'ed kernel, the PMSU configuration
+ * for this CPU might be in the deep idle state, preventing this CPU
+ * from receiving interrupts. Here, we therefore take out the current
+ * CPU from this state, which was entered by armada_xp_cpu_die()
+ * below.
+ */
+static void armada_xp_secondary_init(unsigned int cpu)
+{
+        mvebu_v7_pmsu_idle_exit();
+}
+
 static void __init armada_xp_smp_init_cpus(void)
 {
         unsigned int ncores = num_possible_cpus();
@@ -122,12 +147,36 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
                 panic("The address for the BootROM is incorrect");
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void armada_xp_cpu_die(unsigned int cpu)
+{
+        /*
+         * CPU hotplug is implemented by putting offline CPUs into the
+         * deep idle sleep state.
+         */
+        armada_370_xp_pmsu_idle_enter(true);
+}
+
+/*
+ * We need a dummy function, so that platform_can_cpu_hotplug() knows
+ * we support CPU hotplug. However, the function does not need to do
+ * anything, because CPUs going offline can enter the deep idle state
+ * by themselves, without any help from a still alive CPU.
+ */
+static int armada_xp_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+#endif
+
 struct smp_operations armada_xp_smp_ops __initdata = {
         .smp_init_cpus          = armada_xp_smp_init_cpus,
         .smp_prepare_cpus       = armada_xp_smp_prepare_cpus,
         .smp_boot_secondary     = armada_xp_boot_secondary,
+        .smp_secondary_init     = armada_xp_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = armada_xp_cpu_die,
+        .cpu_kill               = armada_xp_cpu_kill,
 #endif
 };
 
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 25aa8237d668..8a70a51533fd 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -18,22 +18,29 @@
 
 #define pr_fmt(fmt) "mvebu-pmsu: " fmt
 
+#include <linux/clk.h>
 #include <linux/cpu_pm.h>
-#include <linux/kernel.h>
+#include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
-#include <linux/smp.h>
+#include <linux/pm_opp.h>
 #include <linux/resource.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 #include "common.h"
+#include "armada-370-xp.h"
 
-static void __iomem *pmsu_mp_base;
 
 #define PMSU_BASE_OFFSET    0x100
 #define PMSU_REG_SIZE       0x1000
@@ -57,20 +64,45 @@ static void __iomem *pmsu_mp_base;
 #define PMSU_STATUS_AND_MASK_IRQ_MASK           BIT(24)
 #define PMSU_STATUS_AND_MASK_FIQ_MASK           BIT(25)
 
+#define PMSU_EVENT_STATUS_AND_MASK(cpu)     ((cpu * 0x100) + 0x120)
+#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE        BIT(1)
+#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK   BIT(17)
+
 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
 
 /* PMSU fabric registers */
 #define L2C_NFABRIC_PM_CTL                  0x4
 #define L2C_NFABRIC_PM_CTL_PWR_DOWN             BIT(20)
 
+/* PMSU delay registers */
+#define PMSU_POWERDOWN_DELAY                0xF04
+#define PMSU_POWERDOWN_DELAY_PMU                BIT(1)
+#define PMSU_POWERDOWN_DELAY_MASK               0xFFFE
+#define PMSU_DFLT_ARMADA38X_DELAY               0x64
+
+/* CA9 MPcore SoC Control registers */
+
+#define MPCORE_RESET_CTL                    0x64
+#define MPCORE_RESET_CTL_L2                     BIT(0)
+#define MPCORE_RESET_CTL_DEBUG                  BIT(16)
+
+#define SRAM_PHYS_BASE  0xFFFF0000
+#define BOOTROM_BASE    0xFFF00000
+#define BOOTROM_SIZE    0x100000
+
+#define ARMADA_370_CRYPT0_ENG_TARGET   0x9
+#define ARMADA_370_CRYPT0_ENG_ATTR     0x1
+
 extern void ll_disable_coherency(void);
 extern void ll_enable_coherency(void);
 
 extern void armada_370_xp_cpu_resume(void);
+extern void armada_38x_cpu_resume(void);
 
-static struct platform_device armada_xp_cpuidle_device = {
-        .name = "cpuidle-armada-370-xp",
-};
+static phys_addr_t pmsu_mp_phys_base;
+static void __iomem *pmsu_mp_base;
+
+static void *mvebu_cpu_resume;
 
 static struct of_device_id of_pmsu_table[] = {
         { .compatible = "marvell,armada-370-pmsu", },
@@ -85,7 +117,49 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
                 PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
 }
 
-static int __init armada_370_xp_pmsu_init(void)
+extern unsigned char mvebu_boot_wa_start;
+extern unsigned char mvebu_boot_wa_end;
+
+/*
+ * This function sets up the boot address workaround needed for SMP
+ * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
+ * BootROM Mbus window, and instead remaps a crypto SRAM into which a
+ * custom piece of code is copied to replace the problematic BootROM.
+ */
+int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
+                             unsigned int crypto_eng_attribute,
+                             phys_addr_t resume_addr_reg)
+{
+        void __iomem *sram_virt_base;
+        u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
+
+        mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
+        mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
+                                    SRAM_PHYS_BASE, SZ_64K);
+
+        sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
+        if (!sram_virt_base) {
+                pr_err("Unable to map SRAM to setup the boot address WA\n");
+                return -ENOMEM;
+        }
+
+        memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
+
+        /*
+         * The last word of the code copied in SRAM must contain the
+         * physical base address of the PMSU register. We
+         * intentionally store this address in the native endianness
+         * of the system.
+         */
+        __raw_writel((unsigned long)resume_addr_reg,
+                     sram_virt_base + code_len - 4);
+
+        iounmap(sram_virt_base);
+
+        return 0;
+}
+
+static int __init mvebu_v7_pmsu_init(void)
 {
         struct device_node *np;
         struct resource res;
@@ -116,6 +190,8 @@ static int __init armada_370_xp_pmsu_init(void)
                 goto out;
         }
 
+        pmsu_mp_phys_base = res.start;
+
         pmsu_mp_base = ioremap(res.start, resource_size(&res));
         if (!pmsu_mp_base) {
                 pr_err("unable to map registers\n");
@@ -129,7 +205,7 @@ static int __init armada_370_xp_pmsu_init(void)
         return ret;
 }
 
-static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
+static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
 {
         u32 reg;
 
@@ -142,14 +218,20 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
         writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
 }
 
+enum pmsu_idle_prepare_flags {
+        PMSU_PREPARE_NORMAL = 0,
+        PMSU_PREPARE_DEEP_IDLE = BIT(0),
+        PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
+};
+
 /* No locking is needed because we only access per-CPU registers */
-void armada_370_xp_pmsu_idle_prepare(bool deepidle)
+static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
 {
         unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
         u32 reg;
 
         if (pmsu_mp_base == NULL)
-                return;
+                return -EINVAL;
 
         /*
          * Adjust the PMSU configuration to wait for WFI signal, enable
@@ -167,22 +249,34 @@ void armada_370_xp_pmsu_idle_prepare(bool deepidle)
 
         reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
         /* ask HW to power down the L2 Cache if needed */
-        if (deepidle)
+        if (flags & PMSU_PREPARE_DEEP_IDLE)
                 reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
 
         /* request power down */
         reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
         writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
 
-        /* Disable snoop disable by HW - SW is taking care of it */
-        reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
-        reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
-        writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+        if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
+                /* Disable snoop disable by HW - SW is taking care of it */
+                reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+                reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
+                writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+        }
+
+        return 0;
 }
 
-static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
 {
-        armada_370_xp_pmsu_idle_prepare(deepidle);
+        unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
+        int ret;
+
+        if (deepidle)
+                flags |= PMSU_PREPARE_DEEP_IDLE;
+
+        ret = mvebu_v7_pmsu_idle_prepare(flags);
+        if (ret)
+                return ret;
 
         v7_exit_coherency_flush(all);
 
@@ -208,25 +302,50 @@ static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
         "isb    "
         : : : "r0");
 
-        pr_warn("Failed to suspend the system\n");
+        pr_debug("Failed to suspend the system\n");
 
         return 0;
 }
 
 static int armada_370_xp_cpu_suspend(unsigned long deepidle)
 {
-        return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
+        return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
+}
+
+static int armada_38x_do_cpu_suspend(unsigned long deepidle)
+{
+        unsigned long flags = 0;
+
+        if (deepidle)
+                flags |= PMSU_PREPARE_DEEP_IDLE;
+
+        mvebu_v7_pmsu_idle_prepare(flags);
+        /*
+         * Already flushed cache, but do it again as the outer cache
+         * functions dirty the cache with spinlocks
+         */
+        v7_exit_coherency_flush(louis);
+
+        scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
+
+        cpu_do_idle();
+
+        return 1;
+}
+
+static int armada_38x_cpu_suspend(unsigned long deepidle)
+{
+        return cpu_suspend(false, armada_38x_do_cpu_suspend);
 }
 
 /* No locking is needed because we only access per-CPU registers */
-static noinline void armada_370_xp_pmsu_idle_restore(void)
+void mvebu_v7_pmsu_idle_exit(void)
 {
         unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
         u32 reg;
 
         if (pmsu_mp_base == NULL)
                 return;
-
         /* cancel ask HW to power down the L2 Cache if possible */
         reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
         reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
@@ -241,53 +360,292 @@ static noinline void armada_370_xp_pmsu_idle_restore(void)
         writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
 }
 
-static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
+static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
                                     unsigned long action, void *hcpu)
 {
         if (action == CPU_PM_ENTER) {
                 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
-                mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
+                mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
         } else if (action == CPU_PM_EXIT) {
-                armada_370_xp_pmsu_idle_restore();
+                mvebu_v7_pmsu_idle_exit();
         }
 
         return NOTIFY_OK;
 }
 
-static struct notifier_block armada_370_xp_cpu_pm_notifier = {
-        .notifier_call = armada_370_xp_cpu_pm_notify,
+static struct notifier_block mvebu_v7_cpu_pm_notifier = {
+        .notifier_call = mvebu_v7_cpu_pm_notify,
 };
 
-int __init armada_370_xp_cpu_pm_init(void)
+static struct platform_device mvebu_v7_cpuidle_device;
+
+static __init int armada_370_cpuidle_init(void)
 {
         struct device_node *np;
+        phys_addr_t redirect_reg;
+
+        np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
+        if (!np)
+                return -ENODEV;
+        of_node_put(np);
 
         /*
-         * Check that all the requirements are available to enable
-         * cpuidle. So far, it is only supported on Armada XP, cpuidle
-         * needs the coherency fabric and the PMSU enabled
+         * On Armada 370, there is "a slow exit process from the deep
+         * idle state due to heavy L1/L2 cache cleanup operations
+         * performed by the BootROM software". To avoid this, we
+         * replace the restart code of the bootrom by a a simple jump
+         * to the boot address. Then the code located at this boot
+         * address will take care of the initialization.
          */
+        redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
+        mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
+                                 ARMADA_370_CRYPT0_ENG_ATTR,
+                                 redirect_reg);
 
-        if (!of_machine_is_compatible("marvell,armadaxp"))
-                return 0;
+        mvebu_cpu_resume = armada_370_xp_cpu_resume;
+        mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+        mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
+
+        return 0;
+}
+
+static __init int armada_38x_cpuidle_init(void)
+{
+        struct device_node *np;
+        void __iomem *mpsoc_base;
+        u32 reg;
+
+        np = of_find_compatible_node(NULL, NULL,
+                                     "marvell,armada-380-coherency-fabric");
+        if (!np)
+                return -ENODEV;
+        of_node_put(np);
+
+        np = of_find_compatible_node(NULL, NULL,
+                                     "marvell,armada-380-mpcore-soc-ctrl");
+        if (!np)
+                return -ENODEV;
+        mpsoc_base = of_iomap(np, 0);
+        BUG_ON(!mpsoc_base);
+        of_node_put(np);
+
+        /* Set up reset mask when powering down the cpus */
+        reg = readl(mpsoc_base + MPCORE_RESET_CTL);
+        reg |= MPCORE_RESET_CTL_L2;
+        reg |= MPCORE_RESET_CTL_DEBUG;
+        writel(reg, mpsoc_base + MPCORE_RESET_CTL);
+        iounmap(mpsoc_base);
+
+        /* Set up delay */
+        reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
+        reg &= ~PMSU_POWERDOWN_DELAY_MASK;
+        reg |= PMSU_DFLT_ARMADA38X_DELAY;
+        reg |= PMSU_POWERDOWN_DELAY_PMU;
+        writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
+
+        mvebu_cpu_resume = armada_38x_cpu_resume;
+        mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
+        mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
+
+        return 0;
+}
+
+static __init int armada_xp_cpuidle_init(void)
+{
+        struct device_node *np;
 
         np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
         if (!np)
-                return 0;
+                return -ENODEV;
         of_node_put(np);
 
+        mvebu_cpu_resume = armada_370_xp_cpu_resume;
+        mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+        mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
+
+        return 0;
+}
+
+static int __init mvebu_v7_cpu_pm_init(void)
+{
+        struct device_node *np;
+        int ret;
+
         np = of_find_matching_node(NULL, of_pmsu_table);
         if (!np)
                 return 0;
         of_node_put(np);
 
-        armada_370_xp_pmsu_enable_l2_powerdown_onidle();
-        armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
-        platform_device_register(&armada_xp_cpuidle_device);
-        cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
+        if (of_machine_is_compatible("marvell,armadaxp"))
+                ret = armada_xp_cpuidle_init();
+        else if (of_machine_is_compatible("marvell,armada370"))
+                ret = armada_370_cpuidle_init();
+        else if (of_machine_is_compatible("marvell,armada380"))
+                ret = armada_38x_cpuidle_init();
+        else
+                return 0;
+
+        if (ret)
+                return ret;
+
+        mvebu_v7_pmsu_enable_l2_powerdown_onidle();
+        platform_device_register(&mvebu_v7_cpuidle_device);
+        cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
+
+        return 0;
+}
+
+arch_initcall(mvebu_v7_cpu_pm_init);
+early_initcall(mvebu_v7_pmsu_init);
+
+static void mvebu_pmsu_dfs_request_local(void *data)
+{
+        u32 reg;
+        u32 cpu = smp_processor_id();
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        /* Prepare to enter idle */
+        reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+        reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
+               PMSU_STATUS_AND_MASK_IRQ_MASK     |
+               PMSU_STATUS_AND_MASK_FIQ_MASK;
+        writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+
+        /* Request the DFS transition */
+        reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
+        reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
+        writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
+
+        /* The fact of entering idle will trigger the DFS transition */
+        wfi();
+
+        /*
+         * We're back from idle, the DFS transition has completed,
+         * clear the idle wait indication.
+         */
+        reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+        reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
+        writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+
+        local_irq_restore(flags);
+}
+
+int mvebu_pmsu_dfs_request(int cpu)
+{
+        unsigned long timeout;
+        int hwcpu = cpu_logical_map(cpu);
+        u32 reg;
+
+        /* Clear any previous DFS DONE event */
+        reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+        reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
+        writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+
+        /* Mask the DFS done interrupt, since we are going to poll */
+        reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+        reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
+        writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+
+        /* Trigger the DFS on the appropriate CPU */
+        smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
+                                 NULL, false);
+
+        /* Poll until the DFS done event is generated */
+        timeout = jiffies + HZ;
+        while (time_before(jiffies, timeout)) {
+                reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+                if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
+                        break;
+                udelay(10);
+        }
+
+        if (time_after(jiffies, timeout))
+                return -ETIME;
+
+        /* Restore the DFS mask to its original state */
+        reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+        reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
+        writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
+
+        return 0;
+}
+
+static int __init armada_xp_pmsu_cpufreq_init(void)
+{
+        struct device_node *np;
+        struct resource res;
+        int ret, cpu;
+
+        if (!of_machine_is_compatible("marvell,armadaxp"))
+                return 0;
+
+        /*
+         * In order to have proper cpufreq handling, we need to ensure
+         * that the Device Tree description of the CPU clock includes
+         * the definition of the PMU DFS registers. If not, we do not
+         * register the clock notifier and the cpufreq driver. This
+         * piece of code is only for compatibility with old Device
+         * Trees.
+         */
+        np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock");
+        if (!np)
+                return 0;
+
+        ret = of_address_to_resource(np, 1, &res);
+        if (ret) {
+                pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n");
+                of_node_put(np);
+                return 0;
+        }
+
+        of_node_put(np);
+
+        /*
+         * For each CPU, this loop registers the operating points
+         * supported (which are the nominal CPU frequency and half of
+         * it), and registers the clock notifier that will take care
+         * of doing the PMSU part of a frequency transition.
+         */
+        for_each_possible_cpu(cpu) {
+                struct device *cpu_dev;
+                struct clk *clk;
+                int ret;
+
+                cpu_dev = get_cpu_device(cpu);
+                if (!cpu_dev) {
+                        pr_err("Cannot get CPU %d\n", cpu);
+                        continue;
+                }
+
+                clk = clk_get(cpu_dev, 0);
+                if (IS_ERR(clk)) {
+                        pr_err("Cannot get clock for CPU %d\n", cpu);
+                        return PTR_ERR(clk);
+                }
+
+                /*
+                 * In case of a failure of dev_pm_opp_add(), we don't
+                 * bother with cleaning up the registered OPP (there's
+                 * no function to do so), and simply cancel the
+                 * registration of the cpufreq device.
+                 */
+                ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
+                if (ret) {
+                        clk_put(clk);
+                        return ret;
+                }
+
+                ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
+                if (ret) {
+                        clk_put(clk);
+                        return ret;
+                }
+        }
 
+        platform_device_register_simple("cpufreq-generic", -1, NULL, 0);
         return 0;
 }
 
-arch_initcall(armada_370_xp_cpu_pm_init);
-early_initcall(armada_370_xp_pmsu_init);
+device_initcall(armada_xp_pmsu_cpufreq_init);
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index 07a737c6b95d..6b58c1fe2b0d 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -12,5 +12,10 @@
 #define __MACH_MVEBU_PMSU_H
 
 int armada_xp_boot_cpu(unsigned int cpu_id, void *phys_addr);
+int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
+                             unsigned int crypto_eng_attribute,
+                             phys_addr_t resume_addr_reg);
+
+void mvebu_v7_pmsu_idle_exit(void);
 
 #endif  /* __MACH_370_XP_PMSU_H */
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index fc3de68d8c54..a945756cfb45 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -23,3 +23,39 @@ ARM_BE8(setend	be )			@ go BE8 if entered LE
         b       cpu_resume
 ENDPROC(armada_370_xp_cpu_resume)
 
+ENTRY(armada_38x_cpu_resume)
+        /* do we need it for Armada 38x*/
+ARM_BE8(setend  be )                    @ go BE8 if entered LE
+        bl      v7_invalidate_l1
+        mrc     p15, 4, r1, c15, c0     @ get SCU base address
+        orr     r1, r1, #0x8            @ SCU CPU Power Status Register
+        mrc     15, 0, r0, cr0, cr0, 5  @ get the CPU ID
+        and     r0, r0, #15
+        add     r1, r1, r0
+        mov     r0, #0x0
+        strb    r0, [r1]                @ switch SCU power state to Normal mode
+        b       cpu_resume
+ENDPROC(armada_38x_cpu_resume)
+
+.global mvebu_boot_wa_start
+.global mvebu_boot_wa_end
+
+/* The following code will be executed from SRAM */
+ENTRY(mvebu_boot_wa_start)
+mvebu_boot_wa_start:
+ARM_BE8(setend  be)
+        adr     r0, 1f
+        ldr     r0, [r0]                @ load the address of the
+                                        @ resume register
+        ldr     r0, [r0]                @ load the value in the
+                                        @ resume register
+ARM_BE8(rev     r0, r0)                 @ the value is stored LE
+        mov     pc, r0                  @ jump to this value
+/*
+ * the last word of this piece of code will be filled by the physical
+ * address of the boot address register just after being copied in SRAM
+ */
+1:
+        .long   .
+mvebu_boot_wa_end:
+ENDPROC(mvebu_boot_wa_end)
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 0c5524ac75b7..a068cb5c2ce8 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -28,8 +28,14 @@
 #include <linux/io.h>
 #include <linux/reboot.h>
 #include "common.h"
+#include "mvebu-soc-id.h"
+#include "pmsu.h"
+
+#define ARMADA_375_CRYPT0_ENG_TARGET 41
+#define ARMADA_375_CRYPT0_ENG_ATTR    1
 
 static void __iomem *system_controller_base;
+static phys_addr_t system_controller_phys_base;
 
 struct mvebu_system_controller {
         u32 rstoutn_mask_offset;
@@ -39,6 +45,9 @@ struct mvebu_system_controller {
         u32 system_soft_reset;
 
         u32 resume_boot_addr;
+
+        u32 dev_id;
+        u32 rev_id;
 };
 static struct mvebu_system_controller *mvebu_sc;
 
@@ -47,6 +56,8 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = {
         .system_soft_reset_offset = 0x64,
         .rstoutn_mask_reset_out_en = 0x1,
         .system_soft_reset = 0x1,
+        .dev_id = 0x38,
+        .rev_id = 0x3c,
 };
 
 static const struct mvebu_system_controller armada_375_system_controller = {
@@ -55,6 +66,8 @@ static const struct mvebu_system_controller armada_375_system_controller = {
         .rstoutn_mask_reset_out_en = 0x1,
         .system_soft_reset = 0x1,
         .resume_boot_addr = 0xd4,
+        .dev_id = 0x38,
+        .rev_id = 0x3c,
 };
 
 static const struct mvebu_system_controller orion_system_controller = {
@@ -101,11 +114,45 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd)
                 ;
 }
 
+int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
+{
+        if (of_machine_is_compatible("marvell,armada380") &&
+                system_controller_base) {
+                *dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
+                *rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
+                        & 0xF;
+                return 0;
+        } else
+                return -ENODEV;
+}
+
 #ifdef CONFIG_SMP
+void mvebu_armada375_smp_wa_init(void)
+{
+        u32 dev, rev;
+        phys_addr_t resume_addr_reg;
+
+        if (mvebu_get_soc_id(&dev, &rev) != 0)
+                return;
+
+        if (rev != ARMADA_375_Z1_REV)
+                return;
+
+        resume_addr_reg = system_controller_phys_base +
+                mvebu_sc->resume_boot_addr;
+        mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
+                                 ARMADA_375_CRYPT0_ENG_ATTR,
+                                 resume_addr_reg);
+}
+
 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
 {
         BUG_ON(system_controller_base == NULL);
         BUG_ON(mvebu_sc->resume_boot_addr == 0);
+
+        if (of_machine_is_compatible("marvell,armada375"))
+                mvebu_armada375_smp_wa_init();
+
         writel(virt_to_phys(boot_addr), system_controller_base +
                mvebu_sc->resume_boot_addr);
 }
@@ -119,7 +166,10 @@ static int __init mvebu_system_controller_init(void)
         np = of_find_matching_node_and_match(NULL, of_system_controller_table,
                                              &match);
         if (np) {
+                struct resource res;
                 system_controller_base = of_iomap(np, 0);
+                of_address_to_resource(np, 0, &res);
+                system_controller_phys_base = res.start;
                 mvebu_sc = (struct mvebu_system_controller *)match->data;
                 of_node_put(np);
         }
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa7800015753..4481b6867902 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -202,6 +202,7 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
+obj-y                                   += omap_hwmod_common_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594e7622..e966e3a3c931 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
 #define DRA7XX_CM_L3INIT_SATA_CLKCTRL                           DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
 #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET                         0x00a0
 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET                         0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET                 0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET                 0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL                        DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
 #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET                         0x00c0
 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET                         0x00c4
 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET                        0x00c8
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b6f8f348296e..324f02bf8a51 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -432,9 +432,9 @@ static int __init omap2_init_devices(void)
          */
         omap_init_audio();
         omap_init_camera();
-        omap_init_mbox();
         /* If dtb is there, the devices will be created dynamically */
         if (!of_have_populated_dt()) {
+                omap_init_mbox();
                 omap_init_mcspi();
                 omap_init_sham();
                 omap_init_aes();
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index a6d2cf1f8d02..e1a56d87599e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
                 d->dev_caps |= HS_CHANNELS_RESERVED;
 
+        if (platform_get_irq_byname(pdev, "0") < 0)
+                d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
+
         /* Check the capabilities register for descriptor loading feature */
         if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
                 dma_common_ch_end = CCDN;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 2f15979c2e9c..65b1647092bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,7 +16,6 @@
 #include <linux/i2c-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
-#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 };
 
 /* mailbox */
-static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
-        { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
-        { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
-};
-
-static struct omap_mbox_pdata omap2420_mailbox_attrs = {
-        .num_users      = 4,
-        .num_fifos      = 6,
-        .info_cnt       = ARRAY_SIZE(omap2420_mailbox_info),
-        .info           = omap2420_mailbox_info,
-};
-
 static struct omap_hwmod omap2420_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap2xxx_mailbox_hwmod_class,
@@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
-        .dev_attr       = &omap2420_mailbox_attrs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 6d1b60902179..c2555cb95e71 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,7 +17,6 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
-#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 
 /* mailbox */
-static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
-        { .name = "dsp", .tx_id = 0, .rx_id = 1 },
-};
-
-static struct omap_mbox_pdata omap2430_mailbox_attrs = {
-        .num_users      = 4,
-        .num_fifos      = 6,
-        .info_cnt       = ARRAY_SIZE(omap2430_mailbox_info),
-        .info           = omap2430_mailbox_info,
-};
-
 static struct omap_hwmod omap2430_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap2xxx_mailbox_hwmod_class,
@@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
-        .dev_attr       = &omap2430_mailbox_attrs,
 };
 
 /* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 0413daba2dba..c1e98d589100 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x48094000,
-                .pa_end         = 0x48094000 + SZ_512 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
         {
                 .name           = "mpu",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 5da7a42a6d90..c6c6384de867 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -37,46 +37,6 @@ struct omap_hwmod_class omap2_uart_class = {
 };
 
 /*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                           SYSS_HAS_RESET_STATUS),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2_dss_hwmod_class = {
-        .name   = "dss",
-        .sysc   = &omap2_dss_sysc,
-        .reset  = omap_dss_reset,
-};
-
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2_rfbi_hwmod_class = {
-        .name   = "rfbi",
-        .sysc   = &omap2_rfbi_sysc,
-};
-
-/*
  * 'venc' class
  * video encoder
  */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index e2db378b849e..8f5989d48a80 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x480C8000,
-                .pa_end         = 0x480C8000 + (SZ_4K - 1),
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4 ls -> mailbox */
 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_mailbox_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_mailbox_addrs,
         .user           = OCP_USER_MPU,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c2cc8083fdd..fea01aa3ef42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -19,6 +19,8 @@
 #include "omap_hwmod.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
 #include "prcm43xx.h"
+#include "omap_hwmod_common_data.h"
+
 
 /* IP blocks */
 static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
         },
 };
 
+/* dss */
+
+static struct omap_hwmod am43xx_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2_dss_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "disp_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* dispc */
+
+struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
+        .manager_count          = 1,
+        .has_framedonetv_irq    = 0
+};
+
+static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &am43xx_dispc_sysc,
+};
+
+static struct omap_hwmod am43xx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &am43xx_dispc_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "disp_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
+                },
+        },
+        .dev_attr       = &am43xx_dss_dispc_dev_attr,
+};
+
+/* rfbi */
+
+static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2_rfbi_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "disp_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
+                },
+        },
+};
+
 /* Interfaces */
 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
         .master         = &am33xx_l3_main_hwmod,
@@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
+        .master         = &am43xx_dss_core_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_dss_core_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_dss_dispc_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_dss_rfbi_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_wkup__synctimer,
         &am43xx_l4_ls__timer8,
@@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am43xx_l4_ls__ocp2scp1,
         &am43xx_l3_s__usbotgss0,
         &am43xx_l3_s__usbotgss1,
+        &am43xx_dss__l3_main,
+        &am43xx_l4_ls__dss,
+        &am43xx_l4_ls__dss_dispc,
+        &am43xx_l4_ls__dss_rfbi,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index b4acc0a7576f..44e5634bba34 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4138,21 +4138,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x4a0f4000,
-                .pa_end         = 0x4a0f41ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> mailbox */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_mailbox_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 284324f2b98a..2757abf87fbc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 };
 
 /*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+        .name           = "gmac",
+        .sysc           = &dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod dra7xx_gmac_hwmod = {
+        .name           = "gmac",
+        .class          = &dra7xx_gmac_hwmod_class,
+        .clkdm_name     = "gmac_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "dpll_gmac_ck",
+        .mpu_rt_idx     = 1,
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
+                        .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mdio' class
+ */
+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
+        .name           = "davinci_mdio",
+};
+
+static struct omap_hwmod dra7xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &dra7xx_mdio_hwmod_class,
+        .clkdm_name     = "gmac_clkdm",
+        .main_clk       = "dpll_gmac_ck",
+};
+
+/*
  * 'dcan' class
  *
  */
@@ -343,19 +393,10 @@ static struct omap_dma_dev_attr dma_dev_attr = {
 };
 
 /* dma_system */
-static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
-        { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
-        { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
-        { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod dra7xx_dma_system_hwmod = {
         .name           = "dma_system",
         .class          = &dra7xx_dma_hwmod_class,
         .clkdm_name     = "dma_clkdm",
-        .mpu_irqs       = dra7xx_dma_system_irqs,
         .main_clk       = "l3_iclk_div",
         .prcm = {
                 .omap4 = {
@@ -939,6 +980,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &dra7xx_mailbox_sysc,
+};
+
+/* mailbox1 */
+static struct omap_hwmod dra7xx_mailbox1_hwmod = {
+        .name           = "mailbox1",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox2 */
+static struct omap_hwmod dra7xx_mailbox2_hwmod = {
+        .name           = "mailbox2",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox3 */
+static struct omap_hwmod dra7xx_mailbox3_hwmod = {
+        .name           = "mailbox3",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox4 */
+static struct omap_hwmod dra7xx_mailbox4_hwmod = {
+        .name           = "mailbox4",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox5 */
+static struct omap_hwmod dra7xx_mailbox5_hwmod = {
+        .name           = "mailbox5",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox6 */
+static struct omap_hwmod dra7xx_mailbox6_hwmod = {
+        .name           = "mailbox6",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox7 */
+static struct omap_hwmod dra7xx_mailbox7_hwmod = {
+        .name           = "mailbox7",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox8 */
+static struct omap_hwmod dra7xx_mailbox8_hwmod = {
+        .name           = "mailbox8",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox9 */
+static struct omap_hwmod dra7xx_mailbox9_hwmod = {
+        .name           = "mailbox9",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox10 */
+static struct omap_hwmod dra7xx_mailbox10_hwmod = {
+        .name           = "mailbox10",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox11 */
+static struct omap_hwmod dra7xx_mailbox11_hwmod = {
+        .name           = "mailbox11",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox12 */
+static struct omap_hwmod dra7xx_mailbox12_hwmod = {
+        .name           = "mailbox12",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* mailbox13 */
+static struct omap_hwmod dra7xx_mailbox13_hwmod = {
+        .name           = "mailbox13",
+        .class          = &dra7xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
  * 'mcspi' class
  *
  */
@@ -1215,6 +1444,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
         },
 };
 
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+        .name           = "ocp2scp3",
+        .class          = &dra7xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+        .name   = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+        .name           = "pcie1",
+        .class          = &dra7xx_pcie_hwmod_class,
+        .clkdm_name     = "pcie_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+        .name           = "pcie2",
+        .class          = &dra7xx_pcie_hwmod_class,
+        .clkdm_name     = "pcie_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+        .name   = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+        .name           = "pcie1-phy",
+        .class          = &dra7xx_pcie_phy_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+        .name           = "pcie2-phy",
+        .class          = &dra7xx_pcie_phy_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
 /*
  * 'qspi' class
  *
@@ -1249,6 +1569,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
 };
 
 /*
+ * 'rtcss' class
+ *
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
+        .name   = "rtcss",
+        .sysc   = &dra7xx_rtcss_sysc,
+};
+
+/* rtcss */
+static struct omap_hwmod dra7xx_rtcss_hwmod = {
+        .name           = "rtcss",
+        .class          = &dra7xx_rtcss_hwmod_class,
+        .clkdm_name     = "rtc_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
  * 'sata' class
  *
  */
@@ -2007,6 +2359,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_gmac_hwmod,
+        .clk            = "dpll_gmac_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
+        .master         = &dra7xx_gmac_hwmod,
+        .slave          = &dra7xx_mdio_hwmod,
+        .user           = OCP_USER_MPU,
+};
+
 /* l4_wkup -> dcan1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
         .master         = &dra7xx_l4_wkup_hwmod,
@@ -2254,6 +2619,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> mailbox1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_mailbox1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox4_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox5_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox6_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox7_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox8_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox9_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox10_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox11_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox12 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox12_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> mailbox13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_mailbox13_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per1 -> mcspi1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
         .master         = &dra7xx_l4_per1_hwmod,
@@ -2334,6 +2803,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_ocp2scp3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_pcie1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_pcie2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie1_phy_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie2_phy_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
         {
                 .pa_start       = 0x4b300000,
@@ -2352,6 +2877,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per3 -> rtcss */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_rtcss_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
         {
                 .name           = "sysc",
@@ -2650,6 +3183,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_wkup__ctrl_module_wkup,
         &dra7xx_l4_wkup__dcan1,
         &dra7xx_l4_per2__dcan2,
+        &dra7xx_l4_per2__cpgmac0,
+        &dra7xx_gmac__mdio,
         &dra7xx_l4_cfg__dma_system,
         &dra7xx_l3_main_1__dss,
         &dra7xx_l3_main_1__dispc,
@@ -2670,6 +3205,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per1__i2c3,
         &dra7xx_l4_per1__i2c4,
         &dra7xx_l4_per1__i2c5,
+        &dra7xx_l4_cfg__mailbox1,
+        &dra7xx_l4_per3__mailbox2,
+        &dra7xx_l4_per3__mailbox3,
+        &dra7xx_l4_per3__mailbox4,
+        &dra7xx_l4_per3__mailbox5,
+        &dra7xx_l4_per3__mailbox6,
+        &dra7xx_l4_per3__mailbox7,
+        &dra7xx_l4_per3__mailbox8,
+        &dra7xx_l4_per3__mailbox9,
+        &dra7xx_l4_per3__mailbox10,
+        &dra7xx_l4_per3__mailbox11,
+        &dra7xx_l4_per3__mailbox12,
+        &dra7xx_l4_per3__mailbox13,
         &dra7xx_l4_per1__mcspi1,
         &dra7xx_l4_per1__mcspi2,
         &dra7xx_l4_per1__mcspi3,
@@ -2680,7 +3228,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per1__mmc4,
         &dra7xx_l4_cfg__mpu,
         &dra7xx_l4_cfg__ocp2scp1,
+        &dra7xx_l4_cfg__ocp2scp3,
+        &dra7xx_l3_main_1__pcie1,
+        &dra7xx_l4_cfg__pcie1,
+        &dra7xx_l3_main_1__pcie2,
+        &dra7xx_l4_cfg__pcie2,
+        &dra7xx_l4_cfg__pcie1_phy,
+        &dra7xx_l4_cfg__pcie2_phy,
         &dra7xx_l3_main_1__qspi,
+        &dra7xx_l4_per3__rtcss,
         &dra7xx_l4_cfg__sata,
         &dra7xx_l4_cfg__smartreflex_core,
         &dra7xx_l4_cfg__smartreflex_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 2c38c6b0ee03..11ed5a17dd77 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
 extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
 extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
 extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
-extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
 extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
 extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
new file mode 100644
index 000000000000..f21664da25a2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
@@ -0,0 +1,55 @@
+/*
+ * omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &omap2_dss_sysc,
+        .reset  = omap_dss_reset,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_rfbi_hwmod_class = {
+        .name   = "rfbi",
+        .sysc   = &omap2_rfbi_sysc,
+};
+
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7785be984edd..ad7b3e9977f8 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -142,5 +142,6 @@
 #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET     0x05B8
 #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET        0x0268
 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET     0x05C0
+#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET                0x0a20
 
 #endif
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a8404edc7..4bb50fbf29be 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET          0x007c
 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET                      0x0088
 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET                    0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET                   0x00b0
+#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET         0x00b4
+#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET                   0x00b8
+#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET         0x00bc
 #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET                      0x00d4
 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET                0x00e4
 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET                0x00ec
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 4377a1436a98..b29d8ead4cf2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,2 +1,4 @@
+CFLAGS_platsmp.o := -march=armv7-a
+
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 910835d4ccf4..189684f55927 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -21,6 +21,7 @@
 #include <linux/of_address.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cp15.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 #include <asm/mach/map.h>
@@ -178,8 +179,27 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
                 pmu_set_power_domain(0 + i, false);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static int rockchip_cpu_kill(unsigned int cpu)
+{
+        pmu_set_power_domain(0 + cpu, false);
+        return 1;
+}
+
+static void rockchip_cpu_die(unsigned int cpu)
+{
+        v7_exit_coherency_flush(louis);
+        while(1)
+                cpu_do_idle();
+}
+#endif
+
 static struct smp_operations rockchip_smp_ops __initdata = {
         .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
         .smp_boot_secondary     = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = rockchip_cpu_kill,
+        .cpu_die                = rockchip_cpu_die,
+#endif
 };
 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c0763b837745..44fa95df9262 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -49,9 +49,7 @@
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
 #include <plat/cpu-freq.h>
-#include <plat/pll.h>
 #include <plat/pwm-core.h>
 #include <plat/watchdog-reset.h>
 
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index bd064c05c473..28b13951de87 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -29,7 +29,6 @@
 
 #include <plat/cpu.h>
 #include <plat/cpu-freq-core.h>
-#include <plat/clock.h>
 
 #include <mach/s3c2412.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index fbf5487ae5d1..c9a99bbad545 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -60,7 +60,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/samsung-time.h>
 
@@ -73,6 +72,10 @@
 
 #define H1940_LATCH_BIT(x)      (1 << ((x) + 16 - S3C_GPIO_END))
 
+#define S3C24XX_PLL_MDIV_SHIFT         (12)
+#define S3C24XX_PLL_PDIV_SHIFT         (4)
+#define S3C24XX_PLL_SDIV_SHIFT         (0)
+
 static struct map_desc h1940_iodesc[] __initdata = {
         [0] = {
                 .virtual        = (unsigned long)H1940_LATCH,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index e81ea82c55f9..e647b47244a9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -48,7 +48,6 @@
 #include <linux/mtd/partitions.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index fb3b80e44595..10726bf84920 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -43,7 +43,6 @@
 #include <mach/gpio-samsung.h>
 #include <mach/fb.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index fa6f30d23601..24189e8e8560 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -44,7 +44,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index ef5d5ea33182..0ed77614dcfe 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,7 +38,6 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9104c2be36c9..9d4f64750698 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 7eab88829883..5ffe828cd659 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -41,8 +41,6 @@
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/watchdog-reset.h>
 
@@ -83,10 +81,6 @@ void __init s3c2410_map_io(void)
         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
 
-void __init_or_cpufreq s3c2410_setup_clocks(void)
-{
-}
-
 struct bus_type s3c2410_subsys = {
         .name = "s3c2410-core",
         .dev_name = "s3c2410-core",
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index d49f52fbc842..569f3f5a6c71 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -37,12 +37,10 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
 #include <plat/nand-core.h>
-#include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-spi.h>
 
@@ -171,10 +169,6 @@ void __init s3c2412_map_io(void)
         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 }
 
-void __init_or_cpufreq s3c2412_setup_clocks(void)
-{
-}
-
 /* need to register the subsystem before we actually register the device, and
  * we also need to ensure that it has been initialised before any of the
  * drivers even try to use it (even if not on an s3c2412 based system)
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index fb9da2b603a2..7b043349f1c8 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -43,7 +43,6 @@
 
 #include <mach/regs-clock.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 4a64bcc9eb51..d1c3e65785a1 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -38,11 +38,9 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/pll.h>
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
 
@@ -78,10 +76,6 @@ void __init s3c244x_map_io(void)
         s3c2410_device_dclk.name = "s3c2440-dclk";
 }
 
-void __init_or_cpufreq s3c244x_setup_clocks(void)
-{
-}
-
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
 
 struct bus_type s3c2440_subsys = {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 55eb6a69655b..60576dfbea8d 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -45,7 +45,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 4b0199fff9f5..fe116334afda 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -58,7 +58,6 @@
 #include <linux/platform_data/spi-s3c64xx.h>
 
 #include <plat/keypad.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 72cee08c8bf5..19e8feb908fd 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -39,7 +39,6 @@
 #include <plat/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 67f06a9ae656..4bae7dc49eea 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -40,7 +40,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 78dd6f73c072..b3d13537a7f0 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -28,7 +28,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index c85d1cbe769f..910749768340 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index c6a8b2ab0240..1dc86d76b530 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -63,7 +63,6 @@
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 8c42807bf579..1ce48c54cd9c 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -39,7 +39,6 @@
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 5be3f09bac92..b2a7930548d9 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -40,7 +40,6 @@
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
 #include <plat/sdhci.h>
 #include <plat/ata-core.h>
 #include <plat/adc-core.h>
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index f60f2862856d..330bfc8fcd52 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -7,193 +7,28 @@
 
 # Configuration options for the S5PV210/S5PC110
 
+config ARCH_S5PV210
+        bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7
+        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_VIC
+        select CLKSRC_SAMSUNG_PWM
+        select COMMON_CLK_SAMSUNG
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select HAVE_S3C_RTC if RTC_CLASS
+        select PINCTRL
+        select PINCTRL_EXYNOS
+        help
+          Samsung S5PV210/S5PC110 series based systems
+
 if ARCH_S5PV210
 
 config CPU_S5PV210
-        bool
+        def_bool y
         select ARM_AMBA
         select PL330_DMA if DMADEVICES
-        select S5P_EXT_INT
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
         help
           Enable S5PV210 CPU support
 
-config S5PV210_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config S5PV210_SETUP_I2C2
-        bool
-        help
-          Common setup code for i2c bus 2.
-
-config S5PV210_SETUP_IDE
-        bool
-        help
-          Common setup code for S5PV210 IDE GPIO configurations
-
-config S5PV210_SETUP_FB_24BPP
-        bool
-        help
-          Common setup code for S5PV210 with an 24bpp RGB display helper.
-
-config S5PV210_SETUP_KEYPAD
-        bool
-        help
-          Common setup code for keypad.
-
-config S5PV210_SETUP_SDHCI
-        bool
-        select S5PV210_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S5PV210 based SDHCI systems
-
-config S5PV210_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-config S5PV210_SETUP_FIMC
-        bool
-        help
-          Common setup code for the camera interfaces.
-
-config S5PV210_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations.
-
-config S5PV210_SETUP_USB_PHY
-        bool
-        help
-          Common setup code for USB PHY controller
-
-menu "S5PC110 Machines"
-
-config MACH_AQUILA
-        bool "Aquila"
-        select CPU_S5PV210
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S5PV210_SETUP_FB_24BPP
-        select S5PV210_SETUP_SDHCI
-        select S5PV210_SETUP_USB_PHY
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_ONENAND
-        help
-          Machine support for the Samsung Aquila target based on S5PC110 SoC
-
-config MACH_GONI
-        bool "GONI"
-        select CPU_S5PV210
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C2
-        select S3C_DEV_USB_HSOTG
-        select S5PV210_SETUP_FB_24BPP
-        select S5PV210_SETUP_FIMC
-        select S5PV210_SETUP_I2C1
-        select S5PV210_SETUP_I2C2
-        select S5PV210_SETUP_KEYPAD
-        select S5PV210_SETUP_SDHCI
-        select S5PV210_SETUP_USB_PHY
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_MFC
-        select S5P_DEV_ONENAND
-        select S5P_DEV_TV
-        select S5P_GPIO_INT
-        select SAMSUNG_DEV_KEYPAD
-        help
-          Machine support for Samsung GONI board
-          S5PC110(MCP) is one of package option of S5PV210
-
-config MACH_SMDKC110
-        bool "SMDKC110"
-        select CPU_S5PV210
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C2
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S5PV210_SETUP_I2C1
-        select S5PV210_SETUP_I2C2
-        select S5PV210_SETUP_IDE
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_MFC
-        select SAMSUNG_DEV_IDE
-        help
-          Machine support for Samsung SMDKC110
-          S5PC110(MCP) is one of package option of S5PV210
-
-endmenu
-
-menu "S5PV210 Machines"
-
-config MACH_SMDKV210
-        bool "SMDKV210"
-        select CPU_S5PV210
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C2
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5PV210_SETUP_FB_24BPP
-        select S5PV210_SETUP_I2C1
-        select S5PV210_SETUP_I2C2
-        select S5PV210_SETUP_IDE
-        select S5PV210_SETUP_KEYPAD
-        select S5PV210_SETUP_SDHCI
-        select S5PV210_SETUP_USB_PHY
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_IDE
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_TS
-        help
-          Machine support for Samsung SMDKV210
-
-config MACH_TORBRECK
-        bool "Torbreck"
-        select ARCH_SPARSEMEM_ENABLE
-        select CPU_S5PV210
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C2
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S5PV210_SETUP_I2C1
-        select S5PV210_SETUP_I2C2
-        select S5PV210_SETUP_SDHCI
-        select SAMSUNG_DEV_IDE
-        help
-          Machine support for aESOP Torbreck
-
-endmenu
-
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 1c4e41998a10..7dc2d0e25a83 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
 
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
+
 obj-y                           :=
 obj-m                           :=
 obj-n                           :=
@@ -12,31 +14,8 @@ obj-				:=
 
 # Core
 
-obj-y                           += common.o clock.o
-
-obj-$(CONFIG_PM)                += pm.o
-
-obj-y                           += dma.o
+obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
 
 # machine support
 
-obj-$(CONFIG_MACH_AQUILA)       += mach-aquila.o
-obj-$(CONFIG_MACH_GONI)         += mach-goni.o
-obj-$(CONFIG_MACH_SMDKC110)     += mach-smdkc110.o
-obj-$(CONFIG_MACH_SMDKV210)     += mach-smdkv210.o
-obj-$(CONFIG_MACH_TORBRECK)     += mach-torbreck.o
-
-# device support
-
-obj-y                           += dev-audio.o
-
-obj-y                                   += setup-i2c0.o
-obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
-obj-$(CONFIG_S5PV210_SETUP_FIMC)        += setup-fimc.o
-obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
-obj-$(CONFIG_S5PV210_SETUP_IDE)         += setup-ide.o
-obj-$(CONFIG_S5PV210_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_S5PV210_SETUP_SPI)         += setup-spi.o
-obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
+obj-y                           += s5pv210.o
diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pv210/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   += 0x20008000
-params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
deleted file mode 100644
index ca463724a3df..000000000000
--- a/arch/arm/mach-s5pv210/clock.c
+++ /dev/null
@@ -1,1365 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/clock.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-
-#include "common.h"
-
-static unsigned long xtal;
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_armclk_list[] = {
-        [0] = &clk_mout_apll.clk,
-        [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_armclk = {
-        .sources        = clkset_armclk_list,
-        .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
-};
-
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-        },
-        .sources        = &clkset_armclk,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_hclk_msys = {
-        .clk    = {
-                .name           = "hclk_msys",
-                .parent         = &clk_armclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_msys = {
-        .clk    = {
-                .name           = "pclk_msys",
-                .parent         = &clk_hclk_msys.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_sclk_a2m = {
-        .clk    = {
-                .name           = "sclk_a2m",
-                .parent         = &clk_mout_apll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
-};
-
-static struct clk *clkset_hclk_sys_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_a2m.clk,
-};
-
-static struct clksrc_sources clkset_hclk_sys = {
-        .sources        = clkset_hclk_sys_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
-};
-
-static struct clksrc_clk clk_hclk_dsys = {
-        .clk    = {
-                .name   = "hclk_dsys",
-        },
-        .sources        = &clkset_hclk_sys,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_dsys = {
-        .clk    = {
-                .name   = "pclk_dsys",
-                .parent = &clk_hclk_dsys.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_hclk_psys = {
-        .clk    = {
-                .name   = "hclk_psys",
-        },
-        .sources        = &clkset_hclk_sys,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_psys = {
-        .clk    = {
-                .name   = "pclk_psys",
-                .parent = &clk_hclk_psys.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
-};
-
-static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
-}
-
-static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
-}
-
-static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
-}
-
-static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
-}
-
-static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
-}
-
-static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
-}
-
-static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-static struct clk clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-};
-
-static struct clk clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk clk_pcmcdclk0 = {
-        .name           = "pcmcdclk",
-};
-
-static struct clk clk_pcmcdclk1 = {
-        .name           = "pcmcdclk",
-};
-
-static struct clk clk_pcmcdclk2 = {
-        .name           = "pcmcdclk",
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
-        .sources        = clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 7),
-        },
-        .sources        = &clkset_vpllsrc,
-        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
-        [0] = &clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
-        .sources        = clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources        = &clkset_sclk_vpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
-};
-
-static struct clk *clkset_moutdmc0src_list[] = {
-        [0] = &clk_sclk_a2m.clk,
-        [1] = &clk_mout_mpll.clk,
-        [2] = NULL,
-        [3] = NULL,
-};
-
-static struct clksrc_sources clkset_moutdmc0src = {
-        .sources        = clkset_moutdmc0src_list,
-        .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
-};
-
-static struct clksrc_clk clk_mout_dmc0 = {
-        .clk    = {
-                .name           = "mout_dmc0",
-        },
-        .sources        = &clkset_moutdmc0src,
-        .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
-};
-
-static struct clksrc_clk clk_sclk_dmc0 = {
-        .clk    = {
-                .name           = "sclk_dmc0",
-                .parent         = &clk_mout_dmc0.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
-};
-
-static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk_ops clk_hclk_imem_ops = {
-        .get_rate       = s5pv210_clk_imem_get_rate,
-};
-
-static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
-}
-
-static struct clk_ops clk_fout_apll_ops = {
-        .get_rate       = s5pv210_clk_fout_apll_get_rate,
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "rot",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1<<29),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5pv210-fimc.0",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5pv210-fimc.1",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "fimc",
-                .devname        = "s5pv210-fimc.2",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "jpeg",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 28),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "hdmi",
-                .devname        = "s5pv210-hdmi",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "s5pv210-hdmi",
-                .enable         = s5pv210_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "otg",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1<<17),
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_hclk_dsys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1<<0),
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1<<25),
-        }, {
-                .name           = "systimer",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<22),
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<15),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pv210-spi.0",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<12),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pv210-spi.1",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<13),
-        }, {
-                .name           = "spi",
-                .devname        = "s5pv210-spi.2",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<14),
-        }, {
-                .name           = "timers",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<23),
-        }, {
-                .name           = "adc",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "keypad",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<21),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.0",
-                .parent         = &clk_p,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<4),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .parent         = &clk_p,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .parent         = &clk_p,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "spdif",
-                .parent         = &clk_p,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "hclk_imem",
-                .parent         = &clk_hclk_msys.clk,
-                .ctrlbit        = (1 << 5),
-                .enable         = s5pv210_clk_ip0_ctrl,
-                .ops            = &clk_hclk_imem_ops,
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .parent         = &clk_pclk_psys.clk,
-                .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "sromc",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip1_ctrl,
-                .ctrlbit        = (1 << 26),
-        },
-};
-
-static struct clk clk_hsmmc0 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.0",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip2_ctrl,
-        .ctrlbit        = (1<<16),
-};
-
-static struct clk clk_hsmmc1 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip2_ctrl,
-        .ctrlbit        = (1<<17),
-};
-
-static struct clk clk_hsmmc2 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.2",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip2_ctrl,
-        .ctrlbit        = (1<<18),
-};
-
-static struct clk clk_hsmmc3 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.3",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip2_ctrl,
-        .ctrlbit        = (1<<19),
-};
-
-static struct clk clk_pdma0 = {
-        .name           = "pdma0",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip0_ctrl,
-        .ctrlbit        = (1 << 3),
-};
-
-static struct clk clk_pdma1 = {
-        .name           = "pdma1",
-        .parent         = &clk_hclk_psys.clk,
-        .enable         = s5pv210_clk_ip0_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk *clkset_uart_list[] = {
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_group1_list[] = {
-        [0] = &clk_sclk_a2m.clk,
-        [1] = &clk_mout_mpll.clk,
-        [2] = &clk_mout_epll.clk,
-        [3] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_group1 = {
-        .sources        = clkset_group1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
-};
-
-static struct clk *clkset_sclk_onenand_list[] = {
-        [0] = &clk_hclk_psys.clk,
-        [1] = &clk_hclk_dsys.clk,
-};
-
-static struct clksrc_sources clkset_sclk_onenand = {
-        .sources        = clkset_sclk_onenand_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
-        [0] = &clk_sclk_vpll.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
-        .sources        = clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 2),
-        },
-        .sources        = &clkset_sclk_dac,
-        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &clk_sclk_vpll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
-        [0] = &clk_sclk_pixel.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
-        .sources        = clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources        = &clkset_sclk_hdmi,
-        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
-        [0] = &clk_sclk_dac.clk,
-        [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
-        .sources        = clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
-        .clk            = {
-                .name           = "sclk_mixer",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 1),
-        },
-        .sources = &clkset_sclk_mixer,
-        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
-        &clk_sclk_dac,
-        &clk_sclk_pixel,
-        &clk_sclk_hdmi,
-        &clk_sclk_mixer,
-};
-
-static struct clk *clkset_sclk_audio0_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_pcmcdclk0,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_sclk_audio0 = {
-        .sources        = clkset_sclk_audio0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
-};
-
-static struct clksrc_clk clk_sclk_audio0 = {
-        .clk            = {
-                .name           = "sclk_audio",
-                .devname        = "soc-audio.0",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .sources = &clkset_sclk_audio0,
-        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_audio1_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_pcmcdclk1,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_sclk_audio1 = {
-        .sources        = clkset_sclk_audio1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
-};
-
-static struct clksrc_clk clk_sclk_audio1 = {
-        .clk            = {
-                .name           = "sclk_audio",
-                .devname        = "soc-audio.1",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 25),
-        },
-        .sources = &clkset_sclk_audio1,
-        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
-};
-
-static struct clk *clkset_sclk_audio2_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_pcmcdclk0,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_sclk_audio2 = {
-        .sources        = clkset_sclk_audio2_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
-};
-
-static struct clksrc_clk clk_sclk_audio2 = {
-        .clk            = {
-                .name           = "sclk_audio",
-                .devname        = "soc-audio.2",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 26),
-        },
-        .sources = &clkset_sclk_audio2,
-        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
-};
-
-static struct clk *clkset_sclk_spdif_list[] = {
-        [0] = &clk_sclk_audio0.clk,
-        [1] = &clk_sclk_audio1.clk,
-        [2] = &clk_sclk_audio2.clk,
-};
-
-static struct clksrc_sources clkset_sclk_spdif = {
-        .sources        = clkset_sclk_spdif_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
-};
-
-static struct clksrc_clk clk_sclk_spdif = {
-        .clk            = {
-                .name           = "sclk_spdif",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 27),
-                .ops            = &s5p_sclk_spdif_ops,
-        },
-        .sources = &clkset_sclk_spdif,
-        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
-};
-
-static struct clk *clkset_group2_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_group2 = {
-        .sources        = clkset_group2_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_dmc",
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_onenand",
-                },
-                .sources = &clkset_sclk_onenand,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5pv210-fimc.0",
-                        .enable         = s5pv210_clk_mask1_ctrl,
-                        .ctrlbit        = (1 << 2),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5pv210-fimc.1",
-                        .enable         = s5pv210_clk_mask1_ctrl,
-                        .ctrlbit        = (1 << 3),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "s5pv210-fimc.2",
-                        .enable         = s5pv210_clk_mask1_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 3),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 5),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                        .enable         = s5pv210_clk_ip0_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_g2d",
-                        .enable         = s5pv210_clk_ip0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_g3d",
-                        .enable         = s5pv210_clk_ip0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 6),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_pwi",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 29),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_pwm",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 19),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
-        },
-};
-
-static struct clksrc_clk clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "s5pv210-uart.0",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart1 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "s5pv210-uart.1",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 13),
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart2 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "s5pv210-uart.2",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 14),
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart3 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "s5pv210-uart.3",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 15),
-        },
-        .sources = &clkset_uart,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 9),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 10),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc3 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 11),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname        = "s5pv210-spi.0",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
-        };
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname        = "s5pv210-spi.1",
-                .enable         = s5pv210_clk_mask0_ctrl,
-                .ctrlbit        = (1 << 17),
-        },
-        .sources = &clkset_group2,
-        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
-        };
-
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uart0,
-        &clk_sclk_uart1,
-        &clk_sclk_uart2,
-        &clk_sclk_uart3,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_mmc3,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_hsmmc0,
-        &clk_hsmmc1,
-        &clk_hsmmc2,
-        &clk_hsmmc3,
-        &clk_pdma0,
-        &clk_pdma1,
-};
-
-/* Clock initialisation code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_armclk,
-        &clk_hclk_msys,
-        &clk_sclk_a2m,
-        &clk_hclk_dsys,
-        &clk_hclk_psys,
-        &clk_pclk_msys,
-        &clk_pclk_dsys,
-        &clk_pclk_psys,
-        &clk_vpllsrc,
-        &clk_sclk_vpll,
-        &clk_mout_dmc0,
-        &clk_sclk_dmc0,
-        &clk_sclk_audio0,
-        &clk_sclk_audio1,
-        &clk_sclk_audio2,
-        &clk_sclk_spdif,
-};
-
-static u32 epll_div[][6] = {
-        {  48000000, 0, 48, 3, 3, 0 },
-        {  96000000, 0, 48, 3, 2, 0 },
-        { 144000000, 1, 72, 3, 2, 0 },
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 288000000, 1, 72, 3, 1, 0 },
-        {  32750000, 1, 65, 3, 4, 35127 },
-        {  32768000, 1, 65, 3, 4, 35127 },
-        {  45158400, 0, 45, 3, 3, 10355 },
-        {  45000000, 0, 45, 3, 3, 10355 },
-        {  45158000, 0, 45, 3, 3, 10355 },
-        {  49125000, 0, 49, 3, 3, 9961 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  67737600, 1, 67, 3, 3, 48366 },
-        {  67738000, 1, 67, 3, 3, 48366 },
-        {  73800000, 1, 73, 3, 3, 47710 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  36000000, 1, 32, 3, 4, 0 },
-        {  60000000, 1, 60, 3, 3, 0 },
-        {  72000000, 1, 72, 3, 3, 0 },
-        {  80000000, 1, 80, 3, 3, 0 },
-        {  84000000, 0, 42, 3, 2, 0 },
-        {  50000000, 0, 50, 3, 3, 0 },
-};
-
-static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        epll_con = __raw_readl(S5P_EPLL_CON);
-        epll_con_k = __raw_readl(S5P_EPLL_CON1);
-
-        epll_con_k &= ~PLL46XX_KDIV_MASK;
-        epll_con &= ~(1 << 27 |
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k |= epll_div[i][5] << 0;
-                        epll_con |= (epll_div[i][1] << 27 |
-                                        epll_div[i][2] << PLL46XX_MDIV_SHIFT |
-                                        epll_div[i][3] << PLL46XX_PDIV_SHIFT |
-                                        epll_div[i][4] << PLL46XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P_EPLL_CON);
-        __raw_writel(epll_con_k, S5P_EPLL_CON1);
-
-        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
-                        clk->rate, rate);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5pv210_epll_ops = {
-        .set_rate = s5pv210_epll_set_rate,
-        .get_rate = s5p_epll_get_rate,
-};
-
-static u32 vpll_div[][5] = {
-        {  54000000, 3, 53, 3, 0 },
-        { 108000000, 3, 53, 2, 0 },
-};
-
-static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con = __raw_readl(S5P_VPLL_CON);
-        vpll_con &= ~(0x1 << 27 |                                       \
-                        PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-                if (vpll_div[i][0] == rate) {
-                        vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
-                        vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
-                        vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
-                        vpll_con |= vpll_div[i][4] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con, S5P_VPLL_CON);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-static struct clk_ops s5pv210_vpll_ops = {
-        .get_rate = s5pv210_vpll_get_rate,
-        .set_rate = s5pv210_vpll_set_rate,
-};
-
-void __init_or_cpufreq s5pv210_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long vpllsrc;
-        unsigned long armclk;
-        unsigned long hclk_msys;
-        unsigned long hclk_dsys;
-        unsigned long hclk_psys;
-        unsigned long pclk_msys;
-        unsigned long pclk_dsys;
-        unsigned long pclk_psys;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned int ptr;
-        u32 clkdiv0, clkdiv1;
-
-        /* Set functions for clk_fout_epll */
-        clk_fout_epll.enable = s5p_epll_enable;
-        clk_fout_epll.ops = &s5pv210_epll_ops;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        clkdiv0 = __raw_readl(S5P_CLK_DIV0);
-        clkdiv1 = __raw_readl(S5P_CLK_DIV1);
-
-        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
-                                __func__, clkdiv0, clkdiv1);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
-        epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
-                                __raw_readl(S5P_EPLL_CON1), pll_4600);
-        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-        vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
-
-        clk_fout_apll.ops = &clk_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &s5pv210_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&clk_armclk.clk);
-        hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
-        hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
-        hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
-        pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
-        pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
-        pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
-
-        printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
-                         "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
-                        armclk, hclk_msys, hclk_dsys, hclk_psys,
-                        pclk_msys, pclk_dsys, pclk_psys);
-
-        clk_f.rate = armclk;
-        clk_h.rate = hclk_psys;
-        clk_p.rate = pclk_psys;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_sclk_hdmi27m,
-        &clk_sclk_hdmiphy,
-        &clk_sclk_usbphy0,
-        &clk_sclk_usbphy1,
-        &clk_pcmcdclk0,
-        &clk_pcmcdclk1,
-        &clk_pcmcdclk2,
-};
-
-static struct clk_lookup s5pv210_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
-        CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
-        CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
-        CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
-        CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-};
-
-void __init s5pv210_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-                s3c_register_clksrc(sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-                s3c_disable_clocks(clk_cdev[ptr], 1);
-
-}
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
deleted file mode 100644
index 7024dcd0e40a..000000000000
--- a/arch/arm/mach-s5pv210/common.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Codes for S5PV210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <clocksource/samsung_pwm.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-
-#include <asm/proc-fns.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/adc-core.h>
-#include <plat/ata-core.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/keypad-core.h>
-#include <plat/pwm-core.h>
-#include <plat/tv-core.h>
-#include <plat/spi-core.h>
-
-#include "common.h"
-
-static const char name_s5pv210[] = "S5PV210/S5PC110";
-
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = S5PV210_CPU_ID,
-                .idmask         = S5PV210_CPU_MASK,
-                .map_io         = s5pv210_map_io,
-                .init_clocks    = s5pv210_init_clocks,
-                .init_uarts     = s5pv210_init_uarts,
-                .init           = s5pv210_init,
-                .name           = name_s5pv210,
-        },
-};
-
-/* Initial IO mappings */
-
-static struct map_desc s5pv210_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(S5PV210_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_SYS,
-                .pfn            = __phys_to_pfn(S5PV210_PA_SYSCON),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(S5PV210_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(S5PV210_PA_WATCHDOG),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_SROMC,
-                .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(S5PV210_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5PV210_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC2),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC3,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC3),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_DMC0,
-                .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_DMC1,
-                .pfn            = __phys_to_pfn(S5PV210_PA_DMC1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-                .pfn            =__phys_to_pfn(S5PV210_PA_HSPHY),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }
-};
-
-void s5pv210_restart(enum reboot_mode mode, const char *cmd)
-{
-        __raw_writel(0x1, S5P_SWRESET);
-}
-
-static struct samsung_pwm_variant s5pv210_pwm_variant = {
-        .bits           = 32,
-        .div_base       = 0,
-        .has_tint_cstat = true,
-        .tclk_mask      = (1 << 5),
-};
-
-void __init samsung_set_timer_source(unsigned int event, unsigned int source)
-{
-        s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
-        s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
-}
-
-void __init samsung_timer_init(void)
-{
-        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
-                IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
-                IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
-        };
-
-        samsung_pwm_clocksource_init(S3C_VA_TIMER,
-                                        timer_irqs, &s5pv210_pwm_variant);
-}
-
-/*
- * s5pv210_map_io
- *
- * register the standard cpu IO areas
- */
-
-void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
-{
-        /* initialize the io descriptors we need for initialization */
-        iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
-        if (mach_desc)
-                iotable_init(mach_desc, size);
-
-        /* detect cpu id and rev. */
-        s5p_init_cpu(S5P_VA_CHIPID);
-
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
-
-        samsung_pwm_set_platdata(&s5pv210_pwm_variant);
-}
-
-void __init s5pv210_map_io(void)
-{
-        /* initialise device information early */
-        s5pv210_default_sdhci0();
-        s5pv210_default_sdhci1();
-        s5pv210_default_sdhci2();
-        s5pv210_default_sdhci3();
-
-        s3c_adc_setname("samsung-adc-v3");
-
-        s3c_cfcon_setname("s5pv210-pata");
-
-        s3c_fimc_setname(0, "s5pv210-fimc");
-        s3c_fimc_setname(1, "s5pv210-fimc");
-        s3c_fimc_setname(2, "s5pv210-fimc");
-
-        /* the i2c devices are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-
-        s3c_fb_setname("s5pv210-fb");
-
-        /* Use s5pv210-keypad instead of samsung-keypad */
-        samsung_keypad_setname("s5pv210-keypad");
-
-        /* setup TV devices */
-        s5p_hdmi_setname("s5pv210-hdmi");
-
-        s3c64xx_spi_setname("s5pv210-spi");
-}
-
-void __init s5pv210_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5pv210_register_clocks();
-        s5pv210_setup_clocks();
-}
-
-void __init s5pv210_init_irq(void)
-{
-        u32 vic[4];     /* S5PV210 supports 4 VIC */
-
-        /* All the VICs are fully populated. */
-        vic[0] = ~0;
-        vic[1] = ~0;
-        vic[2] = ~0;
-        vic[3] = ~0;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-
-struct bus_type s5pv210_subsys = {
-        .name           = "s5pv210-core",
-        .dev_name       = "s5pv210-core",
-};
-
-static struct device s5pv210_dev = {
-        .bus    = &s5pv210_subsys,
-};
-
-static int __init s5pv210_core_init(void)
-{
-        return subsys_system_register(&s5pv210_subsys, NULL);
-}
-core_initcall(s5pv210_core_init);
-
-int __init s5pv210_init(void)
-{
-        printk(KERN_INFO "S5PV210: Initializing architecture\n");
-        return device_register(&s5pv210_dev);
-}
-
-/* uart registration process */
-
-void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index fe1beb54e548..2ad387c1ecf0 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,19 +12,12 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
 
-#include <linux/reboot.h>
-
-void s5pv210_init_io(struct map_desc *mach_desc, int size);
-void s5pv210_init_irq(void);
-
-void s5pv210_register_clocks(void);
-void s5pv210_setup_clocks(void);
-
-void s5pv210_restart(enum reboot_mode mode, const char *cmd);
-
-extern  int s5pv210_init(void);
-extern void s5pv210_map_io(void);
-extern void s5pv210_init_clocks(int xtal);
-extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#ifdef CONFIG_PM_SLEEP
+u32 exynos_get_eint_wake_mask(void);
+void s5pv210_cpu_resume(void);
+void s5pv210_pm_init(void);
+#else
+static inline void s5pv210_pm_init(void) {}
+#endif
 
 #endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
deleted file mode 100644
index 90356ad10c54..000000000000
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/gpio-samsung.h>
-
-#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
-
-static int s5pv210_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = s5pv210_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                         | QUIRK_NEED_RSTCLR,
-                        .idma_addr = S5PV210_AUDSS_INT_MEM,
-                },
-        },
-};
-
-static struct resource s5pv210_iis0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-};
-
-struct platform_device s5pv210_device_iis0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources    = ARRAY_SIZE(s5pv210_iis0_resource),
-        .resource         = s5pv210_iis0_resource,
-        .dev = {
-                .platform_data = &i2sv5_pdata,
-        },
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = s5pv210_cfg_i2s,
-};
-
-static struct resource s5pv210_iis1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-
-struct platform_device s5pv210_device_iis1 = {
-        .name             = "samsung-i2s",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pv210_iis1_resource),
-        .resource         = s5pv210_iis1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-static struct resource s5pv210_iis2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-
-struct platform_device s5pv210_device_iis2 = {
-        .name             = "samsung-i2s",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s5pv210_iis2_resource),
-        .resource         = s5pv210_iis2_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
-                break;
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5pv210_pcm_cfg_gpio,
-};
-
-static struct resource s5pv210_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-
-struct platform_device s5pv210_device_pcm0 = {
-        .name             = "samsung-pcm",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pv210_pcm0_resource),
-        .resource         = s5pv210_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource s5pv210_pcm1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-};
-
-struct platform_device s5pv210_device_pcm1 = {
-        .name             = "samsung-pcm",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pv210_pcm1_resource),
-        .resource         = s5pv210_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource s5pv210_pcm2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-};
-
-struct platform_device s5pv210_device_pcm2 = {
-        .name             = "samsung-pcm",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s5pv210_pcm2_resource),
-        .resource         = s5pv210_pcm2_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-/* AC97 Controller platform devices */
-
-static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
-{
-        return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource s5pv210_ac97_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        [4] = DEFINE_RES_IRQ(IRQ_AC97),
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = s5pv210_ac97_cfg_gpio,
-};
-
-static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pv210_device_ac97 = {
-        .name             = "samsung-ac97",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s5pv210_ac97_resource),
-        .resource         = s5pv210_ac97_resource,
-        .dev = {
-                .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &s5pv210_ac97_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-/* S/PDIF Controller platform_device */
-
-static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
-
-        return 0;
-}
-
-static struct resource s5pv210_spdif_resource[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-};
-
-static struct s3c_audio_pdata samsung_spdif_pdata = {
-        .cfg_gpio = s5pv210_spdif_cfg_gpio,
-};
-
-static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5pv210_device_spdif = {
-        .name           = "samsung-spdif",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5pv210_spdif_resource),
-        .resource       = s5pv210_spdif_resource,
-        .dev = {
-                .platform_data = &samsung_spdif_pdata,
-                .dma_mask = &s5pv210_spdif_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
deleted file mode 100644
index b8337e248b09..000000000000
--- a/arch/arm/mach-s5pv210/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-
-static u8 pdma0_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_MAX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MAX,
-        DMACH_PWM,
-        DMACH_SPDIF,
-};
-
-static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri_id = pdma0_peri,
-};
-
-static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
-        S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
-
-static u8 pdma1_peri[] = {
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_MAX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_MAX,
-        DMACH_MAX,
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MSM_REQ0,
-        DMACH_MSM_REQ1,
-        DMACH_MSM_REQ2,
-        DMACH_MSM_REQ3,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-};
-
-static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri_id = pdma1_peri,
-};
-
-static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
-        S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
-
-static int __init s5pv210_dma_init(void)
-{
-        dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
-
-        dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
-
-        return 0;
-}
-arch_initcall(s5pv210_dma_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h b/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h
deleted file mode 100644
index e193b891e7b2..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
-
-/* GPIO bank sizes */
-#define S5PV210_GPIO_A0_NR      (8)
-#define S5PV210_GPIO_A1_NR      (4)
-#define S5PV210_GPIO_B_NR       (8)
-#define S5PV210_GPIO_C0_NR      (5)
-#define S5PV210_GPIO_C1_NR      (5)
-#define S5PV210_GPIO_D0_NR      (4)
-#define S5PV210_GPIO_D1_NR      (6)
-#define S5PV210_GPIO_E0_NR      (8)
-#define S5PV210_GPIO_E1_NR      (5)
-#define S5PV210_GPIO_F0_NR      (8)
-#define S5PV210_GPIO_F1_NR      (8)
-#define S5PV210_GPIO_F2_NR      (8)
-#define S5PV210_GPIO_F3_NR      (6)
-#define S5PV210_GPIO_G0_NR      (7)
-#define S5PV210_GPIO_G1_NR      (7)
-#define S5PV210_GPIO_G2_NR      (7)
-#define S5PV210_GPIO_G3_NR      (7)
-#define S5PV210_GPIO_H0_NR      (8)
-#define S5PV210_GPIO_H1_NR      (8)
-#define S5PV210_GPIO_H2_NR      (8)
-#define S5PV210_GPIO_H3_NR      (8)
-#define S5PV210_GPIO_I_NR       (7)
-#define S5PV210_GPIO_J0_NR      (8)
-#define S5PV210_GPIO_J1_NR      (6)
-#define S5PV210_GPIO_J2_NR      (8)
-#define S5PV210_GPIO_J3_NR      (8)
-#define S5PV210_GPIO_J4_NR      (5)
-
-#define S5PV210_GPIO_MP01_NR    (8)
-#define S5PV210_GPIO_MP02_NR    (4)
-#define S5PV210_GPIO_MP03_NR    (8)
-#define S5PV210_GPIO_MP04_NR    (8)
-#define S5PV210_GPIO_MP05_NR    (8)
-
-/* GPIO bank numbers */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-
-#define S5PV210_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5PV210_GPIO_A0_START   = 0,
-        S5PV210_GPIO_A1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_A0),
-        S5PV210_GPIO_B_START    = S5PV210_GPIO_NEXT(S5PV210_GPIO_A1),
-        S5PV210_GPIO_C0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_B),
-        S5PV210_GPIO_C1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_C0),
-        S5PV210_GPIO_D0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_C1),
-        S5PV210_GPIO_D1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_D0),
-        S5PV210_GPIO_E0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_D1),
-        S5PV210_GPIO_E1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_E0),
-        S5PV210_GPIO_F0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_E1),
-        S5PV210_GPIO_F1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_F0),
-        S5PV210_GPIO_F2_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_F1),
-        S5PV210_GPIO_F3_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_F2),
-        S5PV210_GPIO_G0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_F3),
-        S5PV210_GPIO_G1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_G0),
-        S5PV210_GPIO_G2_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_G1),
-        S5PV210_GPIO_G3_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_G2),
-        S5PV210_GPIO_H0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_G3),
-        S5PV210_GPIO_H1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_H0),
-        S5PV210_GPIO_H2_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_H1),
-        S5PV210_GPIO_H3_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_H2),
-        S5PV210_GPIO_I_START    = S5PV210_GPIO_NEXT(S5PV210_GPIO_H3),
-        S5PV210_GPIO_J0_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_I),
-        S5PV210_GPIO_J1_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J0),
-        S5PV210_GPIO_J2_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
-        S5PV210_GPIO_J3_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
-        S5PV210_GPIO_J4_START   = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
-        S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
-        S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
-        S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
-        S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
-        S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
-};
-
-/* S5PV210 GPIO number definitions */
-#define S5PV210_GPA0(_nr)       (S5PV210_GPIO_A0_START + (_nr))
-#define S5PV210_GPA1(_nr)       (S5PV210_GPIO_A1_START + (_nr))
-#define S5PV210_GPB(_nr)        (S5PV210_GPIO_B_START + (_nr))
-#define S5PV210_GPC0(_nr)       (S5PV210_GPIO_C0_START + (_nr))
-#define S5PV210_GPC1(_nr)       (S5PV210_GPIO_C1_START + (_nr))
-#define S5PV210_GPD0(_nr)       (S5PV210_GPIO_D0_START + (_nr))
-#define S5PV210_GPD1(_nr)       (S5PV210_GPIO_D1_START + (_nr))
-#define S5PV210_GPE0(_nr)       (S5PV210_GPIO_E0_START + (_nr))
-#define S5PV210_GPE1(_nr)       (S5PV210_GPIO_E1_START + (_nr))
-#define S5PV210_GPF0(_nr)       (S5PV210_GPIO_F0_START + (_nr))
-#define S5PV210_GPF1(_nr)       (S5PV210_GPIO_F1_START + (_nr))
-#define S5PV210_GPF2(_nr)       (S5PV210_GPIO_F2_START + (_nr))
-#define S5PV210_GPF3(_nr)       (S5PV210_GPIO_F3_START + (_nr))
-#define S5PV210_GPG0(_nr)       (S5PV210_GPIO_G0_START + (_nr))
-#define S5PV210_GPG1(_nr)       (S5PV210_GPIO_G1_START + (_nr))
-#define S5PV210_GPG2(_nr)       (S5PV210_GPIO_G2_START + (_nr))
-#define S5PV210_GPG3(_nr)       (S5PV210_GPIO_G3_START + (_nr))
-#define S5PV210_GPH0(_nr)       (S5PV210_GPIO_H0_START + (_nr))
-#define S5PV210_GPH1(_nr)       (S5PV210_GPIO_H1_START + (_nr))
-#define S5PV210_GPH2(_nr)       (S5PV210_GPIO_H2_START + (_nr))
-#define S5PV210_GPH3(_nr)       (S5PV210_GPIO_H3_START + (_nr))
-#define S5PV210_GPI(_nr)        (S5PV210_GPIO_I_START + (_nr))
-#define S5PV210_GPJ0(_nr)       (S5PV210_GPIO_J0_START + (_nr))
-#define S5PV210_GPJ1(_nr)       (S5PV210_GPIO_J1_START + (_nr))
-#define S5PV210_GPJ2(_nr)       (S5PV210_GPIO_J2_START + (_nr))
-#define S5PV210_GPJ3(_nr)       (S5PV210_GPIO_J3_START + (_nr))
-#define S5PV210_GPJ4(_nr)       (S5PV210_GPIO_J4_START + (_nr))
-#define S5PV210_MP01(_nr)       (S5PV210_GPIO_MP01_START + (_nr))
-#define S5PV210_MP02(_nr)       (S5PV210_GPIO_MP02_START + (_nr))
-#define S5PV210_MP03(_nr)       (S5PV210_GPIO_MP03_START + (_nr))
-#define S5PV210_MP04(_nr)       (S5PV210_GPIO_MP04_START + (_nr))
-#define S5PV210_MP05(_nr)       (S5PV210_GPIO_MP05_START + (_nr))
-
-/* the end of the S5PV210 specific gpios */
-#define S5PV210_GPIO_END        (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
-#define S3C_GPIO_END            S5PV210_GPIO_END
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/hardware.h b/arch/arm/mach-s5pv210/include/mach/hardware.h
deleted file mode 100644
index fada7a392d09..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/hardware.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
deleted file mode 100644
index 5e0de3a31f3d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* VIC0: System, DMA, Timer */
-
-#define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
-#define IRQ_BATF                S5P_IRQ_VIC0(17)
-#define IRQ_MDMA                S5P_IRQ_VIC0(18)
-#define IRQ_PDMA0               S5P_IRQ_VIC0(19)
-#define IRQ_PDMA1               S5P_IRQ_VIC0(20)
-#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
-#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
-#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
-#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
-#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
-#define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
-#define IRQ_WDT                 S5P_IRQ_VIC0(27)
-#define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
-#define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
-#define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
-#define IRQ_FIMC3               S5P_IRQ_VIC0(31)
-
-/* VIC1: ARM, Power, Memory, Connectivity, Storage */
-
-#define IRQ_PMU                 S5P_IRQ_VIC1(0)
-#define IRQ_CORTEX1             S5P_IRQ_VIC1(1)
-#define IRQ_CORTEX2             S5P_IRQ_VIC1(2)
-#define IRQ_CORTEX3             S5P_IRQ_VIC1(3)
-#define IRQ_CORTEX4             S5P_IRQ_VIC1(4)
-#define IRQ_IEMAPC              S5P_IRQ_VIC1(5)
-#define IRQ_IEMIEC              S5P_IRQ_VIC1(6)
-#define IRQ_ONENAND             S5P_IRQ_VIC1(7)
-#define IRQ_NFC                 S5P_IRQ_VIC1(8)
-#define IRQ_CFCON               S5P_IRQ_VIC1(9)
-#define IRQ_UART0               S5P_IRQ_VIC1(10)
-#define IRQ_UART1               S5P_IRQ_VIC1(11)
-#define IRQ_UART2               S5P_IRQ_VIC1(12)
-#define IRQ_UART3               S5P_IRQ_VIC1(13)
-#define IRQ_IIC                 S5P_IRQ_VIC1(14)
-#define IRQ_SPI0                S5P_IRQ_VIC1(15)
-#define IRQ_SPI1                S5P_IRQ_VIC1(16)
-#define IRQ_SPI2                S5P_IRQ_VIC1(17)
-#define IRQ_IRDA                S5P_IRQ_VIC1(18)
-#define IRQ_IIC2                S5P_IRQ_VIC1(19)
-#define IRQ_IIC_HDMIPHY         S5P_IRQ_VIC1(20)
-#define IRQ_HSIRX               S5P_IRQ_VIC1(21)
-#define IRQ_HSITX               S5P_IRQ_VIC1(22)
-#define IRQ_UHOST               S5P_IRQ_VIC1(23)
-#define IRQ_OTG                 S5P_IRQ_VIC1(24)
-#define IRQ_MSM                 S5P_IRQ_VIC1(25)
-#define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
-#define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
-#define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
-#define IRQ_MIPI_CSIS           S5P_IRQ_VIC1(29)
-#define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
-#define IRQ_ONENAND_AUDI        S5P_IRQ_VIC1(31)
-
-/* VIC2: Multimedia, Audio, Security */
-
-#define IRQ_LCD0                S5P_IRQ_VIC2(0)
-#define IRQ_LCD1                S5P_IRQ_VIC2(1)
-#define IRQ_LCD2                S5P_IRQ_VIC2(2)
-#define IRQ_LCD3                S5P_IRQ_VIC2(3)
-#define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
-#define IRQ_FIMC0               S5P_IRQ_VIC2(5)
-#define IRQ_FIMC1               S5P_IRQ_VIC2(6)
-#define IRQ_FIMC2               S5P_IRQ_VIC2(7)
-#define IRQ_JPEG                S5P_IRQ_VIC2(8)
-#define IRQ_2D                  S5P_IRQ_VIC2(9)
-#define IRQ_3D                  S5P_IRQ_VIC2(10)
-#define IRQ_MIXER               S5P_IRQ_VIC2(11)
-#define IRQ_HDMI                S5P_IRQ_VIC2(12)
-#define IRQ_IIC1                S5P_IRQ_VIC2(13)
-#define IRQ_MFC                 S5P_IRQ_VIC2(14)
-#define IRQ_SDO                 S5P_IRQ_VIC2(15)
-#define IRQ_I2S0                S5P_IRQ_VIC2(16)
-#define IRQ_I2S1                S5P_IRQ_VIC2(17)
-#define IRQ_I2S2                S5P_IRQ_VIC2(18)
-#define IRQ_AC97                S5P_IRQ_VIC2(19)
-#define IRQ_PCM0                S5P_IRQ_VIC2(20)
-#define IRQ_PCM1                S5P_IRQ_VIC2(21)
-#define IRQ_SPDIF               S5P_IRQ_VIC2(22)
-#define IRQ_ADC                 S5P_IRQ_VIC2(23)
-#define IRQ_PENDN               S5P_IRQ_VIC2(24)
-#define IRQ_TC                  IRQ_PENDN
-#define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
-#define IRQ_CG                  S5P_IRQ_VIC2(26)
-#define IRQ_SSS_INT             S5P_IRQ_VIC2(27)
-#define IRQ_SSS_HASH            S5P_IRQ_VIC2(28)
-#define IRQ_PCM2                S5P_IRQ_VIC2(29)
-#define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
-#define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
-
-/* VIC3: Etc */
-
-#define IRQ_IPC                 S5P_IRQ_VIC3(0)
-#define IRQ_HOSTIF              S5P_IRQ_VIC3(1)
-#define IRQ_HSMMC3              S5P_IRQ_VIC3(2)
-#define IRQ_CEC                 S5P_IRQ_VIC3(3)
-#define IRQ_TSI                 S5P_IRQ_VIC3(4)
-#define IRQ_MDNIE0              S5P_IRQ_VIC3(5)
-#define IRQ_MDNIE1              S5P_IRQ_VIC3(6)
-#define IRQ_MDNIE2              S5P_IRQ_VIC3(7)
-#define IRQ_MDNIE3              S5P_IRQ_VIC3(8)
-#define IRQ_VIC_END             S5P_IRQ_VIC3(31)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
-#define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
-
-/* GPIO interrupt */
-#define S5P_GPIOINT_BASE        (IRQ_EINT(31) + 1)
-#define S5P_GPIOINT_GROUP_MAXNR 22
-
-/* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
-
-/* Compatibility */
-#define IRQ_LCD_FIFO            IRQ_LCD0
-#define IRQ_LCD_VSYNC           IRQ_LCD1
-#define IRQ_LCD_SYSTEM          IRQ_LCD2
-#define IRQ_MIPI_CSIS0          IRQ_MIPI_CSIS
-
-#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
deleted file mode 100644
index 763929aca52d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/map.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5PV210_PA_SDRAM                0x20000000
-
-#define S5PV210_PA_SROM_BANK5           0xA8000000
-
-#define S5PC110_PA_ONENAND              0xB0000000
-#define S5PC110_PA_ONENAND_DMA          0xB0600000
-
-#define S5PV210_PA_CHIPID               0xE0000000
-
-#define S5PV210_PA_SYSCON               0xE0100000
-
-#define S5PV210_PA_GPIO                 0xE0200000
-
-#define S5PV210_PA_SPDIF                0xE1100000
-
-#define S5PV210_PA_SPI0                 0xE1300000
-#define S5PV210_PA_SPI1                 0xE1400000
-
-#define S5PV210_PA_KEYPAD               0xE1600000
-
-#define S5PV210_PA_ADC                  0xE1700000
-
-#define S5PV210_PA_IIC0                 0xE1800000
-#define S5PV210_PA_IIC1                 0xFAB00000
-#define S5PV210_PA_IIC2                 0xE1A00000
-
-#define S5PV210_PA_AC97                 0xE2200000
-
-#define S5PV210_PA_PCM0                 0xE2300000
-#define S5PV210_PA_PCM1                 0xE1200000
-#define S5PV210_PA_PCM2                 0xE2B00000
-
-#define S5PV210_PA_TIMER                0xE2500000
-#define S5PV210_PA_SYSTIMER             0xE2600000
-#define S5PV210_PA_WATCHDOG             0xE2700000
-#define S5PV210_PA_RTC                  0xE2800000
-
-#define S5PV210_PA_UART                 0xE2900000
-
-#define S5PV210_PA_SROMC                0xE8000000
-
-#define S5PV210_PA_CFCON                0xE8200000
-
-#define S5PV210_PA_MFC                  0xF1700000
-
-#define S5PV210_PA_HSMMC(x)             (0xEB000000 + ((x) * 0x100000))
-
-#define S5PV210_PA_HSOTG                0xEC000000
-#define S5PV210_PA_HSPHY                0xEC100000
-
-#define S5PV210_PA_IIS0                 0xEEE30000
-#define S5PV210_PA_IIS1                 0xE2100000
-#define S5PV210_PA_IIS2                 0xE2A00000
-
-#define S5PV210_PA_DMC0                 0xF0000000
-#define S5PV210_PA_DMC1                 0xF1400000
-
-#define S5PV210_PA_VIC0                 0xF2000000
-#define S5PV210_PA_VIC1                 0xF2100000
-#define S5PV210_PA_VIC2                 0xF2200000
-#define S5PV210_PA_VIC3                 0xF2300000
-
-#define S5PV210_PA_FB                   0xF8000000
-
-#define S5PV210_PA_MDMA                 0xFA200000
-#define S5PV210_PA_PDMA0                0xE0900000
-#define S5PV210_PA_PDMA1                0xE0A00000
-
-#define S5PV210_PA_MIPI_CSIS            0xFA600000
-
-#define S5PV210_PA_FIMC0                0xFB200000
-#define S5PV210_PA_FIMC1                0xFB300000
-#define S5PV210_PA_FIMC2                0xFB400000
-
-#define S5PV210_PA_JPEG                 0xFB600000
-
-#define S5PV210_PA_SDO                  0xF9000000
-#define S5PV210_PA_VP                   0xF9100000
-#define S5PV210_PA_MIXER                0xF9200000
-#define S5PV210_PA_HDMI                 0xFA100000
-#define S5PV210_PA_IIC_HDMIPHY          0xFA900000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_FB                       S5PV210_PA_FB
-#define S3C_PA_HSMMC0                   S5PV210_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   S5PV210_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   S5PV210_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                   S5PV210_PA_HSMMC(3)
-#define S3C_PA_IIC                      S5PV210_PA_IIC0
-#define S3C_PA_IIC1                     S5PV210_PA_IIC1
-#define S3C_PA_IIC2                     S5PV210_PA_IIC2
-#define S3C_PA_RTC                      S5PV210_PA_RTC
-#define S3C_PA_USB_HSOTG                S5PV210_PA_HSOTG
-#define S3C_PA_WDT                      S5PV210_PA_WATCHDOG
-#define S3C_PA_SPI0                     S5PV210_PA_SPI0
-#define S3C_PA_SPI1                     S5PV210_PA_SPI1
-
-#define S5P_PA_CHIPID                   S5PV210_PA_CHIPID
-#define S5P_PA_FIMC0                    S5PV210_PA_FIMC0
-#define S5P_PA_FIMC1                    S5PV210_PA_FIMC1
-#define S5P_PA_FIMC2                    S5PV210_PA_FIMC2
-#define S5P_PA_MIPI_CSIS0               S5PV210_PA_MIPI_CSIS
-#define S5P_PA_MFC                      S5PV210_PA_MFC
-#define S5P_PA_IIC_HDMIPHY              S5PV210_PA_IIC_HDMIPHY
-
-#define S5P_PA_SDO                      S5PV210_PA_SDO
-#define S5P_PA_VP                       S5PV210_PA_VP
-#define S5P_PA_MIXER                    S5PV210_PA_MIXER
-#define S5P_PA_HDMI                     S5PV210_PA_HDMI
-
-#define S5P_PA_ONENAND                  S5PC110_PA_ONENAND
-#define S5P_PA_ONENAND_DMA              S5PC110_PA_ONENAND_DMA
-#define S5P_PA_SDRAM                    S5PV210_PA_SDRAM
-#define S5P_PA_SROMC                    S5PV210_PA_SROMC
-#define S5P_PA_SYSCON                   S5PV210_PA_SYSCON
-#define S5P_PA_TIMER                    S5PV210_PA_TIMER
-
-#define S5P_PA_JPEG                     S5PV210_PA_JPEG
-
-#define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
-#define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
-#define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
-#define SAMSUNG_PA_TIMER                S5PV210_PA_TIMER
-
-/* UART */
-
-#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-
-#define S3C_PA_UART                     S5PV210_PA_UART
-
-#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-
-#define S5P_SZ_UART                     SZ_256
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
deleted file mode 100644
index d584fac9156b..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/memory.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/memory.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Memory definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Sparsemem support
- * Physical memory can be located from 0x20000000 to 0x7fffffff,
- * so MAX_PHYSMEM_BITS is 31.
- */
-
-#define MAX_PHYSMEM_BITS        31
-#define SECTION_SIZE_BITS       28
-
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
deleted file mode 100644
index eba8aea63ed8..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-static inline void s3c_pm_debug_init_uart(void)
-{
-        /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-        __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
-}
-
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-        /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-        /* nothing here yet */
-}
-
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
-                                           struct pm_uart_save *save)
-{
-        /* nothing here yet */
-}
-
-static inline void s3c_pm_restored_gpios(void) { }
-static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index e345584d4c34..b14ffcd7f6cc 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_REGS_CLOCK_H
 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
 
-#include <mach/map.h>
+#include <plat/map-base.h>
 
 #define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
 
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
deleted file mode 100644
index de0c89976078..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV210 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-
-#define S5PV210_EINT30CON               (S5P_VA_GPIO + 0xE00)
-#define S5P_EINT_CON(x)                 (S5PV210_EINT30CON + ((x) * 0x4))
-
-#define S5PV210_EINT30FLTCON0           (S5P_VA_GPIO + 0xE80)
-#define S5P_EINT_FLTCON(x)              (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
-
-#define S5PV210_EINT30MASK              (S5P_VA_GPIO + 0xF00)
-#define S5P_EINT_MASK(x)                (S5PV210_EINT30MASK + ((x) * 0x4))
-
-#define S5PV210_EINT30PEND              (S5P_VA_GPIO + 0xF40)
-#define S5P_EINT_PEND(x)                (S5PV210_EINT30PEND + ((x) * 0x4))
-
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE               S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)          S5PV210_GPH0(x)
-#define EINT_GPIO_1(x)          S5PV210_GPH1(x)
-#define EINT_GPIO_2(x)          S5PV210_GPH2(x)
-#define EINT_GPIO_3(x)          S5PV210_GPH3(x)
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
deleted file mode 100644
index d8bc1e6c7aaa..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/regs-irq.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
deleted file mode 100644
index 4262d8ff1988..000000000000
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ /dev/null
@@ -1,688 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/mach-aquila.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/fb.h>
-#include <linux/i2c.h>
-#include <linux/i2c-gpio.h>
-#include <linux/mfd/max8998.h>
-#include <linux/mfd/wm8994/pdata.h>
-#include <linux/regulator/fixed.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/gpio-samsung.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/fb.h>
-#include <plat/fimc-core.h>
-#include <plat/sdhci.h>
-#include <plat/samsung-time.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define AQUILA_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define AQUILA_ULCON_DEFAULT    S3C2410_LCON_CS8
-
-#define AQUILA_UFCON_DEFAULT    S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = AQUILA_UCON_DEFAULT,
-                .ulcon          = AQUILA_ULCON_DEFAULT,
-                /*
-                 * Actually UART0 can support 256 bytes fifo, but aquila board
-                 * supports 128 bytes fifo because of initial chip bug
-                 */
-                .ufcon          = AQUILA_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = AQUILA_UCON_DEFAULT,
-                .ulcon          = AQUILA_ULCON_DEFAULT,
-                .ufcon          = AQUILA_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = AQUILA_UCON_DEFAULT,
-                .ulcon          = AQUILA_ULCON_DEFAULT,
-                .ufcon          = AQUILA_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = AQUILA_UCON_DEFAULT,
-                .ulcon          = AQUILA_ULCON_DEFAULT,
-                .ufcon          = AQUILA_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
-        },
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win aquila_fb_win0 = {
-        .max_bpp = 32,
-        .default_bpp = 16,
-        .xres = 480,
-        .yres = 800,
-};
-
-static struct s3c_fb_pd_win aquila_fb_win1 = {
-        .max_bpp = 32,
-        .default_bpp = 16,
-        .xres = 480,
-        .yres = 800,
-};
-
-static struct fb_videomode aquila_lcd_timing = {
-        .left_margin = 16,
-        .right_margin = 16,
-        .upper_margin = 3,
-        .lower_margin = 28,
-        .hsync_len = 2,
-        .vsync_len = 2,
-        .xres = 480,
-        .yres = 800,
-};
-
-static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
-        .win[0]         = &aquila_fb_win0,
-        .win[1]         = &aquila_fb_win1,
-        .vtiming        = &aquila_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                          VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
-        .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
-};
-
-/* MAX8998 regulators */
-#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
-
-static struct regulator_init_data aquila_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled = 1,
-                },
-        },
-};
-
-static struct regulator_init_data aquila_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB+MIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo4_data = {
-        .constraints    = {
-                .name           = "VDAC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo5_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo6_data = {
-        .constraints    = {
-                .name           = "VCC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo7_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC+VCAM_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo11_data = {
-        .constraints    = {
-                .name           = "CAM_IO_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo12_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo13_data = {
-        .constraints    = {
-                .name           = "CAM_A_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo14_data = {
-        .constraints    = {
-                .name           = "CAM_CIF_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo15_data = {
-        .constraints    = {
-                .name           = "CAM_AF_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo16_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data aquila_ldo17_data = {
-        .constraints    = {
-                .name           = "CAM_8M_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-/* BUCK */
-static struct regulator_consumer_supply buck1_consumer =
-        REGULATOR_SUPPLY("vddarm", NULL);
-
-static struct regulator_consumer_supply buck2_consumer =
-        REGULATOR_SUPPLY("vddint", NULL);
-
-static struct regulator_init_data aquila_buck1_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &buck1_consumer,
-};
-
-static struct regulator_init_data aquila_buck2_data = {
-        .constraints    = {
-                .name           = "VINT_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &buck2_consumer,
-};
-
-static struct regulator_init_data aquila_buck3_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .enabled = 1,
-                },
-        },
-};
-
-static struct regulator_init_data aquila_buck4_data = {
-        .constraints    = {
-                .name           = "CAM_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct max8998_regulator_data aquila_regulators[] = {
-        { MAX8998_LDO2,  &aquila_ldo2_data },
-        { MAX8998_LDO3,  &aquila_ldo3_data },
-        { MAX8998_LDO4,  &aquila_ldo4_data },
-        { MAX8998_LDO5,  &aquila_ldo5_data },
-        { MAX8998_LDO6,  &aquila_ldo6_data },
-        { MAX8998_LDO7,  &aquila_ldo7_data },
-        { MAX8998_LDO8,  &aquila_ldo8_data },
-        { MAX8998_LDO9,  &aquila_ldo9_data },
-        { MAX8998_LDO10, &aquila_ldo10_data },
-        { MAX8998_LDO11, &aquila_ldo11_data },
-        { MAX8998_LDO12, &aquila_ldo12_data },
-        { MAX8998_LDO13, &aquila_ldo13_data },
-        { MAX8998_LDO14, &aquila_ldo14_data },
-        { MAX8998_LDO15, &aquila_ldo15_data },
-        { MAX8998_LDO16, &aquila_ldo16_data },
-        { MAX8998_LDO17, &aquila_ldo17_data },
-        { MAX8998_BUCK1, &aquila_buck1_data },
-        { MAX8998_BUCK2, &aquila_buck2_data },
-        { MAX8998_BUCK3, &aquila_buck3_data },
-        { MAX8998_BUCK4, &aquila_buck4_data },
-};
-
-static struct max8998_platform_data aquila_max8998_pdata = {
-        .num_regulators = ARRAY_SIZE(aquila_regulators),
-        .regulators     = aquila_regulators,
-        .buck1_set1     = S5PV210_GPH0(3),
-        .buck1_set2     = S5PV210_GPH0(4),
-        .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_voltage  = { 1200000, 1200000, 1200000, 1200000 },
-        .buck2_voltage  = { 1200000, 1200000 },
-};
-#endif
-
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
-        REGULATOR_SUPPLY("DBVDD", "5-001a"),
-        REGULATOR_SUPPLY("AVDD2", "5-001a"),
-        REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
-        REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
-        REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
-        .constraints = {
-                .always_on = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
-        .consumer_supplies      = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
-        .constraints = {
-                .always_on = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
-        .consumer_supplies      = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
-        .supply_name    = "VCC_1.8V_PDA",
-        .microvolts     = 1800000,
-        .gpio           = -EINVAL,
-        .init_data      = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
-        .supply_name    = "V_BAT",
-        .microvolts     = 3700000,
-        .gpio           = -EINVAL,
-        .init_data      = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
-        .name           = "reg-fixed-voltage",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &wm8994_fixed_voltage0_config,
-        },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &wm8994_fixed_voltage1_config,
-        },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
-        REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
-        REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-static struct regulator_init_data wm8994_ldo1_data = {
-        .constraints    = {
-                .name           = "AVDD1_3.0V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
-        .constraints    = {
-                .name           = "DCVDD_1.0V",
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-        /* configure gpio1 function: 0x0001(Logic level input/output) */
-        .gpio_defaults[0] = 0x0001,
-        /* configure gpio3/4/5/7 function for AIF2 voice */
-        .gpio_defaults[2] = 0x8100,
-        .gpio_defaults[3] = 0x8100,
-        .gpio_defaults[4] = 0x8100,
-        .gpio_defaults[6] = 0x0100,
-        /* configure gpio8/9/10/11 function for AIF3 BT */
-        .gpio_defaults[7] = 0x8100,
-        .gpio_defaults[8] = 0x0100,
-        .gpio_defaults[9] = 0x0100,
-        .gpio_defaults[10] = 0x0100,
-        .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data },       /* XM0FRNB_2 */
-        .ldo[1] = { 0, &wm8994_ldo2_data },
-};
-
-/* GPIO I2C PMIC */
-#define AP_I2C_GPIO_PMIC_BUS_4  4
-static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
-        .sda_pin        = S5PV210_GPJ4(0),      /* XMSMCSN */
-        .scl_pin        = S5PV210_GPJ4(3),      /* XMSMIRQN */
-};
-
-static struct platform_device aquila_i2c_gpio_pmic = {
-        .name           = "i2c-gpio",
-        .id             = AP_I2C_GPIO_PMIC_BUS_4,
-        .dev            = {
-                .platform_data = &aquila_i2c_gpio_pmic_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
-#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
-        {
-                /* 0xCC when SRAD = 0 */
-                I2C_BOARD_INFO("max8998", 0xCC >> 1),
-                .platform_data = &aquila_max8998_pdata,
-        },
-#endif
-};
-
-/* GPIO I2C AP 1.8V */
-#define AP_I2C_GPIO_BUS_5       5
-static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
-        .sda_pin        = S5PV210_MP05(3),      /* XM0ADDR_11 */
-        .scl_pin        = S5PV210_MP05(2),      /* XM0ADDR_10 */
-};
-
-static struct platform_device aquila_i2c_gpio5 = {
-        .name           = "i2c-gpio",
-        .id             = AP_I2C_GPIO_BUS_5,
-        .dev            = {
-                .platform_data  = &aquila_i2c_gpio5_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
-        {
-                /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
-                I2C_BOARD_INFO("wm8994", 0x1a),
-                .platform_data  = &wm8994_platform_data,
-        },
-};
-
-/* PMIC Power button */
-static struct gpio_keys_button aquila_gpio_keys_table[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = S5PV210_GPH2(6),
-                .desc           = "gpio-keys: KEY_POWER",
-                .type           = EV_KEY,
-                .active_low     = 1,
-                .wakeup         = 1,
-                .debounce_interval = 1,
-        },
-};
-
-static struct gpio_keys_platform_data aquila_gpio_keys_data = {
-        .buttons        = aquila_gpio_keys_table,
-        .nbuttons       = ARRAY_SIZE(aquila_gpio_keys_table),
-};
-
-static struct platform_device aquila_device_gpiokeys = {
-        .name = "gpio-keys",
-        .dev = {
-                .platform_data = &aquila_gpio_keys_data,
-        },
-};
-
-static void __init aquila_pmic_init(void)
-{
-        /* AP_PMIC_IRQ: EINT7 */
-        s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
-
-        /* nPower: EINT22 */
-        s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
-}
-
-/* MoviNAND */
-static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-/* Wireless LAN */
-static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-        /* ext_cd_{init,cleanup} callbacks will be added later */
-};
-
-/* External Flash */
-#define AQUILA_EXT_FLASH_EN     S5PV210_MP05(4)
-#define AQUILA_EXT_FLASH_CD     S5PV210_GPH3(4)
-static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = AQUILA_EXT_FLASH_CD,
-        .ext_cd_gpio_invert     = 1,
-};
-
-static void aquila_setup_sdhci(void)
-{
-        gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
-
-        s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
-        s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
-        s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
-};
-
-/* Audio device */
-static struct platform_device aquila_device_audio = {
-        .name = "smdk-audio",
-        .id = -1,
-};
-
-static struct platform_device *aquila_devices[] __initdata = {
-        &aquila_i2c_gpio_pmic,
-        &aquila_i2c_gpio5,
-        &aquila_device_gpiokeys,
-        &aquila_device_audio,
-        &s3c_device_fb,
-        &s5p_device_onenand,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc_md,
-        &s5pv210_device_iis0,
-        &wm8994_fixed_voltage0,
-        &wm8994_fixed_voltage1,
-};
-
-static void __init aquila_sound_init(void)
-{
-        unsigned int gpio;
-
-        /* CODEC_XTAL_EN
-         *
-         * The Aquila board have a oscillator which provide main clock
-         * to WM8994 codec. The oscillator provide 24MHz clock to WM8994
-         * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
-         * */
-        gpio = S5PV210_GPH3(2);         /* XEINT_26 */
-        gpio_request(gpio, "CODEC_XTAL_EN");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-        /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
-         * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
-         * because it needs 24MHz clock to operate WM8994 codec.
-         */
-        __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
-}
-
-static void __init aquila_map_io(void)
-{
-        s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void __init aquila_machine_init(void)
-{
-        /* PMIC */
-        aquila_pmic_init();
-        i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
-                        ARRAY_SIZE(i2c_gpio_pmic_devs));
-        /* SDHCI */
-        aquila_setup_sdhci();
-
-        s3c_fimc_setname(0, "s5p-fimc");
-        s3c_fimc_setname(1, "s5p-fimc");
-        s3c_fimc_setname(2, "s5p-fimc");
-
-        /* SOUND */
-        aquila_sound_init();
-        i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
-                        ARRAY_SIZE(i2c_gpio5_devs));
-
-        /* FB */
-        s3c_fb_set_platdata(&aquila_lcd_pdata);
-
-        platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
-}
-
-MACHINE_START(AQUILA, "Aquila")
-        /* Maintainers:
-           Marek Szyprowski <m.szyprowski@samsung.com>
-           Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pv210_init_irq,
-        .map_io         = aquila_map_io,
-        .init_machine   = aquila_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5pv210_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
deleted file mode 100644
index 096a8173a1d9..000000000000
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/mach-goni.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/fb.h>
-#include <linux/i2c.h>
-#include <linux/i2c-gpio.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/mfd/max8998.h>
-#include <linux/mfd/wm8994/pdata.h>
-#include <linux/regulator/fixed.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/lcd.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/interrupt.h>
-#include <linux/platform_data/s3c-hsotg.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/gpio-samsung.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/fb.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/keypad.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/samsung-time.h>
-#include <plat/mfc.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define GONI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define GONI_ULCON_DEFAULT      S3C2410_LCON_CS8
-
-#define GONI_UFCON_DEFAULT      S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = GONI_UCON_DEFAULT,
-                .ulcon          = GONI_ULCON_DEFAULT,
-                .ufcon          = GONI_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = GONI_UCON_DEFAULT,
-                .ulcon          = GONI_ULCON_DEFAULT,
-                .ufcon          = GONI_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = GONI_UCON_DEFAULT,
-                .ulcon          = GONI_ULCON_DEFAULT,
-                .ufcon          = GONI_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = GONI_UCON_DEFAULT,
-                .ulcon          = GONI_ULCON_DEFAULT,
-                .ufcon          = GONI_UFCON_DEFAULT |
-                        S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
-        },
-};
-
-/* Frame Buffer */
-static struct s3c_fb_pd_win goni_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 16,
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 2 * 800,
-};
-
-static struct fb_videomode goni_lcd_timing = {
-        .left_margin    = 16,
-        .right_margin   = 16,
-        .upper_margin   = 2,
-        .lower_margin   = 28,
-        .hsync_len      = 2,
-        .vsync_len      = 1,
-        .xres           = 480,
-        .yres           = 800,
-        .refresh        = 55,
-};
-
-static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
-        .win[0]         = &goni_fb_win0,
-        .vtiming        = &goni_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
-};
-
-static int lcd_power_on(struct lcd_device *ld, int enable)
-{
-        return 1;
-}
-
-static int reset_lcd(struct lcd_device *ld)
-{
-        static unsigned int first = 1;
-        int reset_gpio = -1;
-
-        reset_gpio = S5PV210_MP05(5);
-
-        if (first) {
-                gpio_request(reset_gpio, "MLCD_RST");
-                first = 0;
-        }
-
-        gpio_direction_output(reset_gpio, 1);
-        return 1;
-}
-
-static struct lcd_platform_data goni_lcd_platform_data = {
-        .reset                  = reset_lcd,
-        .power_on               = lcd_power_on,
-        .lcd_enabled            = 0,
-        .reset_delay            = 120,  /* 120ms */
-        .power_on_delay         = 25,   /* 25ms */
-        .power_off_delay        = 200,  /* 200ms */
-};
-
-#define LCD_BUS_NUM     3
-static struct spi_board_info spi_board_info[] __initdata = {
-        {
-                .modalias       = "s6e63m0",
-                .platform_data  = &goni_lcd_platform_data,
-                .max_speed_hz   = 1200000,
-                .bus_num        = LCD_BUS_NUM,
-                .chip_select    = 0,
-                .mode           = SPI_MODE_3,
-                .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
-        },
-};
-
-static struct spi_gpio_platform_data lcd_spi_gpio_data = {
-        .sck    = S5PV210_MP04(1), /* DISPLAY_CLK */
-        .mosi   = S5PV210_MP04(3), /* DISPLAY_SI */
-        .miso   = SPI_GPIO_NO_MISO,
-        .num_chipselect = 1,
-};
-
-static struct platform_device goni_spi_gpio = {
-        .name   = "spi_gpio",
-        .id     = LCD_BUS_NUM,
-        .dev    = {
-                .parent         = &s3c_device_fb.dev,
-                .platform_data  = &lcd_spi_gpio_data,
-        },
-};
-
-/* KEYPAD */
-static uint32_t keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 1, KEY_MENU),            /* Send */
-        KEY(0, 2, KEY_BACK),            /* End */
-        KEY(1, 1, KEY_CONFIG),          /* Half shot */
-        KEY(1, 2, KEY_VOLUMEUP),
-        KEY(2, 1, KEY_CAMERA),          /* Full shot */
-        KEY(2, 2, KEY_VOLUMEDOWN),
-};
-
-static struct matrix_keymap_data keymap_data __initdata = {
-        .keymap         = keymap,
-        .keymap_size    = ARRAY_SIZE(keymap),
-};
-
-static struct samsung_keypad_platdata keypad_data __initdata = {
-        .keymap_data    = &keymap_data,
-        .rows           = 3,
-        .cols           = 3,
-};
-
-/* Radio */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("si470x", 0x10),
-        },
-};
-
-static void __init goni_radio_init(void)
-{
-        int gpio;
-
-        gpio = S5PV210_GPJ2(4);                 /* XMSMDATA_4 */
-        gpio_request(gpio, "FM_INT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        i2c1_devs[0].irq = gpio_to_irq(gpio);
-
-        gpio = S5PV210_GPJ2(5);                 /* XMSMDATA_5 */
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
-}
-
-/* TSP */
-static struct mxt_platform_data qt602240_platform_data = {
-        .irqflags       = IRQF_TRIGGER_FALLING,
-};
-
-static struct s3c2410_platform_i2c i2c2_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 2,
-        .slave_addr     = 0x10,
-        .frequency      = 400 * 1000,
-        .sda_delay      = 100,
-};
-
-static struct i2c_board_info i2c2_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("qt602240_ts", 0x4a),
-                .platform_data = &qt602240_platform_data,
-        },
-};
-
-static void __init goni_tsp_init(void)
-{
-        int gpio;
-
-        gpio = S5PV210_GPJ1(3);         /* XMSMADDR_11 */
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_export(gpio, 0);
-
-        gpio = S5PV210_GPJ0(5);         /* XMSMADDR_5 */
-        gpio_request(gpio, "TSP_INT");
-
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-        i2c2_devs[0].irq = gpio_to_irq(gpio);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat goni_hsotg_pdata;
-
-/* MAX8998 regulators */
-#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
-
-static struct regulator_consumer_supply goni_ldo3_consumers[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
-};
-
-static struct regulator_consumer_supply goni_ldo5_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
-};
-
-static struct regulator_consumer_supply goni_ldo8_consumers[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
-};
-
-static struct regulator_consumer_supply goni_ldo11_consumers[] = {
-        REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
-};
-
-static struct regulator_consumer_supply goni_ldo13_consumers[] = {
-        REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
-};
-
-static struct regulator_consumer_supply goni_ldo14_consumers[] = {
-        REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
-};
-
-static struct regulator_init_data goni_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled = 1,
-                },
-        },
-};
-
-static struct regulator_init_data goni_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB+MIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
-        .consumer_supplies = goni_ldo3_consumers,
-};
-
-static struct regulator_init_data goni_ldo4_data = {
-        .constraints    = {
-                .name           = "VDAC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo5_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
-        .consumer_supplies = goni_ldo5_consumers,
-};
-
-static struct regulator_init_data goni_ldo6_data = {
-        .constraints    = {
-                .name           = "VCC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo7_data = {
-        .constraints    = {
-                .name           = "VLCD_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
-        .consumer_supplies = goni_ldo8_consumers,
-};
-
-static struct regulator_init_data goni_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC+VCAM_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo11_data = {
-        .constraints    = {
-                .name           = "CAM_IO_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo11_consumers),
-        .consumer_supplies      = goni_ldo11_consumers,
-};
-
-static struct regulator_init_data goni_ldo12_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo13_data = {
-        .constraints    = {
-                .name           = "CAM_A_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo13_consumers),
-        .consumer_supplies      = goni_ldo13_consumers,
-};
-
-static struct regulator_init_data goni_ldo14_data = {
-        .constraints    = {
-                .name           = "CAM_CIF_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo14_consumers),
-        .consumer_supplies      = goni_ldo14_consumers,
-};
-
-static struct regulator_init_data goni_ldo15_data = {
-        .constraints    = {
-                .name           = "CAM_AF_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo16_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data goni_ldo17_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_LCD",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-/* BUCK */
-static struct regulator_consumer_supply buck1_consumer =
-        REGULATOR_SUPPLY("vddarm", NULL);
-
-static struct regulator_consumer_supply buck2_consumer =
-        REGULATOR_SUPPLY("vddint", NULL);
-
-static struct regulator_consumer_supply buck3_consumer =
-        REGULATOR_SUPPLY("vdet", "s5p-sdo");
-
-
-static struct regulator_init_data goni_buck1_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &buck1_consumer,
-};
-
-static struct regulator_init_data goni_buck2_data = {
-        .constraints    = {
-                .name           = "VINT_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &buck2_consumer,
-};
-
-static struct regulator_init_data goni_buck3_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .enabled = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &buck3_consumer,
-};
-
-static struct regulator_init_data goni_buck4_data = {
-        .constraints    = {
-                .name           = "CAM_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-        },
-};
-
-static struct max8998_regulator_data goni_regulators[] = {
-        { MAX8998_LDO2,  &goni_ldo2_data },
-        { MAX8998_LDO3,  &goni_ldo3_data },
-        { MAX8998_LDO4,  &goni_ldo4_data },
-        { MAX8998_LDO5,  &goni_ldo5_data },
-        { MAX8998_LDO6,  &goni_ldo6_data },
-        { MAX8998_LDO7,  &goni_ldo7_data },
-        { MAX8998_LDO8,  &goni_ldo8_data },
-        { MAX8998_LDO9,  &goni_ldo9_data },
-        { MAX8998_LDO10, &goni_ldo10_data },
-        { MAX8998_LDO11, &goni_ldo11_data },
-        { MAX8998_LDO12, &goni_ldo12_data },
-        { MAX8998_LDO13, &goni_ldo13_data },
-        { MAX8998_LDO14, &goni_ldo14_data },
-        { MAX8998_LDO15, &goni_ldo15_data },
-        { MAX8998_LDO16, &goni_ldo16_data },
-        { MAX8998_LDO17, &goni_ldo17_data },
-        { MAX8998_BUCK1, &goni_buck1_data },
-        { MAX8998_BUCK2, &goni_buck2_data },
-        { MAX8998_BUCK3, &goni_buck3_data },
-        { MAX8998_BUCK4, &goni_buck4_data },
-};
-
-static struct max8998_platform_data goni_max8998_pdata = {
-        .num_regulators = ARRAY_SIZE(goni_regulators),
-        .regulators     = goni_regulators,
-        .buck1_set1     = S5PV210_GPH0(3),
-        .buck1_set2     = S5PV210_GPH0(4),
-        .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_voltage  = { 1200000, 1200000, 1200000, 1200000 },
-        .buck2_voltage  = { 1200000, 1200000 },
-};
-#endif
-
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
-        REGULATOR_SUPPLY("DBVDD", "5-001a"),
-        REGULATOR_SUPPLY("AVDD2", "5-001a"),
-        REGULATOR_SUPPLY("CPVDD", "5-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
-        REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
-        REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
-        .constraints = {
-                .always_on = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
-        .consumer_supplies      = wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
-        .constraints = {
-                .always_on = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
-        .consumer_supplies      = wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
-        .supply_name    = "VCC_1.8V_PDA",
-        .microvolts     = 1800000,
-        .gpio           = -EINVAL,
-        .init_data      = &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
-        .supply_name    = "V_BAT",
-        .microvolts     = 3700000,
-        .gpio           = -EINVAL,
-        .init_data      = &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
-        .name           = "reg-fixed-voltage",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &wm8994_fixed_voltage0_config,
-        },
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &wm8994_fixed_voltage1_config,
-        },
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
-        REGULATOR_SUPPLY("AVDD1", "5-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
-        REGULATOR_SUPPLY("DCVDD", "5-001a");
-
-static struct regulator_init_data wm8994_ldo1_data = {
-        .constraints    = {
-                .name           = "AVDD1_3.0V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
-        .constraints    = {
-                .name           = "DCVDD_1.0V",
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-        /* configure gpio1 function: 0x0001(Logic level input/output) */
-        .gpio_defaults[0] = 0x0001,
-        /* configure gpio3/4/5/7 function for AIF2 voice */
-        .gpio_defaults[2] = 0x8100,
-        .gpio_defaults[3] = 0x8100,
-        .gpio_defaults[4] = 0x8100,
-        .gpio_defaults[6] = 0x0100,
-        /* configure gpio8/9/10/11 function for AIF3 BT */
-        .gpio_defaults[7] = 0x8100,
-        .gpio_defaults[8] = 0x0100,
-        .gpio_defaults[9] = 0x0100,
-        .gpio_defaults[10] = 0x0100,
-        .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data },       /* XM0FRNB_2 */
-        .ldo[1] = { 0, &wm8994_ldo2_data },
-};
-
-/* GPIO I2C PMIC */
-#define AP_I2C_GPIO_PMIC_BUS_4  4
-static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
-        .sda_pin        = S5PV210_GPJ4(0),      /* XMSMCSN */
-        .scl_pin        = S5PV210_GPJ4(3),      /* XMSMIRQN */
-};
-
-static struct platform_device goni_i2c_gpio_pmic = {
-        .name           = "i2c-gpio",
-        .id             = AP_I2C_GPIO_PMIC_BUS_4,
-        .dev            = {
-                .platform_data  = &goni_i2c_gpio_pmic_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
-#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
-        {
-                /* 0xCC when SRAD = 0 */
-                I2C_BOARD_INFO("max8998", 0xCC >> 1),
-                .platform_data = &goni_max8998_pdata,
-        },
-#endif
-};
-
-/* GPIO I2C AP 1.8V */
-#define AP_I2C_GPIO_BUS_5       5
-static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
-        .sda_pin        = S5PV210_MP05(3),      /* XM0ADDR_11 */
-        .scl_pin        = S5PV210_MP05(2),      /* XM0ADDR_10 */
-};
-
-static struct platform_device goni_i2c_gpio5 = {
-        .name           = "i2c-gpio",
-        .id             = AP_I2C_GPIO_BUS_5,
-        .dev            = {
-                .platform_data  = &goni_i2c_gpio5_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
-        {
-                /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
-                I2C_BOARD_INFO("wm8994", 0x1a),
-                .platform_data  = &wm8994_platform_data,
-        },
-};
-
-/* PMIC Power button */
-static struct gpio_keys_button goni_gpio_keys_table[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = S5PV210_GPH2(6),
-                .desc           = "gpio-keys: KEY_POWER",
-                .type           = EV_KEY,
-                .active_low     = 1,
-                .wakeup         = 1,
-                .debounce_interval = 1,
-        },
-};
-
-static struct gpio_keys_platform_data goni_gpio_keys_data = {
-        .buttons        = goni_gpio_keys_table,
-        .nbuttons       = ARRAY_SIZE(goni_gpio_keys_table),
-};
-
-static struct platform_device goni_device_gpiokeys = {
-        .name = "gpio-keys",
-        .dev = {
-                .platform_data = &goni_gpio_keys_data,
-        },
-};
-
-static void __init goni_pmic_init(void)
-{
-        /* AP_PMIC_IRQ: EINT7 */
-        s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
-
-        /* nPower: EINT22 */
-        s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
-}
-
-/* MoviNAND */
-static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-/* Wireless LAN */
-static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-        /* ext_cd_{init,cleanup} callbacks will be added later */
-};
-
-/* External Flash */
-#define GONI_EXT_FLASH_EN       S5PV210_MP05(4)
-#define GONI_EXT_FLASH_CD       S5PV210_GPH3(4)
-static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = GONI_EXT_FLASH_CD,
-        .ext_cd_gpio_invert     = 1,
-};
-
-static struct regulator_consumer_supply mmc2_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
-};
-
-static struct regulator_init_data mmc2_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "V_TF_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(mmc2_supplies),
-        .consumer_supplies      = mmc2_supplies,
-};
-
-static struct fixed_voltage_config mmc2_fixed_voltage_config = {
-        .supply_name            = "EXT_FLASH_EN",
-        .microvolts             = 2800000,
-        .gpio                   = GONI_EXT_FLASH_EN,
-        .enable_high            = true,
-        .init_data              = &mmc2_fixed_voltage_init_data,
-};
-
-static struct platform_device mmc2_fixed_voltage = {
-        .name           = "reg-fixed-voltage",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &mmc2_fixed_voltage_config,
-        },
-};
-
-static void goni_setup_sdhci(void)
-{
-        s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
-        s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
-        s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
-};
-
-/* Audio device */
-static struct platform_device goni_device_audio = {
-        .name = "smdk-audio",
-        .id = -1,
-};
-
-static struct platform_device *goni_devices[] __initdata = {
-        &s3c_device_fb,
-        &s5p_device_onenand,
-        &goni_spi_gpio,
-        &goni_i2c_gpio_pmic,
-        &goni_i2c_gpio5,
-        &goni_device_audio,
-        &mmc2_fixed_voltage,
-        &goni_device_gpiokeys,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_mixer,
-        &s5p_device_sdo,
-        &s3c_device_i2c0,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s5pv210_device_iis0,
-        &s3c_device_usb_hsotg,
-        &samsung_device_keypad,
-        &s3c_device_i2c1,
-        &s3c_device_i2c2,
-        &wm8994_fixed_voltage0,
-        &wm8994_fixed_voltage1,
-};
-
-static void __init goni_sound_init(void)
-{
-        /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
-         * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
-         * because it needs 24MHz clock to operate WM8994 codec.
-         */
-        __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
-}
-
-static void __init goni_map_io(void)
-{
-        s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
-        s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void __init goni_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init goni_machine_init(void)
-{
-        /* Radio: call before I2C 1 registeration */
-        goni_radio_init();
-
-        /* I2C0 */
-        s3c_i2c0_set_platdata(NULL);
-
-        /* I2C1 */
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-
-        /* TSP: call before I2C 2 registeration */
-        goni_tsp_init();
-
-        /* I2C2 */
-        s3c_i2c2_set_platdata(&i2c2_data);
-        i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
-
-        /* PMIC */
-        goni_pmic_init();
-        i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
-                        ARRAY_SIZE(i2c_gpio_pmic_devs));
-        /* SDHCI */
-        goni_setup_sdhci();
-
-        /* SOUND */
-        goni_sound_init();
-        i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
-                        ARRAY_SIZE(i2c_gpio5_devs));
-
-        /* FB */
-        s3c_fb_set_platdata(&goni_lcd_pdata);
-
-        s3c_hsotg_set_platdata(&goni_hsotg_pdata);
-
-        /* SPI */
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-
-        /* KEYPAD */
-        samsung_keypad_set_platdata(&keypad_data);
-
-        platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
-}
-
-MACHINE_START(GONI, "GONI")
-        /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pv210_init_irq,
-        .map_io         = goni_map_io,
-        .init_machine   = goni_machine_init,
-        .init_time      = samsung_timer_init,
-        .reserve        = &goni_reserve,
-        .restart        = s5pv210_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
deleted file mode 100644
index 448e1d2eeed6..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/mach-smdkc110.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/i2c.h>
-#include <linux/device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <linux/platform_data/ata-samsung_cf.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
-#include <plat/mfc.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKC110_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKC110_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKC110_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKC110_UCON_DEFAULT,
-                .ulcon          = SMDKC110_ULCON_DEFAULT,
-                .ufcon          = SMDKC110_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKC110_UCON_DEFAULT,
-                .ulcon          = SMDKC110_ULCON_DEFAULT,
-                .ufcon          = SMDKC110_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKC110_UCON_DEFAULT,
-                .ulcon          = SMDKC110_ULCON_DEFAULT,
-                .ufcon          = SMDKC110_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKC110_UCON_DEFAULT,
-                .ulcon          = SMDKC110_ULCON_DEFAULT,
-                .ufcon          = SMDKC110_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
-        .setup_gpio     = s5pv210_ide_setup_gpio,
-};
-
-static struct platform_device *smdkc110_devices[] __initdata = {
-        &s5pv210_device_iis0,
-        &s5pv210_device_ac97,
-        &s5pv210_device_spdif,
-        &s3c_device_cfcon,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c2,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc_md,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-};
-
-static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
-        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
-        { I2C_BOARD_INFO("wm8580", 0x1b), },
-};
-
-static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
-        /* To Be Updated */
-};
-
-static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = {
-        /* To Be Updated */
-};
-
-static void __init smdkc110_map_io(void)
-{
-        s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void __init smdkc110_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdkc110_machine_init(void)
-{
-        s3c_pm_init();
-
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
-        s3c_i2c2_set_platdata(NULL);
-        i2c_register_board_info(0, smdkc110_i2c_devs0,
-                        ARRAY_SIZE(smdkc110_i2c_devs0));
-        i2c_register_board_info(1, smdkc110_i2c_devs1,
-                        ARRAY_SIZE(smdkc110_i2c_devs1));
-        i2c_register_board_info(2, smdkc110_i2c_devs2,
-                        ARRAY_SIZE(smdkc110_i2c_devs2));
-
-        s3c_ide_set_platdata(&smdkc110_ide_pdata);
-
-        platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
-}
-
-MACHINE_START(SMDKC110, "SMDKC110")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pv210_init_irq,
-        .map_io         = smdkc110_map_io,
-        .init_machine   = smdkc110_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5pv210_restart,
-        .reserve        = &smdkc110_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
deleted file mode 100644
index a146089c9ee6..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/mach-smdkv210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/device.h>
-#include <linux/dm9000.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/s3c-hsotg.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/gpio-samsung.h>
-
-#include <plat/regs-srom.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/adc.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <linux/platform_data/ata-samsung_cf.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/keypad.h>
-#include <plat/pm.h>
-#include <plat/fb.h>
-#include <plat/samsung-time.h>
-#include <plat/backlight.h>
-#include <plat/mfc.h>
-#include <plat/clock.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKV210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKV210_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKV210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKV210_UCON_DEFAULT,
-                .ulcon          = SMDKV210_ULCON_DEFAULT,
-                .ufcon          = SMDKV210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKV210_UCON_DEFAULT,
-                .ulcon          = SMDKV210_ULCON_DEFAULT,
-                .ufcon          = SMDKV210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKV210_UCON_DEFAULT,
-                .ulcon          = SMDKV210_ULCON_DEFAULT,
-                .ufcon          = SMDKV210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKV210_UCON_DEFAULT,
-                .ulcon          = SMDKV210_ULCON_DEFAULT,
-                .ufcon          = SMDKV210_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
-        .setup_gpio     = s5pv210_ide_setup_gpio,
-};
-
-static uint32_t smdkv210_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-
-static struct matrix_keymap_data smdkv210_keymap_data __initdata = {
-        .keymap         = smdkv210_keymap,
-        .keymap_size    = ARRAY_SIZE(smdkv210_keymap),
-};
-
-static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
-        .keymap_data    = &smdkv210_keymap_data,
-        .rows           = 8,
-        .cols           = 8,
-};
-
-static struct resource smdkv210_dm9000_resources[] = {
-        [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1),
-        [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1),
-        [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \
-                                | IORESOURCE_IRQ_HIGHLEVEL),
-};
-
-static struct dm9000_plat_data smdkv210_dm9000_platdata = {
-        .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
-        .dev_addr       = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
-};
-
-static struct platform_device smdkv210_dm9000 = {
-        .name           = "dm9000",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkv210_dm9000_resources),
-        .resource       = smdkv210_dm9000_resources,
-        .dev            = {
-                .platform_data  = &smdkv210_dm9000_platdata,
-        },
-};
-
-static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
-                                        unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(S5PV210_GPD0(3));
-#endif
-
-                /* fire nRESET on power up */
-                gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
-
-                gpio_set_value(S5PV210_GPH0(6), 0);
-                mdelay(10);
-
-                gpio_set_value(S5PV210_GPH0(6), 1);
-                mdelay(10);
-
-                gpio_free(S5PV210_GPH0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(S5PV210_GPD0(3));
-#endif
-        }
-}
-
-static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
-        .set_power      = smdkv210_lte480wv_set_power,
-};
-
-static struct platform_device smdkv210_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s3c_device_fb.dev,
-        .dev.platform_data      = &smdkv210_lcd_lte480wv_data,
-};
-
-static struct s3c_fb_pd_win smdkv210_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdkv210_lcd_timing = {
-        .left_margin    = 13,
-        .right_margin   = 8,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
-        .win[0]         = &smdkv210_fb_win0,
-        .vtiming        = &smdkv210_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
-};
-
-/* USB OTG */
-static struct s3c_hsotg_plat smdkv210_hsotg_pdata;
-
-static struct platform_device *smdkv210_devices[] __initdata = {
-        &s3c_device_adc,
-        &s3c_device_cfcon,
-        &s3c_device_fb,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c2,
-        &samsung_device_pwm,
-        &s3c_device_rtc,
-        &s3c_device_ts,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc_md,
-        &s5p_device_jpeg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5pv210_device_ac97,
-        &s5pv210_device_iis0,
-        &s5pv210_device_spdif,
-        &samsung_asoc_idma,
-        &samsung_device_keypad,
-        &smdkv210_dm9000,
-        &smdkv210_lcd_lte480wv,
-};
-
-static void __init smdkv210_dm9000_init(void)
-{
-        unsigned int tmp;
-
-        gpio_request(S5PV210_MP01(5), "nCS5");
-        s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
-        gpio_free(S5PV210_MP01(5));
-
-        tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
-        __raw_writel(tmp, S5P_SROM_BC5);
-
-        tmp = __raw_readl(S5P_SROM_BW);
-        tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
-        tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
-        __raw_writel(tmp, S5P_SROM_BW);
-}
-
-static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
-        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
-        { I2C_BOARD_INFO("wm8580", 0x1b), },
-};
-
-static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
-        /* To Be Updated */
-};
-
-static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
-        /* To Be Updated */
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
-        .no = S5PV210_GPD0(3),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkv210_bl_data = {
-        .pwm_id = 3,
-        .pwm_period_ns = 1000,
-        .enable_gpio = -1,
-};
-
-static void __init smdkv210_map_io(void)
-{
-        s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
-        s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
-}
-
-static void __init smdkv210_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdkv210_machine_init(void)
-{
-        s3c_pm_init();
-
-        smdkv210_dm9000_init();
-
-        samsung_keypad_set_platdata(&smdkv210_keypad_data);
-        s3c24xx_ts_set_platdata(NULL);
-
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
-        s3c_i2c2_set_platdata(NULL);
-        i2c_register_board_info(0, smdkv210_i2c_devs0,
-                        ARRAY_SIZE(smdkv210_i2c_devs0));
-        i2c_register_board_info(1, smdkv210_i2c_devs1,
-                        ARRAY_SIZE(smdkv210_i2c_devs1));
-        i2c_register_board_info(2, smdkv210_i2c_devs2,
-                        ARRAY_SIZE(smdkv210_i2c_devs2));
-
-        s3c_ide_set_platdata(&smdkv210_ide_pdata);
-
-        s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
-
-        s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
-
-        platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
-
-        samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
-}
-
-MACHINE_START(SMDKV210, "SMDKV210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pv210_init_irq,
-        .map_io         = smdkv210_map_io,
-        .init_machine   = smdkv210_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5pv210_restart,
-        .reserve        = &smdkv210_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
deleted file mode 100644
index 157805529f26..000000000000
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
- *
- * Copyright (c) 2010 aESOP Community
- *              http://www.aesop.or.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/samsung-time.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define TORBRECK_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define TORBRECK_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define TORBRECK_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = TORBRECK_UCON_DEFAULT,
-                .ulcon          = TORBRECK_ULCON_DEFAULT,
-                .ufcon          = TORBRECK_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = TORBRECK_UCON_DEFAULT,
-                .ulcon          = TORBRECK_ULCON_DEFAULT,
-                .ufcon          = TORBRECK_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = TORBRECK_UCON_DEFAULT,
-                .ulcon          = TORBRECK_ULCON_DEFAULT,
-                .ufcon          = TORBRECK_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = TORBRECK_UCON_DEFAULT,
-                .ulcon          = TORBRECK_ULCON_DEFAULT,
-                .ufcon          = TORBRECK_UFCON_DEFAULT,
-        },
-};
-
-static struct platform_device *torbreck_devices[] __initdata = {
-        &s5pv210_device_iis0,
-        &s3c_device_cfcon,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c2,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-};
-
-static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
-        /* To Be Updated */
-};
-
-static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
-        /* To Be Updated */
-};
-
-static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
-        /* To Be Updated */
-};
-
-static void __init torbreck_map_io(void)
-{
-        s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
-}
-
-static void __init torbreck_machine_init(void)
-{
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
-        s3c_i2c2_set_platdata(NULL);
-        i2c_register_board_info(0, torbreck_i2c_devs0,
-                        ARRAY_SIZE(torbreck_i2c_devs0));
-        i2c_register_board_info(1, torbreck_i2c_devs1,
-                        ARRAY_SIZE(torbreck_i2c_devs1));
-        i2c_register_board_info(2, torbreck_i2c_devs2,
-                        ARRAY_SIZE(torbreck_i2c_devs2));
-
-        platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
-}
-
-MACHINE_START(TORBRECK, "TORBRECK")
-        /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
-        .atag_offset    = 0x100,
-        .init_irq       = s5pv210_init_irq,
-        .map_io         = torbreck_map_io,
-        .init_machine   = torbreck_machine_init,
-        .init_time      = samsung_timer_init,
-        .restart        = s5pv210_restart,
-MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 3cf3f9c8ddd1..123163dd2ab0 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv210/pm.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * S5PV210 - Power Management support
@@ -19,65 +19,28 @@
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include <asm/cacheflush.h>
+#include <asm/suspend.h>
+
+#include <plat/pm-common.h>
 
-#include <mach/regs-irq.h>
 #include <mach/regs-clock.h>
 
-static struct sleep_save s5pv210_core_save[] = {
-        /* Clock source */
-        SAVE_ITEM(S5P_CLK_SRC0),
-        SAVE_ITEM(S5P_CLK_SRC1),
-        SAVE_ITEM(S5P_CLK_SRC2),
-        SAVE_ITEM(S5P_CLK_SRC3),
-        SAVE_ITEM(S5P_CLK_SRC4),
-        SAVE_ITEM(S5P_CLK_SRC5),
-        SAVE_ITEM(S5P_CLK_SRC6),
-
-        /* Clock source Mask */
-        SAVE_ITEM(S5P_CLK_SRC_MASK0),
-        SAVE_ITEM(S5P_CLK_SRC_MASK1),
-
-        /* Clock Divider */
-        SAVE_ITEM(S5P_CLK_DIV0),
-        SAVE_ITEM(S5P_CLK_DIV1),
-        SAVE_ITEM(S5P_CLK_DIV2),
-        SAVE_ITEM(S5P_CLK_DIV3),
-        SAVE_ITEM(S5P_CLK_DIV4),
-        SAVE_ITEM(S5P_CLK_DIV5),
-        SAVE_ITEM(S5P_CLK_DIV6),
-        SAVE_ITEM(S5P_CLK_DIV7),
-
-        /* Clock Main Gate */
-        SAVE_ITEM(S5P_CLKGATE_MAIN0),
-        SAVE_ITEM(S5P_CLKGATE_MAIN1),
-        SAVE_ITEM(S5P_CLKGATE_MAIN2),
-
-        /* Clock source Peri Gate */
-        SAVE_ITEM(S5P_CLKGATE_PERI0),
-        SAVE_ITEM(S5P_CLKGATE_PERI1),
-
-        /* Clock source SCLK Gate */
-        SAVE_ITEM(S5P_CLKGATE_SCLK0),
-        SAVE_ITEM(S5P_CLKGATE_SCLK1),
-
-        /* Clock IP Clock gate */
-        SAVE_ITEM(S5P_CLKGATE_IP0),
-        SAVE_ITEM(S5P_CLKGATE_IP1),
-        SAVE_ITEM(S5P_CLKGATE_IP2),
-        SAVE_ITEM(S5P_CLKGATE_IP3),
-        SAVE_ITEM(S5P_CLKGATE_IP4),
-
-        /* Clock Blcok and Bus gate */
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKGATE_BUS0),
+#include "common.h"
 
+static struct sleep_save s5pv210_core_save[] = {
         /* Clock ETC */
-        SAVE_ITEM(S5P_CLK_OUT),
         SAVE_ITEM(S5P_MDNIE_SEL),
 };
 
+/*
+ * VIC wake-up support (TODO)
+ */
+static u32 s5pv210_irqwake_intmask = 0xffffffff;
+
+/*
+ * Suspend helpers.
+ */
 static int s5pv210_cpu_suspend(unsigned long arg)
 {
         unsigned long tmp;
@@ -102,8 +65,12 @@ static void s5pv210_pm_prepare(void)
 {
         unsigned int tmp;
 
+        /* Set wake-up mask registers */
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
+
         /* ensure at least INFORM0 has the resume address */
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+        __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
 
         tmp = __raw_readl(S5P_SLEEP_CFG);
         tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
@@ -123,26 +90,70 @@ static void s5pv210_pm_prepare(void)
         s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }
 
-static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
+/*
+ * Suspend operations.
+ */
+static int s5pv210_suspend_enter(suspend_state_t state)
 {
-        pm_cpu_prep = s5pv210_pm_prepare;
-        pm_cpu_sleep = s5pv210_cpu_suspend;
+        int ret;
+
+        s3c_pm_debug_init();
+
+        S3C_PMDBG("%s: suspending the system...\n", __func__);
+
+        S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
+                        s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
+
+        if (s5pv210_irqwake_intmask == -1U
+            && exynos_get_eint_wake_mask() == -1U) {
+                pr_err("%s: No wake-up sources!\n", __func__);
+                pr_err("%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+
+        s3c_pm_save_uarts();
+        s5pv210_pm_prepare();
+        flush_cache_all();
+        s3c_pm_check_store();
+
+        ret = cpu_suspend(0, s5pv210_cpu_suspend);
+        if (ret)
+                return ret;
+
+        s3c_pm_restore_uarts();
+
+        S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
+                        __raw_readl(S5P_WAKEUP_STAT));
+
+        s3c_pm_check_restore();
+
+        S3C_PMDBG("%s: resuming the system...\n", __func__);
 
         return 0;
 }
 
-static struct subsys_interface s5pv210_pm_interface = {
-        .name           = "s5pv210_pm",
-        .subsys         = &s5pv210_subsys,
-        .add_dev        = s5pv210_pm_add,
-};
+static int s5pv210_suspend_prepare(void)
+{
+        s3c_pm_check_prepare();
 
-static __init int s5pv210_pm_drvinit(void)
+        return 0;
+}
+
+static void s5pv210_suspend_finish(void)
 {
-        return subsys_interface_register(&s5pv210_pm_interface);
+        s3c_pm_check_cleanup();
 }
-arch_initcall(s5pv210_pm_drvinit);
 
+static const struct platform_suspend_ops s5pv210_suspend_ops = {
+        .enter          = s5pv210_suspend_enter,
+        .prepare        = s5pv210_suspend_prepare,
+        .finish         = s5pv210_suspend_finish,
+        .valid          = suspend_valid_only_mem,
+};
+
+/*
+ * Syscore operations used to delay restore of certain registers.
+ */
 static void s5pv210_pm_resume(void)
 {
         u32 tmp;
@@ -159,9 +170,11 @@ static struct syscore_ops s5pv210_pm_syscore_ops = {
         .resume         = s5pv210_pm_resume,
 };
 
-static __init int s5pv210_pm_syscore_init(void)
+/*
+ * Initialization entry point.
+ */
+void __init s5pv210_pm_init(void)
 {
         register_syscore_ops(&s5pv210_pm_syscore_ops);
-        return 0;
+        suspend_set_ops(&s5pv210_suspend_ops);
 }
-arch_initcall(s5pv210_pm_syscore_init);
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
new file mode 100644
index 000000000000..53feff33d129
--- /dev/null
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -0,0 +1,77 @@
+/*
+ * Samsung's S5PC110/S5PV210 flattened device tree enabled machine.
+ *
+ * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
+ * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/system_misc.h>
+
+#include <plat/map-base.h>
+#include <mach/regs-clock.h>
+
+#include "common.h"
+
+static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
+                                        int depth, void *data)
+{
+        struct map_desc iodesc;
+        const __be32 *reg;
+        int len;
+
+        if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock"))
+                return 0;
+
+        reg = of_get_flat_dt_prop(node, "reg", &len);
+        if (reg == NULL || len != (sizeof(unsigned long) * 2))
+                return 0;
+
+        iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
+        iodesc.length = be32_to_cpu(reg[1]) - 1;
+        iodesc.virtual = (unsigned long)S3C_VA_SYS;
+        iodesc.type = MT_DEVICE;
+        iotable_init(&iodesc, 1);
+
+        return 1;
+}
+
+static void __init s5pv210_dt_map_io(void)
+{
+        debug_ll_io_init();
+
+        of_scan_flat_dt(s5pv210_fdt_map_sys, NULL);
+}
+
+static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd)
+{
+        __raw_writel(0x1, S5P_SWRESET);
+}
+
+static void __init s5pv210_dt_init_late(void)
+{
+        platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0);
+        s5pv210_pm_init();
+}
+
+static char const *s5pv210_dt_compat[] __initconst = {
+        "samsung,s5pc110",
+        "samsung,s5pv210",
+        NULL
+};
+
+DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board")
+        .dt_compat = s5pv210_dt_compat,
+        .map_io = s5pv210_dt_map_io,
+        .restart = s5pv210_dt_restart,
+        .init_late = s5pv210_dt_init_late,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
deleted file mode 100644
index 815e329f70c4..000000000000
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Base s5pv210 setup information for 24bpp LCD framebuffer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/fb.h>
-
-#include <mach/map.h>
-#include <plat/fb.h>
-#include <mach/regs-clock.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
-{
-        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
-
-        for (; nr > 0; nr--, base++)
-                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
-}
-
-
-void s5pv210_fb_gpio_setup_24bpp(void)
-{
-        s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
-        s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
-        s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
-        s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
-
-        /* Set DISPLAY_CONTROL register for Display path selection.
-         *
-         * ouput   |   RGB   |   I80   |   ITU
-         * -----------------------------------
-         *  00     |   MIE   |  FIMD   |  FIMD
-         *  01     | MDNIE   | MDNIE   |  FIMD
-         *  10     |  FIMD   |  FIMD   |  FIMD
-         *  11     |  FIMD   |  FIMD   |  FIMD
-         */
-        writel(0x2, S5P_MDNIE_SEL);
-}
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
deleted file mode 100644
index 36945ec437f8..000000000000
--- a/arch/arm/mach-s5pv210/setup-fimc.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * S5PV210 camera interface GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <plat/gpio-cfg.h>
-#include <plat/camport.h>
-#include <mach/gpio-samsung.h>
-
-int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
-{
-        u32 gpio8, gpio5;
-        int ret;
-
-        switch (id) {
-        case S5P_CAMPORT_A:
-                gpio8 = S5PV210_GPE0(0);
-                gpio5 = S5PV210_GPE1(0);
-                break;
-
-        case S5P_CAMPORT_B:
-                gpio8 = S5PV210_GPJ0(0);
-                gpio5 = S5PV210_GPJ1(0);
-                break;
-
-        default:
-                WARN(1, "Wrong camport id: %d\n", id);
-                return -EINVAL;
-        }
-
-        ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
-                                    S3C_GPIO_PULL_UP);
-        if (ret)
-                return ret;
-
-        return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
-                                     S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
deleted file mode 100644
index b0f2b69ac743..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
deleted file mode 100644
index aac1da7b9071..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-i2c1.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C1 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c1.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
deleted file mode 100644
index eff4503b903f..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-i2c2.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C2 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-void s3c_i2c2_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
deleted file mode 100644
index 5b6042d97892..000000000000
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-ide.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV210 setup information for IDE
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
-{
-        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
-
-        for (; nr > 0; nr--, base++)
-                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
-}
-
-void s5pv210_ide_setup_gpio(void)
-{
-        /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
-        s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
-
-        /* CF_Data[0 - 7] */
-        s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
-
-        /* CF_Data[8 - 15] */
-        s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
-
-        /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
-        s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
-}
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
deleted file mode 100644
index faf6178f3a1b..000000000000
--- a/arch/arm/mach-s5pv210/setup-keypad.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * linux/arch/arm/mach-s5pv210/setup-keypad.c
- *
- * Copyright (C) 2010 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-        /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
-
-        /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
deleted file mode 100644
index 0dd055b47579..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-#include <mach/gpio-samsung.h>
-
-void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG0/GPG1 pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
-
-        switch (width) {
-        case 8:
-                /* GPG1[3:6] special-function 3 */
-                s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
-        case 4:
-                /* GPG0[3:6] special-function 2 */
-                s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
-        }
-}
-
-void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG1[0:1] pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
-
-        /* Data pin GPG1[3:6] to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
-        }
-}
-
-void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG2[0:1] pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
-
-        switch (width) {
-        case 8:
-                /* Data pin GPG3[3:6] to special-function 3 */
-                s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
-        case 4:
-                /* Data pin GPG2[3:6] to special-function 2 */
-                s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
-        }
-}
-
-void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-
-        /* Set all the necessary GPG3[0:1] pins to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
-
-        /* Data pin GPG3[3:6] to special-function 2 */
-        s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
-        }
-}
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
deleted file mode 100644
index e1faf8ea4502..000000000000
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
-                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
-                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
deleted file mode 100644
index b2ee5333f89c..000000000000
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundationr
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
-#define S5PV210_USB_PHY0_EN     (1 << 0)
-#define S5PV210_USB_PHY1_EN     (1 << 1)
-
-static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
-{
-        struct clk *xusbxti;
-        u32 phyclk;
-
-        writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
-                        S5PV210_USB_PHY_CON);
-
-        /* set clock frequency for PLL */
-        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-        xusbxti = clk_get(&pdev->dev, "xusbxti");
-        if (xusbxti && !IS_ERR(xusbxti)) {
-                switch (clk_get_rate(xusbxti)) {
-                case 12 * MHZ:
-                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
-                        break;
-                case 24 * MHZ:
-                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
-                        break;
-                default:
-                case 48 * MHZ:
-                        /* default reference clock */
-                        break;
-                }
-                clk_put(xusbxti);
-        }
-
-        /* TODO: select external clock/oscillator */
-        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-        /* set to normal OTG PHY */
-        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-        mdelay(1);
-
-        /* reset OTG PHY and Link */
-        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-                        S3C_RSTCON);
-        udelay(20);     /* at-least 10uS */
-        writel(0, S3C_RSTCON);
-
-        return 0;
-}
-
-static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
-{
-        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-        writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
-                        S5PV210_USB_PHY_CON);
-
-        return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return s5pv210_usb_otgphy_init(pdev);
-
-        return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return s5pv210_usb_otgphy_exit(pdev);
-
-        return -EINVAL;
-}
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 25c68ceb9e2b..7c43ddd33ba8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * Common S5P Sleep Code
+ * S5PV210 Sleep Code
  * Based on S3C64XX sleep code by:
  *      Ben Dooks, (c) 2008 Simtec Electronics
  *
@@ -10,16 +10,7 @@
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
+ */
 
 #include <linux/linkage.h>
 
@@ -40,6 +31,6 @@
          * resume code entry for bootloader to call
          */
 
-ENTRY(s3c_cpu_resume)
+ENTRY(s5pv210_cpu_resume)
         b       cpu_resume
-ENDPROC(s3c_cpu_resume)
+ENDPROC(s5pv210_cpu_resume)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3a6e3c20a86d..e15dff790dbb 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -12,6 +12,7 @@ menuconfig ARCH_SHMOBILE_MULTI
         select NO_IOPORT_MAP
         select PINCTRL
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_OPP
 
 if ARCH_SHMOBILE_MULTI
 
@@ -25,6 +26,11 @@ config ARCH_R7S72100
         bool "RZ/A1H (R7S72100)"
         select SYS_SUPPORTS_SH_MTU2
 
+config ARCH_R8A7779
+        bool "R-Car H1 (R8A77790)"
+        select RENESAS_INTC_IRQPIN
+        select SYS_SUPPORTS_SH_TMU
+
 config ARCH_R8A7790
         bool "R-Car H2 (R8A77900)"
         select RENESAS_IRQC
@@ -51,6 +57,11 @@ config MACH_LAGER
         depends on ARCH_R8A7790
         select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+        bool "MARZEN board"
+        depends on ARCH_R8A7779
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
@@ -233,19 +244,6 @@ config MACH_MARZEN
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select USE_OF
 
-config MACH_MARZEN_REFERENCE
-        bool "MARZEN board - Reference Device Tree Implementation"
-        depends on ARCH_R8A7779
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select USE_OF
-        ---help---
-           Use reference implementation of Marzen board support
-           which makes use of device tree at the expense
-           of not supporting a number of devices.
-
-           This is intended to aid developers
-
 config MACH_LAGER
         bool "Lager board"
         depends on ARCH_R8A7790
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 38d5fe825e93..fe3878a1a69a 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -34,31 +34,39 @@ obj-$(CONFIG_ARCH_R8A7791)	+= clock-r8a7791.o
 obj-$(CONFIG_ARCH_R7S72100)     += clock-r7s72100.o
 endif
 
+# CPU reset vector handling objects
+cpu-y                           := platsmp.o headsmp.o
+cpu-$(CONFIG_ARCH_R8A7790)      += platsmp-apmu.o
+cpu-$(CONFIG_ARCH_R8A7791)      += platsmp-apmu.o
+
 # SMP objects
-smp-y                           := platsmp.o headsmp.o
+smp-y                           := $(cpu-y)
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
-smp-$(CONFIG_ARCH_R8A7790)      += smp-r8a7790.o platsmp-apmu.o
-smp-$(CONFIG_ARCH_R8A7791)      += smp-r8a7791.o platsmp-apmu.o
+smp-$(CONFIG_ARCH_R8A7790)      += smp-r8a7790.o
+smp-$(CONFIG_ARCH_R8A7791)      += smp-r8a7791.o
 smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o platsmp-scu.o
 
-# IRQ objects
-obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
-
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o pm-rmobile.o
 obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o pm-rcar.o
-obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o
+obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o $(cpu-y)
+obj-$(CONFIG_ARCH_R8A7791)      += pm-r8a7791.o pm-rcar.o $(cpu-y)
+
+# IRQ objects
+obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)       += board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)    += board-ape6evm-reference.o
@@ -67,7 +75,6 @@ obj-$(CONFIG_MACH_BOCKW)	+= board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 918fccffa1b6..ebf97d4bcfd8 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -13,7 +13,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR      := $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index 1d3f67d4ccd6..0b1fb2345aa1 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -23,11 +23,13 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
-#include <mach/r8a7791.h>
+
 #include <asm/mach/arch.h>
+
 #include "clock.h"
 #include "common.h"
 #include "irqs.h"
+#include "r8a7791.h"
 #include "rcar-gen2.h"
 
 /* DU */
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index c932f2ca85b1..766442f82948 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -45,11 +45,13 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
-#include <mach/r8a7791.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+
 #include "common.h"
 #include "irqs.h"
+#include "r8a7791.h"
 #include "rcar-gen2.h"
 
 /* DU */
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 94bd57203ff5..21b3e1ca2261 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,19 +19,42 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <mach/r8a7779.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
+#include <linux/of_platform.h>
+
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
+
+#include "clock.h"
 #include "common.h"
 #include "irqs.h"
+#include "r8a7779.h"
+
+static void __init marzen_init_timer(void)
+{
+        r8a7779_clocks_init(r8a7779_read_mode_pins());
+        clocksource_of_init();
+}
+
+/*
+ * This is a really crude hack to provide clkdev support to platform
+ * devices until they get moved to DT.
+ */
+static const struct clk_name clk_names[] __initconst = {
+        { "tmu0", "fck", "sh-tmu.0" },
+};
 
 static void __init marzen_init(void)
 {
+        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
         r8a7779_add_standard_devices_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+        "renesas,marzen",
         "renesas,marzen-reference",
         NULL,
 };
@@ -39,7 +62,8 @@ static const char *marzen_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(MARZEN, "marzen")
         .smp            = smp_ops(r8a7779_smp_ops),
         .map_io         = r8a7779_map_io,
-        .init_early     = r8a7779_init_delay,
+        .init_early     = shmobile_init_delay,
+        .init_time      = marzen_init_timer,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = marzen_init,
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index d0b5b746fe05..e5cf4201e769 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -41,13 +41,15 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+
 #include <media/soc_camera.h>
-#include <mach/r8a7779.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/traps.h>
+
 #include "common.h"
 #include "irqs.h"
+#include "r8a7779.h"
 
 /* Fixed 3.3V regulator to be used by SDHI0 */
 static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 0f431498229b..49d139748aa6 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -574,11 +574,17 @@ static struct clk_lookup lookups[] = {
 
         /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
+        CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
+        CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 789091cfa37a..a60c324df64e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -556,27 +556,27 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
-        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.serial",        &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
-        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.serial",        &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
-        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.serial",        &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
-        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.serial",        &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
-        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.serial",        &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
-        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.serial",        &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
-        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.serial",        &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
-        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.serial",        &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
-        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.serial",        &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("fe1f0000.sound",         &mstp_clks[MSTP328]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 16bbc94a1520..95579073cfce 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -202,11 +202,17 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
+        CLKDEV_DEV_ID("ffe40000.serial", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
+        CLKDEV_DEV_ID("ffe41000.serial", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
+        CLKDEV_DEV_ID("ffe42000.serial", &mstp_clks[MSTP024]), /* SCIF2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
+        CLKDEV_DEV_ID("ffe43000.serial", &mstp_clks[MSTP023]), /* SCIF3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
+        CLKDEV_DEV_ID("ffe44000.serial", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("ffe45000.serial", &mstp_clks[MSTP021]), /* SCIF5 */
         CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index d81539a26dbd..c51f9db3f66f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,8 +23,11 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <linux/sh_timer.h>
+
 #include "clock.h"
 #include "common.h"
+#include "r8a7779.h"
 
 /*
  *              MD1 = 1                 MD1 = 0
@@ -52,9 +55,6 @@
 #define MSTPCR3         IOMEM(0xffc8003c)
 #define MSTPSR1         IOMEM(0xffc80044)
 
-#define MODEMR          0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -207,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-        u32 mode;
+        u32 mode = r8a7779_read_mode_pins();
         int k, ret = 0;
 
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
         if (mode & MD(1)) {
                 plla_clk.rate = 1500000000;
 
@@ -268,3 +263,13 @@ void __init r8a7779_clock_init(void)
         else
                 panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+        r8a7779_clock_init();
+        r8a7779_register_twd();
+        shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 37f48383e05a..9433a4e2c88e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -638,16 +638,25 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
+        CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), /* SCIFA1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), /* SCIFA2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+        CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP331]), /* SCIFA6 */
         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index f7a360edcc35..98056081f0da 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -35,8 +35,10 @@ extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 
 #ifdef CONFIG_SUSPEND
 int shmobile_suspend_init(void);
+void shmobile_smp_apmu_suspend_init(void);
 #else
 static inline int shmobile_suspend_init(void) { return 0; }
+static inline void shmobile_smp_apmu_suspend_init(void) { }
 #endif
 
 #ifdef CONFIG_CPU_IDLE
@@ -45,12 +47,19 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
+#ifdef CONFIG_CPU_FREQ
+int shmobile_cpufreq_init(void);
+#else
+static inline int shmobile_cpufreq_init(void) { return 0; }
+#endif
+
 extern void __iomem *shmobile_scu_base;
 
 static inline void __init shmobile_init_late(void)
 {
         shmobile_suspend_init();
         shmobile_cpuidle_init();
+        shmobile_cpufreq_init();
 }
 
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/cpufreq.c b/arch/arm/mach-shmobile/cpufreq.c
new file mode 100644
index 000000000000..8a24b2be46ae
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpufreq.c
@@ -0,0 +1,17 @@
+/*
+ * CPUFreq support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2014 Gaku Inami
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+
+int __init shmobile_cpufreq_init(void)
+{
+        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
+        return 0;
+}
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 293007579b8e..50c491567e11 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -10,15 +10,18 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/linkage.h>
 #include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/threads.h>
 #include <asm/assembler.h>
 #include <asm/memory.h>
 
+#ifdef CONFIG_SMP
 ENTRY(shmobile_invalidate_start)
         bl      v7_invalidate_l1
         b       secondary_startup
 ENDPROC(shmobile_invalidate_start)
+#endif
 
 /*
  * Reset vector for secondary CPUs.
@@ -69,7 +72,7 @@ shmobile_smp_boot_find_mpidr:
 
 shmobile_smp_boot_next:
         add     r1, r1, #1
-        cmp     r1, #CONFIG_NR_CPUS
+        cmp     r1, #NR_CPUS
         blo     shmobile_smp_boot_find_mpidr
 
         b       shmobile_smp_sleep
@@ -86,10 +89,10 @@ ENDPROC(shmobile_smp_sleep)
 
         .globl  shmobile_smp_mpidr
 shmobile_smp_mpidr:
-1:      .space  CONFIG_NR_CPUS * 4
+1:      .space  NR_CPUS * 4
         .globl  shmobile_smp_fn
 shmobile_smp_fn:
-2:      .space  CONFIG_NR_CPUS * 4
+2:      .space  NR_CPUS * 4
         .globl  shmobile_smp_arg
 shmobile_smp_arg:
-3:      .space  CONFIG_NR_CPUS * 4
+3:      .space  NR_CPUS * 4
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index fe648f5d8f06..2c06810d3a70 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -7,27 +7,32 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/cpu_pm.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/suspend.h>
+#include <linux/threads.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/proc-fns.h>
 #include <asm/smp_plat.h>
+#include <asm/suspend.h>
 #include "common.h"
 
 static struct {
         void __iomem *iomem;
         int bit;
-} apmu_cpus[CONFIG_NR_CPUS];
+} apmu_cpus[NR_CPUS];
 
 #define WUPCR_OFFS 0x10
 #define PSTR_OFFS 0x40
 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
 
-static int apmu_power_on(void __iomem *p, int bit)
+static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
 {
         /* request power on */
         writel_relaxed(BIT(bit), p + WUPCR_OFFS);
@@ -46,7 +51,7 @@ static int apmu_power_off(void __iomem *p, int bit)
         return 0;
 }
 
-static int apmu_power_off_poll(void __iomem *p, int bit)
+static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
 {
         int k;
 
@@ -69,7 +74,7 @@ static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
 
 static void apmu_init_cpu(struct resource *res, int cpu, int bit)
 {
-        if (apmu_cpus[cpu].iomem)
+        if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
                 return;
 
         apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
@@ -133,6 +138,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
         apmu_parse_cfg(apmu_init_cpu);
 }
 
+#ifdef CONFIG_SMP
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         /* For this particular CPU register boot vector */
@@ -140,8 +146,9 @@ int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         return apmu_wrap(cpu, apmu_power_on);
 }
+#endif
 
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
 /* nicked from arch/arm/mach-exynos/hotplug.c */
 static inline void cpu_enter_lowpower_a15(void)
 {
@@ -172,16 +179,40 @@ static inline void cpu_enter_lowpower_a15(void)
         dsb();
 }
 
-void shmobile_smp_apmu_cpu_die(unsigned int cpu)
+void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
 {
-        /* For this particular CPU deregister boot vector */
-        shmobile_smp_hook(cpu, 0, 0);
 
         /* Select next sleep mode using the APMU */
         apmu_wrap(cpu, apmu_power_off);
 
         /* Do ARM specific CPU shutdown */
         cpu_enter_lowpower_a15();
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile("mrc    p15, 0, %0, c1, c0, 0\n"
+                     "       orr     %0, %0, %1\n"
+                     "       mcr     p15, 0, %0, c1, c0, 0\n"
+                     "       mrc     p15, 0, %0, c1, c0, 1\n"
+                     "       orr     %0, %0, %2\n"
+                     "       mcr     p15, 0, %0, c1, c0, 1\n"
+                     : "=&r" (v)
+                     : "Ir" (CR_C), "Ir" (0x40)
+                     : "cc");
+}
+#endif
+
+#if defined(CONFIG_HOTPLUG_CPU)
+void shmobile_smp_apmu_cpu_die(unsigned int cpu)
+{
+        /* For this particular CPU deregister boot vector */
+        shmobile_smp_hook(cpu, 0, 0);
+
+        /* Shutdown CPU core */
+        shmobile_smp_apmu_cpu_shutdown(cpu);
 
         /* jump to shared mach-shmobile sleep / reset code */
         shmobile_smp_sleep();
@@ -192,3 +223,25 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
         return apmu_wrap(cpu, apmu_power_off_poll);
 }
 #endif
+
+#if defined(CONFIG_SUSPEND)
+static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
+{
+        shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
+        shmobile_smp_apmu_cpu_shutdown(cpu);
+        cpu_do_idle(); /* WFI selects Core Standby */
+        return 1;
+}
+
+static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
+{
+        cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
+        cpu_leave_lowpower();
+        return 0;
+}
+
+void __init shmobile_smp_apmu_suspend_init(void)
+{
+        shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
+}
+#endif
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index f0f36cb5ffe7..69f70b7f7fb2 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -19,10 +19,12 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
+
 #include <asm/io.h>
-#include <mach/r8a7779.h>
+
 #include "common.h"
 #include "pm-rcar.h"
+#include "r8a7779.h"
 
 /* SYSC */
 #define SYSCIER 0x0c
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
index 8845433a00b3..80e8d95e54d3 100644
--- a/arch/arm/mach-shmobile/pm-r8a7790.c
+++ b/arch/arm/mach-shmobile/pm-r8a7790.c
@@ -11,12 +11,22 @@
  */
 
 #include <linux/kernel.h>
-
+#include <linux/smp.h>
 #include <asm/io.h>
-
+#include "common.h"
 #include "pm-rcar.h"
 #include "r8a7790.h"
 
+/* RST */
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA7BAR          0x0030
+#define CA15RESCNT      0x0040
+#define CA7RESCNT       0x0044
+
+/* On-chip RAM */
+#define MERAM          0xe8080000
+
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
@@ -40,8 +50,33 @@ static inline void r8a7790_sysc_init(void) {}
 
 void __init r8a7790_pm_init(void)
 {
+        void __iomem *p;
+        u32 bar;
         static int once;
 
-        if (!once++)
-                r8a7790_sysc_init();
+        if (once++)
+                return;
+
+        /* MERAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(MERAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (MERAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar, p + CA7BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA7BAR);
+
+        /* de-assert reset for all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
+                       p + CA7RESCNT);
+        iounmap(p);
+
+        r8a7790_sysc_init();
+        shmobile_smp_apmu_suspend_init();
 }
diff --git a/arch/arm/mach-shmobile/pm-r8a7791.c b/arch/arm/mach-shmobile/pm-r8a7791.c
new file mode 100644
index 000000000000..25f107bb3657
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7791.c
@@ -0,0 +1,73 @@
+/*
+ * r8a7791 Power management support
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <asm/io.h>
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7791.h"
+
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA15RESCNT      0x0040
+#define RAM             0xe6300000
+
+/* SYSC */
+#define SYSCIER 0x0c
+#define SYSCIMR 0x10
+
+#if defined(CONFIG_SMP)
+
+static void __init r8a7791_sysc_init(void)
+{
+        void __iomem *base = rcar_sysc_init(0xe6180000);
+
+        /* enable all interrupt sources, but do not use interrupt handler */
+        iowrite32(0x0131000e, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
+}
+
+#else /* CONFIG_SMP */
+
+static inline void r8a7791_sysc_init(void) {}
+
+#endif /* CONFIG_SMP */
+
+void __init r8a7791_pm_init(void)
+{
+        void __iomem *p;
+        u32 bar;
+        static int once;
+
+        if (once++)
+                return;
+
+        /* RAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(RAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (RAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+
+        /* enable clocks to all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        iounmap(p);
+
+        r8a7791_sysc_init();
+        shmobile_smp_apmu_suspend_init();
+}
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h
index def10a29e09a..5415c719dc19 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/r8a7779.h
@@ -10,7 +10,6 @@ enum {
         HPBDMA_SLAVE_SDHI0_RX,
 };
 
-extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq_extpin(int irlm);
 extern void r8a7779_init_irq_extpin_dt(int irlm);
 extern void r8a7779_init_irq_dt(void);
@@ -20,6 +19,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index 664274cc4b64..86eae7bceb6f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -5,6 +5,7 @@ void r8a7791_add_standard_devices(void);
 void r8a7791_add_dt_devices(void);
 void r8a7791_clock_init(void);
 void r8a7791_pinmux_init(void);
+void r8a7791_pm_init(void);
 extern struct smp_operations r8a7791_smp_ops;
 
 #endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h
index 43f606eb2d82..ce53cb5f53a1 100644
--- a/arch/arm/mach-shmobile/rcar-gen2.h
+++ b/arch/arm/mach-shmobile/rcar-gen2.h
@@ -4,5 +4,6 @@
 void rcar_gen2_timer_init(void);
 #define MD(nr) BIT(nr)
 u32 rcar_gen2_read_mode_pins(void);
+void rcar_gen2_reserve(void);
 
 #endif /* __ASM_RCAR_GEN2_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 280303cef702..236c1befb9e3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -40,14 +40,16 @@
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/pm_runtime.h>
-#include <mach/r8a7779.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
+
 #include "common.h"
 #include "irqs.h"
+#include "r8a7779.h"
 
 static struct map_desc r8a7779_io_desc[] __initdata = {
         /* 2M entity map for 0xf0000000 (MPCORE) */
@@ -640,16 +642,16 @@ static void __init r8a7779_register_hpb_dmae(void)
 }
 
 static struct platform_device *r8a7779_devices_dt[] __initdata = {
+        &tmu0_device,
+};
+
+static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
         &scif3_device,
         &scif4_device,
         &scif5_device,
-        &tmu0_device,
-};
-
-static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
@@ -674,16 +676,6 @@ void __init r8a7779_add_standard_devices(void)
         r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-        r8a7779_clock_init();
-        r8a7779_register_twd();
-        shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
         early_platform_add_devices(r8a7779_devices_dt,
@@ -747,19 +739,28 @@ void __init r8a7779_init_irq_dt(void)
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
 
-void __init r8a7779_init_delay(void)
+void __init r8a7779_add_standard_devices_dt(void)
 {
-        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
 }
 
-void __init r8a7779_add_standard_devices_dt(void)
+#define MODEMR          0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
 {
-        /* clocks are setup late during boot in the case of DT */
-        r8a7779_clock_init();
+        static u32 mode;
+        static bool mode_valid;
+
+        if (!mode_valid) {
+                void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+                BUG_ON(!modemr);
+                mode = ioread32(modemr);
+                iounmap(modemr);
+                mode_valid = true;
+        }
 
-        platform_add_devices(r8a7779_devices_dt,
-                             ARRAY_SIZE(r8a7779_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        return mode;
 }
 
 static const char *r8a7779_compat_dt[] __initdata = {
@@ -769,7 +770,7 @@ static const char *r8a7779_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
         .map_io         = r8a7779_map_io,
-        .init_early     = r8a7779_init_delay,
+        .init_early     = shmobile_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = r8a7779_add_standard_devices_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 240411b42424..0c12b01bb9e3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -321,6 +321,8 @@ DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
         .smp            = smp_ops(r8a7790_smp_ops),
         .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
+        .init_late      = shmobile_init_late,
+        .reserve        = rcar_gen2_reserve,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index 004b11a8fd88..d47d8b16a43f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -26,10 +26,12 @@
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
-#include <mach/r8a7791.h>
+
 #include <asm/mach/arch.h>
+
 #include "common.h"
 #include "irqs.h"
+#include "r8a7791.h"
 #include "rcar-gen2.h"
 
 static const struct resource pfc_resources[] __initconst = {
@@ -217,6 +219,8 @@ DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
         .smp            = smp_ops(r8a7791_smp_ops),
         .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
+        .init_late      = shmobile_init_late,
+        .reserve        = rcar_gen2_reserve,
         .dt_compat      = r8a7791_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index fdc714ebc4cd..42d5b4308923 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -20,8 +20,11 @@
 
 #include <linux/clk/shmobile.h>
 #include <linux/clocksource.h>
+#include <linux/device.h>
+#include <linux/dma-contiguous.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_fdt.h>
 #include <asm/mach/arch.h>
 #include "common.h"
 #include "rcar-gen2.h"
@@ -110,3 +113,72 @@ void __init rcar_gen2_timer_init(void)
 #endif
         clocksource_of_init();
 }
+
+struct memory_reserve_config {
+        u64 reserved;
+        u64 base, size;
+};
+
+static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
+                                     int depth, void *data)
+{
+        const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
+        const __be32 *reg, *endp;
+        int l;
+        struct memory_reserve_config *mrc = data;
+        u64 lpae_start = 1ULL << 32;
+
+        /* We are scanning "memory" nodes only */
+        if (type == NULL || strcmp(type, "memory"))
+                return 0;
+
+        reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
+        if (reg == NULL)
+                reg = of_get_flat_dt_prop(node, "reg", &l);
+        if (reg == NULL)
+                return 0;
+
+        endp = reg + (l / sizeof(__be32));
+        while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
+                u64 base, size;
+
+                base = dt_mem_next_cell(dt_root_addr_cells, &reg);
+                size = dt_mem_next_cell(dt_root_size_cells, &reg);
+
+                if (base >= lpae_start)
+                        continue;
+
+                if ((base + size) >= lpae_start)
+                        size = lpae_start - base;
+
+                if (size < mrc->reserved)
+                        continue;
+
+                if (base < mrc->base)
+                        continue;
+
+                /* keep the area at top near the 32-bit legacy limit */
+                mrc->base = base + size - mrc->reserved;
+                mrc->size = mrc->reserved;
+        }
+
+        return 0;
+}
+
+struct cma *rcar_gen2_dma_contiguous;
+
+void __init rcar_gen2_reserve(void)
+{
+        struct memory_reserve_config mrc;
+
+        /* reserve 256 MiB at the top of the physical legacy 32-bit space */
+        memset(&mrc, 0, sizeof(mrc));
+        mrc.reserved = SZ_256M;
+
+        of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
+#ifdef CONFIG_DMA_CMA
+        if (mrc.size)
+                dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
+                                            &rcar_gen2_dma_contiguous, true);
+#endif
+}
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index c230fc0c3fef..3100e355c3fd 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,13 +23,15 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/r8a7779.h>
+
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
+
 #include "common.h"
 #include "pm-rcar.h"
+#include "r8a7779.h"
 
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE 0xf0000000
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index c256fdfbb5b0..2311694636e1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -24,13 +24,6 @@
 #include "pm-rcar.h"
 #include "r8a7790.h"
 
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA7BAR          0x0030
-#define CA15RESCNT      0x0040
-#define CA7RESCNT       0x0044
-#define MERAM           0xe8080000
-
 static struct rcar_sysc_ch r8a7790_ca15_scu = {
         .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */
         .isr_bit = 12, /* CA15-SCU */
@@ -43,32 +36,9 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
 
 static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void __iomem *p;
-        u32 bar;
-
         /* let APMU code install data related to shmobile_boot_vector */
         shmobile_smp_apmu_prepare_cpus(max_cpus);
 
-        /* MERAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(MERAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (MERAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar, p + CA7BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA7BAR);
-
-        /* enable clocks to all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
-                       p + CA7RESCNT);
-        iounmap(p);
-
         /* turn on power to SCU */
         r8a7790_pm_init();
         rcar_sysc_power_up(&r8a7790_ca15_scu);
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 2648d68650e4..f743386166fb 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -17,39 +17,19 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+
 #include <asm/smp_plat.h>
-#include <mach/r8a7791.h>
+
 #include "common.h"
+#include "r8a7791.h"
 #include "rcar-gen2.h"
 
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA15RESCNT      0x0040
-#define RAM             0xe6300000
-
 static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void __iomem *p;
-        u32 bar;
-
         /* let APMU code install data related to shmobile_boot_vector */
         shmobile_smp_apmu_prepare_cpus(max_cpus);
 
-        /* RAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(RAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (RAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-
-        /* enable clocks to all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        iounmap(p);
+        r8a7791_pm_init();
 }
 
 static int r8a7791_smp_boot_secondary(unsigned int cpu,
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 68bc0b82226d..942efdc82a62 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -59,29 +59,37 @@ void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 
 void __init shmobile_init_delay(void)
 {
-        struct device_node *np, *parent;
-        u32 max_freq, freq;
-
-        max_freq = 0;
-
-        parent = of_find_node_by_path("/cpus");
-        if (parent) {
-                for_each_child_of_node(parent, np) {
-                        if (!of_property_read_u32(np, "clock-frequency", &freq))
-                                max_freq = max(max_freq, freq);
-                }
-                of_node_put(parent);
-        }
+        struct device_node *np, *cpus;
+        bool is_a8_a9 = false;
+        bool is_a15 = false;
+        u32 max_freq = 0;
+
+        cpus = of_find_node_by_path("/cpus");
+        if (!cpus)
+                return;
+
+        for_each_child_of_node(cpus, np) {
+                u32 freq;
+
+                if (!of_property_read_u32(np, "clock-frequency", &freq))
+                        max_freq = max(max_freq, freq);
 
-        if (max_freq) {
-                if (of_find_compatible_node(NULL, NULL, "arm,cortex-a8"))
-                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
-                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a15"))
-                        if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
-                                shmobile_setup_delay_hz(max_freq, 2, 4);
+                if (of_device_is_compatible(np, "arm,cortex-a8") ||
+                    of_device_is_compatible(np, "arm,cortex-a9"))
+                        is_a8_a9 = true;
+                else if (of_device_is_compatible(np, "arm,cortex-a15"))
+                        is_a15 = true;
         }
+
+        of_node_put(cpus);
+
+        if (!max_freq)
+                return;
+
+        if (is_a8_a9)
+                shmobile_setup_delay_hz(max_freq, 1, 3);
+        else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+                shmobile_setup_delay_hz(max_freq, 2, 4);
 }
 
 static void __init shmobile_late_time_init(void)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index d46b9495cd55..1aaa1e15ef70 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -34,4 +34,12 @@ config MACH_SUN7I
         select HAVE_ARM_ARCH_TIMER
         select SUN5I_HSTIMER
 
+config MACH_SUN8I
+        bool "Allwinner A23 (sun8i) SoCs support"
+        default ARCH_SUNXI
+        select ARCH_HAS_RESET_CONTROLLER
+        select ARM_GIC
+        select MFD_SUN6I_PRCM
+        select RESET_CONTROLLER
+
 endif
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index b6085084e0ff..42d4753683ce 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -130,3 +130,12 @@ DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
         .dt_compat      = sun7i_board_dt_compat,
         .restart        = sun4i_restart,
 MACHINE_END
+
+static const char * const sun8i_board_dt_compat[] = {
+        "allwinner,sun8i-a23",
+        NULL,
+};
+
+DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
+        .dt_compat      = sun8i_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index 3621b000a0f6..9f9bc61ca64b 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -44,7 +44,6 @@ static const char *versatile_dt_match[] __initconst = {
 DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
-        .init_irq       = versatile_init_irq,
         .init_machine   = versatile_dt_init,
         .dt_compat      = versatile_dt_match,
         .restart        = versatile_restart,
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 577039a3f6e5..ae69809a9e47 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -854,7 +854,7 @@ config OUTER_CACHE_SYNC
 
 config CACHE_FEROCEON_L2
         bool "Enable the Feroceon L2 cache controller"
-        depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
+        depends on ARCH_MV78XX0 || ARCH_MVEBU
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 1c98659bbf89..c2baa8ede543 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2102,7 +2102,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
                                 DMA_DEFAULT_FIFO_DEPTH, 0);
 
-        if (dma_omap2plus()) {
+        if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
                 strcpy(irq_name, "0");
                 dma_irq = platform_get_irq_byname(pdev, irq_name);
                 if (dma_irq < 0) {
@@ -2147,7 +2147,8 @@ static int omap_system_dma_remove(struct platform_device *pdev)
                 char irq_name[4];
                 strcpy(irq_name, "0");
                 dma_irq = platform_get_irq_byname(pdev, irq_name);
-                remove_irq(dma_irq, &omap24xx_dma_irq);
+                if (dma_irq >= 0)
+                        remove_irq(dma_irq, &omap24xx_dma_irq);
         } else {
                 int irq_rel = 0;
                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6910c8669742..c87aefbf3a13 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,30 +6,16 @@
 
 config PLAT_SAMSUNG
         bool
-        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
+        depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
         default y
         select GENERIC_IRQ_CHIP
         select NO_IOPORT_MAP
         help
           Base platform code for all Samsung SoC based systems
 
-config PLAT_S5P
-        bool
-        depends on ARCH_S5PV210
-        default y
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_VIC
-        select NO_IOPORT_MAP
-        select PLAT_SAMSUNG
-        select S3C_GPIO_TRACK
-        select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC if !COMMON_CLK
-        help
-          Base platform code for Samsung's S5P series SoC.
-
 config SAMSUNG_PM
         bool
-        depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
+        depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
         default y
         help
           Base platform power management code for samsung code
@@ -65,48 +51,6 @@ config SAMSUNG_ATAGS
 
 if SAMSUNG_ATAGS
 
-# clock options
-
-config SAMSUNG_CLOCK
-        bool
-        default y if !COMMON_CLK
-
-config SAMSUNG_CLKSRC
-        bool
-        help
-          Select the clock code for the clksrc implementation
-          used by newer systems such as the S3C64XX.
-
-config S5P_CLOCK
-        def_bool ARCH_S5PV210
-        help
-          Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
-
-# options for IRQ support
-
-config S5P_IRQ
-        def_bool ARCH_S5PV210
-        help
-          Support common interrupt part for ARCH_S5P SoCs
-
-config S5P_EXT_INT
-        bool
-        help
-          Use the external interrupts (other than GPIO interrupts.)
-
-config S5P_GPIO_INT
-        bool
-        help
-          Common code for the GPIO interrupts (other than external interrupts.)
-
-# options for gpio configuration support
-
-config S5P_GPIO_DRVSTR
-        bool
-        help
-          Internal configuration to get and set correct GPIO driver strength
-          helper
-
 config S3C_GPIO_SPACE
         int "Space between gpio banks"
         default 0
@@ -122,12 +66,6 @@ config S3C_GPIO_TRACK
           Internal configuration option to enable the s3c specific gpio
           chip tracking if the platform requires it.
 
-# uart options
-
-config S5P_DEV_UART
-        def_bool y
-        depends on ARCH_S5PV210
-
 # ADC driver
 
 config S3C_ADC
@@ -285,66 +223,6 @@ config SAMSUNG_DEV_BACKLIGHT
         help
           Compile in platform device definition LCD backlight with PWM Timer
 
-config S5P_DEV_CSIS0
-        bool
-        help
-          Compile in platform device definitions for MIPI-CSIS channel 0
-
-config S5P_DEV_CSIS1
-        bool
-        help
-          Compile in platform device definitions for MIPI-CSIS channel 1
-
-config S5P_DEV_FIMC0
-        bool
-        help
-          Compile in platform device definitions for FIMC controller 0
-
-config S5P_DEV_FIMC1
-        bool
-        help
-          Compile in platform device definitions for FIMC controller 1
-
-config S5P_DEV_FIMC2
-        bool
-        help
-          Compile in platform device definitions for FIMC controller 2
-
-config S5P_DEV_FIMC3
-        bool
-        help
-          Compile in platform device definitions for FIMC controller 3
-
-config S5P_DEV_FIMD0
-        bool
-        help
-          Compile in platform device definitions for FIMD controller 0
-
-config S5P_DEV_G2D
-        bool
-        help
-          Compile in platform device definitions for G2D device
-
-config S5P_DEV_I2C_HDMIPHY
-        bool
-        help
-          Compile in platform device definitions for I2C HDMIPHY controller
-
-config S5P_DEV_JPEG
-        bool
-        help
-          Compile in platform device definitions for JPEG codec
-
-config S5P_DEV_ONENAND
-        bool
-        help
-          Compile in platform device definition for OneNAND controller
-
-config S5P_DEV_TV
-        bool
-        help
-          Compile in platform device definition for TV interface
-
 config S3C24XX_PWM
         bool "PWM device support"
         select PWM
@@ -365,12 +243,6 @@ config S3C_DMA
         help
           Internal configuration for S3C DMA core
 
-config S5P_IRQ_PM
-        bool
-        default y if S5P_PM
-        help
-          Legacy IRQ power management for S5P platforms
-
 config SAMSUNG_PM_GPIO
         bool
         default y if GPIO_SAMSUNG && PM
@@ -453,17 +325,6 @@ config SAMSUNG_WDT_RESET
           Compile support for system restart by triggering watchdog reset.
           Used on SoCs that do not provide dedicated reset control.
 
-config S5P_PM
-        bool
-        help
-          Common code for power management support on S5P and newer SoCs
-
-config S5P_SLEEP
-        bool
-        help
-          Internal config node to apply common S5P sleep management code.
-          Can be selected by S5P and newer SoCs with similar sleep procedure.
-
 config DEBUG_S3C_UART
         depends on PLAT_SAMSUNG
         int
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 5e5beaa9ae15..5fe175017f07 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -5,7 +5,6 @@
 # Licensed under GPLv2
 
 ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
-ccflags-$(CONFIG_ARCH_EXYNOS)   += -I$(srctree)/arch/arm/mach-exynos/include
 
 obj-y                           :=
 obj-m                           :=
@@ -16,15 +15,6 @@ obj-				:=
 
 obj-y                           += init.o cpu.o
 
-obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
-
-obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
-obj-$(CONFIG_S5P_CLOCK)         += s5p-clock.o
-
-obj-$(CONFIG_S5P_IRQ)           += s5p-irq.o
-obj-$(CONFIG_S5P_EXT_INT)       += s5p-irq-eint.o
-obj-$(CONFIG_S5P_GPIO_INT)      += s5p-irq-gpioint.o
-
 # ADC
 
 obj-$(CONFIG_S3C_ADC)   += adc.o
@@ -36,7 +26,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS)	+= platformdata.o
 obj-$(CONFIG_SAMSUNG_ATAGS)     += devs.o
 obj-$(CONFIG_SAMSUNG_ATAGS)     += dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)       += s5p-dev-mfc.o
-obj-$(CONFIG_S5P_DEV_UART)      += s5p-dev-uart.o
 
 obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT)     += dev-backlight.o
 
@@ -58,7 +47,3 @@ obj-$(CONFIG_SAMSUNG_PM_DEBUG)	+= pm-debug.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
 obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
-
-obj-$(CONFIG_S5P_PM)            += s5p-pm.o
-obj-$(CONFIG_S5P_IRQ_PM)        += s5p-irq-pm.o
-obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
deleted file mode 100644
index 786a4107a157..000000000000
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* linux/arch/arm/plat-samsung/clock-clksrc.c
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu-freq.h>
-
-static inline struct clksrc_clk *to_clksrc(struct clk *clk)
-{
-        return container_of(clk, struct clksrc_clk, clk);
-}
-
-static inline u32 bit_mask(u32 shift, u32 nr_bits)
-{
-        u32 mask = 0xffffffff >> (32 - nr_bits);
-
-        return mask << shift;
-}
-
-static unsigned long s3c_getrate_clksrc(struct clk *clk)
-{
-        struct clksrc_clk *sclk = to_clksrc(clk);
-        unsigned long rate = clk_get_rate(clk->parent);
-        u32 clkdiv = __raw_readl(sclk->reg_div.reg);
-        u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
-
-        clkdiv &= mask;
-        clkdiv >>= sclk->reg_div.shift;
-        clkdiv++;
-
-        rate /= clkdiv;
-        return rate;
-}
-
-static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
-{
-        struct clksrc_clk *sclk = to_clksrc(clk);
-        void __iomem *reg = sclk->reg_div.reg;
-        unsigned int div;
-        u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
-        u32 val;
-
-        rate = clk_round_rate(clk, rate);
-        div = clk_get_rate(clk->parent) / rate;
-        if (div > (1 << sclk->reg_div.size))
-                return -EINVAL;
-
-        val = __raw_readl(reg);
-        val &= ~mask;
-        val |= (div - 1) << sclk->reg_div.shift;
-        __raw_writel(val, reg);
-
-        return 0;
-}
-
-static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
-{
-        struct clksrc_clk *sclk = to_clksrc(clk);
-        struct clksrc_sources *srcs = sclk->sources;
-        u32 clksrc = __raw_readl(sclk->reg_src.reg);
-        u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
-        int src_nr = -1;
-        int ptr;
-
-        for (ptr = 0; ptr < srcs->nr_sources; ptr++)
-                if (srcs->sources[ptr] == parent) {
-                        src_nr = ptr;
-                        break;
-                }
-
-        if (src_nr >= 0) {
-                clk->parent = parent;
-
-                clksrc &= ~mask;
-                clksrc |= src_nr << sclk->reg_src.shift;
-
-                __raw_writel(clksrc, sclk->reg_src.reg);
-                return 0;
-        }
-
-        return -EINVAL;
-}
-
-static unsigned long s3c_roundrate_clksrc(struct clk *clk,
-                                              unsigned long rate)
-{
-        struct clksrc_clk *sclk = to_clksrc(clk);
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int max_div = 1 << sclk->reg_div.size;
-        int div;
-
-        if (rate >= parent_rate)
-                rate = parent_rate;
-        else {
-                div = parent_rate / rate;
-                if (parent_rate % rate)
-                        div++;
-
-                if (div == 0)
-                        div = 1;
-                if (div > max_div)
-                        div = max_div;
-
-                rate = parent_rate / div;
-        }
-
-        return rate;
-}
-
-/* Clock initialisation code */
-
-void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
-{
-        struct clksrc_sources *srcs = clk->sources;
-        u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
-        u32 clksrc;
-
-        if (!clk->reg_src.reg) {
-                if (!clk->clk.parent)
-                        printk(KERN_ERR "%s: no parent clock specified\n",
-                                clk->clk.name);
-                return;
-        }
-
-        clksrc = __raw_readl(clk->reg_src.reg);
-        clksrc &= mask;
-        clksrc >>= clk->reg_src.shift;
-
-        if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
-                printk(KERN_ERR "%s: bad source %d\n",
-                       clk->clk.name, clksrc);
-                return;
-        }
-
-        clk->clk.parent = srcs->sources[clksrc];
-
-        if (announce)
-                printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
-                       clk->clk.name, clk->clk.parent->name, clksrc,
-                       clk_get_rate(&clk->clk));
-}
-
-static struct clk_ops clksrc_ops = {
-        .set_parent     = s3c_setparent_clksrc,
-        .get_rate       = s3c_getrate_clksrc,
-        .set_rate       = s3c_setrate_clksrc,
-        .round_rate     = s3c_roundrate_clksrc,
-};
-
-static struct clk_ops clksrc_ops_nodiv = {
-        .set_parent     = s3c_setparent_clksrc,
-};
-
-static struct clk_ops clksrc_ops_nosrc = {
-        .get_rate       = s3c_getrate_clksrc,
-        .set_rate       = s3c_setrate_clksrc,
-        .round_rate     = s3c_roundrate_clksrc,
-};
-
-void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
-{
-        int ret;
-
-        for (; size > 0; size--, clksrc++) {
-                if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
-                        printk(KERN_ERR "%s: clock %s has no registers set\n",
-                               __func__, clksrc->clk.name);
-
-                /* fill in the default functions */
-
-                if (!clksrc->clk.ops) {
-                        if (!clksrc->reg_div.reg)
-                                clksrc->clk.ops = &clksrc_ops_nodiv;
-                        else if (!clksrc->reg_src.reg)
-                                clksrc->clk.ops = &clksrc_ops_nosrc;
-                        else
-                                clksrc->clk.ops = &clksrc_ops;
-                }
-
-                /* setup the clocksource, but do not announce it
-                 * as it may be re-set by the setup routines
-                 * called after the rest of the clocks have been
-                 * registered
-                 */
-                s3c_set_clksrc(clksrc, false);
-
-                ret = s3c24xx_register_clock(&clksrc->clk);
-
-                if (ret < 0) {
-                        printk(KERN_ERR "%s: failed to register %s (%d)\n",
-                               __func__, clksrc->clk.name, ret);
-                }
-        }
-}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
deleted file mode 100644
index d103ac1a52af..000000000000
--- a/arch/arm/plat-samsung/clock.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/clock.c
- *
- * Copyright 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX Core clock control support
- *
- * Based on, and code from linux/arch/arm/mach-versatile/clock.c
- **
- **  Copyright (C) 2004 ARM Limited.
- **  Written by Deep Blue Solutions Limited.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#if defined(CONFIG_DEBUG_FS)
-#include <linux/debugfs.h>
-#endif
-
-#include <asm/irq.h>
-
-#include <plat/cpu-freq.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
-
-/* clock information */
-
-static LIST_HEAD(clocks);
-
-/* We originally used an mutex here, but some contexts (see resume)
- * are calling functions such as clk_set_parent() with IRQs disabled
- * causing an BUG to be triggered.
- */
-DEFINE_SPINLOCK(clocks_lock);
-
-/* Global watchdog clock used by arch_wtd_reset() callback */
-struct clk *s3c2410_wdtclk;
-static int __init s3c_wdt_reset_init(void)
-{
-        s3c2410_wdtclk = clk_get(NULL, "watchdog");
-        if (IS_ERR(s3c2410_wdtclk))
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
-        return 0;
-}
-arch_initcall(s3c_wdt_reset_init);
-
-/* enable and disable calls for use with the clk struct */
-
-static int clk_null_enable(struct clk *clk, int enable)
-{
-        return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (IS_ERR(clk) || clk == NULL)
-                return -EINVAL;
-
-        clk_enable(clk->parent);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        if ((clk->usage++) == 0)
-                (clk->enable)(clk, 1);
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (IS_ERR(clk) || clk == NULL)
-                return;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        if ((--clk->usage) == 0)
-                (clk->enable)(clk, 0);
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        clk_disable(clk->parent);
-}
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (IS_ERR_OR_NULL(clk))
-                return 0;
-
-        if (clk->rate != 0)
-                return clk->rate;
-
-        if (clk->ops != NULL && clk->ops->get_rate != NULL)
-                return (clk->ops->get_rate)(clk);
-
-        if (clk->parent != NULL)
-                return clk_get_rate(clk->parent);
-
-        return clk->rate;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
-                return (clk->ops->round_rate)(clk, rate);
-
-        return rate;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        int ret;
-
-        if (IS_ERR_OR_NULL(clk))
-                return -EINVAL;
-
-        /* We do not default just do a clk->rate = rate as
-         * the clock may have been made this way by choice.
-         */
-
-        WARN_ON(clk->ops == NULL);
-        WARN_ON(clk->ops && clk->ops->set_rate == NULL);
-
-        if (clk->ops == NULL || clk->ops->set_rate == NULL)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        ret = (clk->ops->set_rate)(clk, rate);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        return ret;
-}
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return clk->parent;
-}
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        int ret = 0;
-
-        if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
-                return -EINVAL;
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        if (clk->ops && clk->ops->set_parent)
-                ret = (clk->ops->set_parent)(clk, parent);
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-
-        return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-EXPORT_SYMBOL(clk_disable);
-EXPORT_SYMBOL(clk_get_rate);
-EXPORT_SYMBOL(clk_round_rate);
-EXPORT_SYMBOL(clk_set_rate);
-EXPORT_SYMBOL(clk_get_parent);
-EXPORT_SYMBOL(clk_set_parent);
-
-/* base clocks */
-
-int clk_default_setrate(struct clk *clk, unsigned long rate)
-{
-        clk->rate = rate;
-        return 0;
-}
-
-struct clk_ops clk_ops_def_setrate = {
-        .set_rate       = clk_default_setrate,
-};
-
-struct clk clk_xtal = {
-        .name           = "xtal",
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-};
-
-struct clk clk_ext = {
-        .name           = "ext",
-};
-
-struct clk clk_epll = {
-        .name           = "epll",
-};
-
-struct clk clk_mpll = {
-        .name           = "mpll",
-        .ops            = &clk_ops_def_setrate,
-};
-
-struct clk clk_upll = {
-        .name           = "upll",
-        .parent         = NULL,
-        .ctrlbit        = 0,
-};
-
-struct clk clk_f = {
-        .name           = "fclk",
-        .rate           = 0,
-        .parent         = &clk_mpll,
-        .ctrlbit        = 0,
-};
-
-struct clk clk_h = {
-        .name           = "hclk",
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-struct clk clk_p = {
-        .name           = "pclk",
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-struct clk clk_usb_bus = {
-        .name           = "usb-bus",
-        .rate           = 0,
-        .parent         = &clk_upll,
-};
-
-
-struct clk s3c24xx_uclk = {
-        .name           = "uclk",
-};
-
-/* initialise the clock system */
-
-/**
- * s3c24xx_register_clock() - register a clock
- * @clk: The clock to register
- *
- * Add the specified clock to the list of clocks known by the system.
- */
-int s3c24xx_register_clock(struct clk *clk)
-{
-        if (clk->enable == NULL)
-                clk->enable = clk_null_enable;
-
-        /* fill up the clk_lookup structure and register it*/
-        clk->lookup.dev_id = clk->devname;
-        clk->lookup.con_id = clk->name;
-        clk->lookup.clk = clk;
-        clkdev_add(&clk->lookup);
-
-        return 0;
-}
-
-/**
- * s3c24xx_register_clocks() - register an array of clock pointers
- * @clks: Pointer to an array of struct clk pointers
- * @nr_clks: The number of clocks in the @clks array.
- *
- * Call s3c24xx_register_clock() for all the clock pointers contained
- * in the @clks list. Returns the number of failures.
- */
-int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
-{
-        int fails = 0;
-
-        for (; nr_clks > 0; nr_clks--, clks++) {
-                if (s3c24xx_register_clock(*clks) < 0) {
-                        struct clk *clk = *clks;
-                        printk(KERN_ERR "%s: failed to register %p: %s\n",
-                               __func__, clk, clk->name);
-                        fails++;
-                }
-        }
-
-        return fails;
-}
-
-/**
- * s3c_register_clocks() - register an array of clocks
- * @clkp: Pointer to the first clock in the array.
- * @nr_clks: Number of clocks to register.
- *
- * Call s3c24xx_register_clock() on the @clkp array given, printing an
- * error if it fails to register the clock (unlikely).
- */
-void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
-{
-        int ret;
-
-        for (; nr_clks > 0; nr_clks--, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-}
-
-/**
- * s3c_disable_clocks() - disable an array of clocks
- * @clkp: Pointer to the first clock in the array.
- * @nr_clks: Number of clocks to register.
- *
- * for internal use only at initialisation time. disable the clocks in the
- * @clkp array.
- */
-
-void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
-{
-        for (; nr_clks > 0; nr_clks--, clkp++)
-                (clkp->enable)(clkp, 0);
-}
-
-/* initialise all the clocks */
-
-int __init s3c24xx_register_baseclocks(unsigned long xtal)
-{
-        printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
-
-        clk_xtal.rate = xtal;
-
-        /* register our clocks */
-
-        if (s3c24xx_register_clock(&clk_xtal) < 0)
-                printk(KERN_ERR "failed to register master xtal\n");
-
-        if (s3c24xx_register_clock(&clk_mpll) < 0)
-                printk(KERN_ERR "failed to register mpll clock\n");
-
-        if (s3c24xx_register_clock(&clk_upll) < 0)
-                printk(KERN_ERR "failed to register upll clock\n");
-
-        if (s3c24xx_register_clock(&clk_f) < 0)
-                printk(KERN_ERR "failed to register cpu fclk\n");
-
-        if (s3c24xx_register_clock(&clk_h) < 0)
-                printk(KERN_ERR "failed to register cpu hclk\n");
-
-        if (s3c24xx_register_clock(&clk_p) < 0)
-                printk(KERN_ERR "failed to register cpu pclk\n");
-
-        return 0;
-}
-
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-/* debugfs support to trace clock tree hierarchy and attributes */
-
-static struct dentry *clk_debugfs_root;
-
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
-        struct clk *child;
-        const char *state;
-        char buf[255] = { 0 };
-        int n = 0;
-
-        if (c->name)
-                n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
-
-        if (c->devname)
-                n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
-
-        state = (c->usage > 0) ? "on" : "off";
-
-        seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
-                   level * 3 + 1, "",
-                   50 - level * 3, buf,
-                   state, c->usage, clk_get_rate(c));
-
-        list_for_each_entry(child, &clocks, list) {
-                if (child->parent != c)
-                        continue;
-
-                clock_tree_show_one(s, child, level + 1);
-        }
-}
-
-static int clock_tree_show(struct seq_file *s, void *data)
-{
-        struct clk *c;
-        unsigned long flags;
-
-        seq_printf(s, " clock state ref rate\n");
-        seq_printf(s, "----------------------------------------------------\n");
-
-        spin_lock_irqsave(&clocks_lock, flags);
-
-        list_for_each_entry(c, &clocks, list)
-                if (c->parent == NULL)
-                        clock_tree_show_one(s, c, 0);
-
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clock_tree_show, inode->i_private);
-}
-
-static const struct file_operations clock_tree_fops = {
-        .open           = clock_tree_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int clock_rate_show(void *data, u64 *val)
-{
-        struct clk *c = data;
-        *val = clk_get_rate(c);
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d;
-        struct clk *pa = c->parent;
-        char s[255];
-        char *p = s;
-
-        p += sprintf(p, "%s", c->devname);
-
-        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-
-        c->dent = d;
-
-        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-
-        d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err = -ENOMEM;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
-                                 &clock_tree_fops);
-        if (!d)
-                goto err_out;
-
-        list_for_each_entry(c, &clocks, list) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-late_initcall(clk_debugfs_init);
-
-#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 364963a0a344..360618ee39e5 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -15,8 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-
-#include <mach/map.h>
+#include <plat/map-base.h>
 #include <plat/cpu.h>
 
 unsigned long samsung_cpu_id;
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index ead4f1c94058..83c7d154bde0 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -53,7 +53,6 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <plat/fb.h>
 #include <plat/fb-s3c2410.h>
-#include <plat/hdmi.h>
 #include <linux/platform_data/hwmon-s3c.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
@@ -145,23 +144,6 @@ struct platform_device s3c_device_camif = {
 };
 #endif /* CONFIG_CPU_S3C2440 */
 
-/* ASOC DMA */
-
-#ifdef CONFIG_PLAT_S5P 
-static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
-
-struct platform_device samsung_asoc_idma = {
-        .name           = "samsung-idma",
-        .id             = -1,
-        .num_resources  = 1,
-        .resource       = &samsung_asoc_idma_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-#endif
-
 /* FB */
 
 #ifdef CONFIG_S3C_DEV_FB
@@ -190,151 +172,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
 }
 #endif /* CONFIG_S3C_DEV_FB */
 
-/* FIMC */
-
-#ifdef CONFIG_S5P_DEV_FIMC0
-static struct resource s5p_fimc0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
-};
-
-struct platform_device s5p_device_fimc0 = {
-        .name           = "s5p-fimc",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p_fimc0_resource),
-        .resource       = s5p_fimc0_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device s5p_device_fimc_md = {
-        .name   = "s5p-fimc-md",
-        .id     = -1,
-};
-#endif /* CONFIG_S5P_DEV_FIMC0 */
-
-#ifdef CONFIG_S5P_DEV_FIMC1
-static struct resource s5p_fimc1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
-};
-
-struct platform_device s5p_device_fimc1 = {
-        .name           = "s5p-fimc",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p_fimc1_resource),
-        .resource       = s5p_fimc1_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /* CONFIG_S5P_DEV_FIMC1 */
-
-#ifdef CONFIG_S5P_DEV_FIMC2
-static struct resource s5p_fimc2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
-};
-
-struct platform_device s5p_device_fimc2 = {
-        .name           = "s5p-fimc",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(s5p_fimc2_resource),
-        .resource       = s5p_fimc2_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /* CONFIG_S5P_DEV_FIMC2 */
-
-#ifdef CONFIG_S5P_DEV_FIMC3
-static struct resource s5p_fimc3_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
-};
-
-struct platform_device s5p_device_fimc3 = {
-        .name           = "s5p-fimc",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(s5p_fimc3_resource),
-        .resource       = s5p_fimc3_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /* CONFIG_S5P_DEV_FIMC3 */
-
-/* G2D */
-
-#ifdef CONFIG_S5P_DEV_G2D
-static struct resource s5p_g2d_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_2D),
-};
-
-struct platform_device s5p_device_g2d = {
-        .name           = "s5p-g2d",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p_g2d_resource),
-        .resource       = s5p_g2d_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /* CONFIG_S5P_DEV_G2D */
-
-#ifdef CONFIG_S5P_DEV_JPEG
-static struct resource s5p_jpeg_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_JPEG),
-};
-
-struct platform_device s5p_device_jpeg = {
-        .name           = "s5p-jpeg",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p_jpeg_resource),
-        .resource       = s5p_jpeg_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /*  CONFIG_S5P_DEV_JPEG */
-
-/* FIMD0 */
-
-#ifdef CONFIG_S5P_DEV_FIMD0
-static struct resource s5p_fimd0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
-        [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
-        [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
-        [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
-};
-
-struct platform_device s5p_device_fimd0 = {
-        .name           = "s5p-fb",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p_fimd0_resource),
-        .resource       = s5p_fimd0_resource,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
-{
-        s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
-                         &s5p_device_fimd0);
-}
-#endif /* CONFIG_S5P_DEV_FIMD0 */
-
 /* HWMON */
 
 #ifdef CONFIG_S3C_DEV_HWMON
@@ -722,60 +559,6 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
 }
 #endif /* CONFIG_S3C_DEV_I2C7 */
 
-/* I2C HDMIPHY */
-
-#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
-static struct resource s5p_i2c_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
-        [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
-};
-
-struct platform_device s5p_device_i2c_hdmiphy = {
-        .name           = "s3c2440-hdmiphy-i2c",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_i2c_resource),
-        .resource       = s5p_i2c_resource,
-};
-
-void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
-{
-        struct s3c2410_platform_i2c *npd;
-
-        if (!pd) {
-                pd = &default_i2c_data;
-
-                if (soc_is_s5pv210())
-                        pd->bus_num = 3;
-                else
-                        pd->bus_num = 0;
-        }
-
-        npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
-                               &s5p_device_i2c_hdmiphy);
-}
-
-static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
-
-void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
-                                  struct i2c_board_info *mhl_info, int mhl_bus)
-{
-        struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
-
-        if (soc_is_s5pv210())
-                pd->hdmiphy_bus = 3;
-        else
-                pd->hdmiphy_bus = 0;
-
-        pd->hdmiphy_info = hdmiphy_info;
-        pd->mhl_info = mhl_info;
-        pd->mhl_bus = mhl_bus;
-
-        s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
-                         &s5p_device_hdmi);
-}
-
-#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
-
 /* I2S */
 
 #ifdef CONFIG_PLAT_S3C24XX
@@ -879,36 +662,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
 }
 #endif /* CONFIG_PLAT_S3C24XX */
 
-/* MIPI CSIS */
-
-#ifdef CONFIG_S5P_DEV_CSIS0
-static struct resource s5p_mipi_csis0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
-        [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
-};
-
-struct platform_device s5p_device_mipi_csis0 = {
-        .name           = "s5p-mipi-csis",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p_mipi_csis0_resource),
-        .resource       = s5p_mipi_csis0_resource,
-};
-#endif /* CONFIG_S5P_DEV_CSIS0 */
-
-#ifdef CONFIG_S5P_DEV_CSIS1
-static struct resource s5p_mipi_csis1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
-        [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
-};
-
-struct platform_device s5p_device_mipi_csis1 = {
-        .name           = "s5p-mipi-csis",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p_mipi_csis1_resource),
-        .resource       = s5p_mipi_csis1_resource,
-};
-#endif
-
 /* NAND */
 
 #ifdef CONFIG_S3C_DEV_NAND
@@ -1052,43 +805,6 @@ void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
 }
 #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
 
-#ifdef CONFIG_S5P_DEV_ONENAND
-static struct resource s5p_onenand_resources[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
-        [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
-        [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
-};
-
-struct platform_device s5p_device_onenand = {
-        .name           = "s5pc110-onenand",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_onenand_resources),
-        .resource       = s5p_onenand_resources,
-};
-#endif /* CONFIG_S5P_DEV_ONENAND */
-
-/* PMU */
-
-#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
-static struct resource s5p_pmu_resource[] = {
-        DEFINE_RES_IRQ(IRQ_PMU)
-};
-
-static struct platform_device s5p_device_pmu = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
-        .resource       = s5p_pmu_resource,
-};
-
-static int __init s5p_pmu_init(void)
-{
-        platform_device_register(&s5p_device_pmu);
-        return 0;
-}
-arch_initcall(s5p_pmu_init);
-#endif /* CONFIG_PLAT_S5P */
-
 /* PWM Timer */
 
 #ifdef CONFIG_SAMSUNG_DEV_PWM
@@ -1251,52 +967,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 }
 #endif /* CONFIG_SAMSUNG_DEV_TS */
 
-/* TV */
-
-#ifdef CONFIG_S5P_DEV_TV
-
-static struct resource s5p_hdmi_resources[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
-        [1] = DEFINE_RES_IRQ(IRQ_HDMI),
-};
-
-struct platform_device s5p_device_hdmi = {
-        .name           = "s5p-hdmi",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_hdmi_resources),
-        .resource       = s5p_hdmi_resources,
-};
-
-static struct resource s5p_sdo_resources[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
-        [1] = DEFINE_RES_IRQ(IRQ_SDO),
-};
-
-struct platform_device s5p_device_sdo = {
-        .name           = "s5p-sdo",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_sdo_resources),
-        .resource       = s5p_sdo_resources,
-};
-
-static struct resource s5p_mixer_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
-        [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
-        [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
-};
-
-struct platform_device s5p_device_mixer = {
-        .name           = "s5p-mixer",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_mixer_resources),
-        .resource       = s5p_mixer_resources,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-#endif /* CONFIG_S5P_DEV_TV */
-
 /* USB */
 
 #ifdef CONFIG_S3C_DEV_USB_HOST
diff --git a/arch/arm/plat-samsung/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
deleted file mode 100644
index a5708bf84b3a..000000000000
--- a/arch/arm/plat-samsung/include/plat/camport.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * S5P series camera interface helper functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PLAT_SAMSUNG_CAMPORT_H_
-#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
-
-enum s5p_camport_id {
-        S5P_CAMPORT_A,
-        S5P_CAMPORT_B,
-};
-
-/*
- * The helper functions to configure GPIO for the camera parallel bus.
- * The camera port can be multiplexed with any FIMC entity, even multiple
- * FIMC entities are allowed to be attached to a single port simultaneously.
- * These functions are to be used in the board setup code.
- */
-int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
-int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
-
-#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
deleted file mode 100644
index 50a8ca7c3760..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
- *
- * Parts taken from arch/arm/plat-s3c64xx/clock.c
- *      Copyright 2008 Openmoko, Inc.
- *      Copyright 2008 Simtec Electronics
- *              Ben Dooks <ben@simtec.co.uk>
- *              http://armlinux.simtec.co.uk/
- *
- * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
- * Copyright 2009 Harald Welte
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/**
- * struct clksrc_sources - list of sources for a given clock
- * @sources: array of pointers to clocks
- * @nr_sources: The size of @sources
- */
-struct clksrc_sources {
-        unsigned int    nr_sources;
-        struct clk      **sources;
-};
-
-/**
- * struct clksrc_reg - register definition for clock control bits
- * @reg: pointer to the register in virtual memory.
- * @shift: the shift in bits to where the bitfield is.
- * @size: the size in bits of the bitfield.
- *
- * This specifies the size and position of the bits we are interested
- * in within the register specified by @reg.
- */
-struct clksrc_reg {
-        void __iomem            *reg;
-        unsigned short          shift;
-        unsigned short          size;
-};
-
-/**
- * struct clksrc_clk - class of clock for newer style samsung devices.
- * @clk: the standard clock representation
- * @sources: the sources for this clock
- * @reg_src: the register definition for selecting the clock's source
- * @reg_div: the register definition for the clock's output divisor
- *
- * This clock implements the features required by the newer SoCs where
- * the standard clock block provides an input mux and a post-mux divisor
- * to provide the periperhal's clock.
- *
- * The array of @sources provides the mapping of mux position to the
- * clock, and @reg_src shows the code where to modify to change the mux
- * position. The @reg_div defines how to change the divider settings on
- * the output.
- */
-struct clksrc_clk {
-        struct clk              clk;
-        struct clksrc_sources   *sources;
-
-        struct clksrc_reg       reg_src;
-        struct clksrc_reg       reg_div;
-};
-
-/**
- * s3c_set_clksrc() - setup the clock from the register settings
- * @clk: The clock to setup.
- * @announce: true to announce the setting to printk().
- *
- * Setup the clock from the current register settings, for when the
- * kernel boots or if it is resuming from a possibly unknown state.
- */
-extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
-
-/**
- * s3c_register_clksrc() register clocks from an array of clksrc clocks
- * @srcs: The array of clocks to register
- * @size: The size of the @srcs array.
- *
- * Initialise and register the array of clocks described by @srcs.
- */
-extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
deleted file mode 100644
index 63239f409807..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* linux/arch/arm/plat-s3c/include/plat/clock.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/SWLINUX/
- *      Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_CLOCK_H
-#define __ASM_PLAT_CLOCK_H __FILE__
-
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-
-struct clk;
-
-/**
- * struct clk_ops - standard clock operations
- * @set_rate: set the clock rate, see clk_set_rate().
- * @get_rate: get the clock rate, see clk_get_rate().
- * @round_rate: round a given clock rate, see clk_round_rate().
- * @set_parent: set the clock's parent, see clk_set_parent().
- *
- * Group the common clock implementations together so that we
- * don't have to keep setting the same fields again. We leave
- * enable in struct clk.
- *
- * Adding an extra layer of indirection into the process should
- * not be a problem as it is unlikely these operations are going
- * to need to be called quickly.
- */
-struct clk_ops {
-        int                 (*set_rate)(struct clk *c, unsigned long rate);
-        unsigned long       (*get_rate)(struct clk *c);
-        unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
-        int                 (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-struct clk {
-        struct list_head      list;
-        struct module        *owner;
-        struct clk           *parent;
-        const char           *name;
-        const char              *devname;
-        int                   id;
-        int                   usage;
-        unsigned long         rate;
-        unsigned long         ctrlbit;
-
-        struct clk_ops          *ops;
-        int                 (*enable)(struct clk *, int enable);
-        struct clk_lookup       lookup;
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;  /* For visible tree hierarchy */
-#endif
-};
-
-/* other clocks which may be registered by board support */
-
-extern struct clk s3c24xx_dclk0;
-extern struct clk s3c24xx_dclk1;
-extern struct clk s3c24xx_clkout0;
-extern struct clk s3c24xx_clkout1;
-extern struct clk s3c24xx_uclk;
-
-extern struct clk clk_usb_bus;
-
-/* core clock support */
-
-extern struct clk clk_f;
-extern struct clk clk_h;
-extern struct clk clk_p;
-extern struct clk clk_mpll;
-extern struct clk clk_upll;
-extern struct clk clk_epll;
-extern struct clk clk_xtal;
-extern struct clk clk_ext;
-
-/* S3C2443/S3C2416 specific clocks */
-extern struct clksrc_clk clk_epllref;
-extern struct clksrc_clk clk_esysclk;
-
-/* S3C24XX UART clocks */
-extern struct clk s3c24xx_clk_uart0;
-extern struct clk s3c24xx_clk_uart1;
-extern struct clk s3c24xx_clk_uart2;
-
-/* S3C64XX specific clocks */
-extern struct clk clk_h2;
-extern struct clk clk_27m;
-extern struct clk clk_48m;
-extern struct clk clk_xusbxti;
-
-extern int clk_default_setrate(struct clk *clk, unsigned long rate);
-extern struct clk_ops clk_ops_def_setrate;
-
-/* exports for arch/arm/mach-s3c2410
- *
- * Please DO NOT use these outside of arch/arm/mach-s3c2410
-*/
-
-extern spinlock_t clocks_lock;
-
-extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
-
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
-
-extern void s3c_register_clocks(struct clk *clk, int nr_clks);
-extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
-
-extern int s3c24xx_register_baseclocks(unsigned long xtal);
-
-extern void s5p_register_clocks(unsigned long xtal_freq);
-
-extern void s3c24xx_setup_clocks(unsigned long fclk,
-                                 unsigned long hclk,
-                                 unsigned long pclk);
-
-extern void s3c2410_setup_clocks(void);
-extern void s3c2412_setup_clocks(void);
-extern void s3c244x_setup_clocks(void);
-
-/* S3C2410 specific clock functions */
-
-extern int s3c2410_baseclk_add(void);
-
-/* S3C2443/S3C2416 specific clock functions */
-
-typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
-
-extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
-extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-                                       unsigned int *divs, int nr_divs,
-                                       int divmask);
-
-extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
-
-/* S3C64XX specific functions and clocks */
-
-extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
-
-/* Global watchdog clock used by arch_wtd_reset() callback */
-
-extern struct clk *s3c2410_wdtclk;
-
-#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 72d4178ad23b..317c52303288 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -140,7 +140,6 @@ struct s3c_cpufreq_config {
  *      any frequency changes. This is really only need by devices like the
  *      S3C2410 where there is no or limited divider between the PLL and the
  *      ARMCLK.
- * @resume_clocks: Update the clocks on resume.
  * @get_iotiming: Get the current IO timing data, mainly for use at start.
  * @set_iotiming: Update the IO timings from the cached copies calculated
  *      from the @calc_iotiming entry when changing the frequency.
@@ -169,8 +168,6 @@ struct s3c_cpufreq_info {
 
         /* driver routines */
 
-        void            (*resume_clocks)(void);
-
         int             (*get_iotiming)(struct s3c_cpufreq_config *cfg,
                                         struct s3c_iotimings *timings);
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d1d4659025bb..61d14f3a0426 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -47,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -76,12 +75,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 # define soc_is_s3c64xx()       0
 #endif
 
-#if defined(CONFIG_CPU_S5PV210)
-# define soc_is_s5pv210()       is_samsung_s5pv210()
-#else
-# define soc_is_s5pv210()       0
-#endif
-
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef KHZ
@@ -117,12 +110,9 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s5p_init_irq(u32 *vic, u32 num_vic);
-
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
 
 extern void s3c64xx_init_cpu(void);
-extern void s5p_init_cpu(void __iomem *cpuid_addr);
 
 extern unsigned int samsung_rev(void);
 
@@ -149,8 +139,5 @@ extern struct bus_type s3c2440_subsys;
 extern struct bus_type s3c2442_subsys;
 extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
-extern struct bus_type s5pv210_subsys;
-
-extern void (*s5pc1xx_idle)(void);
 
 #endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5f5a28d08c2e..e23fed311e5f 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -25,9 +25,6 @@ struct s3c24xx_uart_resources {
 
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
-extern struct s3c24xx_uart_resources s5p_uart_resources[];
-extern struct s3c24xx_uart_resources exynos4_uart_resources[];
-extern struct s3c24xx_uart_resources exynos5_uart_resources[];
 
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
@@ -75,45 +72,6 @@ extern struct platform_device s3c_device_usb_hsotg;
 extern struct platform_device s3c_device_usb_hsudc;
 extern struct platform_device s3c_device_wdt;
 
-extern struct platform_device s5p_device_fimc0;
-extern struct platform_device s5p_device_fimc1;
-extern struct platform_device s5p_device_fimc2;
-extern struct platform_device s5p_device_fimc3;
-extern struct platform_device s5p_device_fimc_md;
-extern struct platform_device s5p_device_jpeg;
-extern struct platform_device s5p_device_g2d;
-extern struct platform_device s5p_device_fimd0;
-extern struct platform_device s5p_device_hdmi;
-extern struct platform_device s5p_device_i2c_hdmiphy;
-extern struct platform_device s5p_device_mfc;
-extern struct platform_device s5p_device_mfc_l;
-extern struct platform_device s5p_device_mfc_r;
-extern struct platform_device s5p_device_mipi_csis0;
-extern struct platform_device s5p_device_mipi_csis1;
-extern struct platform_device s5p_device_mixer;
-extern struct platform_device s5p_device_onenand;
-extern struct platform_device s5p_device_sdo;
-
-extern struct platform_device s5pv210_device_ac97;
-extern struct platform_device s5pv210_device_iis0;
-extern struct platform_device s5pv210_device_iis1;
-extern struct platform_device s5pv210_device_iis2;
-extern struct platform_device s5pv210_device_pcm0;
-extern struct platform_device s5pv210_device_pcm1;
-extern struct platform_device s5pv210_device_pcm2;
-extern struct platform_device s5pv210_device_spdif;
-
-extern struct platform_device exynos4_device_ac97;
-extern struct platform_device exynos4_device_ahci;
-extern struct platform_device exynos4_device_i2s0;
-extern struct platform_device exynos4_device_i2s1;
-extern struct platform_device exynos4_device_i2s2;
-extern struct platform_device exynos4_device_ohci;
-extern struct platform_device exynos4_device_pcm0;
-extern struct platform_device exynos4_device_pcm1;
-extern struct platform_device exynos4_device_pcm2;
-extern struct platform_device exynos4_device_spdif;
-
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
 extern struct platform_device samsung_device_pwm;
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index 6abcbf139cee..bca383efcf6d 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,19 +26,4 @@ static inline void s3c_fb_setname(char *name)
 #endif
 }
 
-/* Re-define device name depending on support. */
-static inline void s5p_fb_setname(int id, char *name)
-{
-        switch (id) {
-#ifdef CONFIG_S5P_DEV_FIMD0
-        case 0:
-                s5p_device_fimd0.name = name;
-        break;
-#endif
-        default:
-                printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
-        break;
-        }
-}
-
 #endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 5a0e26afb961..b89f8f208515 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -26,32 +26,10 @@
 extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
 
 /**
- * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
- * @pd: The platform data to set. The data is copied from the passed structure
- *      so the machine data can mark the data __initdata so that any unused
- *      machines will end up dumping their data at runtime.
- */
-extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
-
-/**
  * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
  *
  * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
  */
 extern void s3c64xx_fb_gpio_setup_24bpp(void);
 
-/**
- * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
- *
- * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
- */
-extern void s5pv210_fb_gpio_setup_24bpp(void);
-
-/**
- * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
- *
- * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
- */
-extern void exynos4_fimd0_gpio_setup_24bpp(void);
-
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
deleted file mode 100644
index 1d6cb2b8b094..000000000000
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * arch/arm/plat-samsung/include/plat/fimc-core.h
- *
- * Copyright 2010 Samsung Electronics Co., Ltd.
- *      Sylwester Nawrocki <s.nawrocki@samsung.com>
- *
- * Samsung camera interface driver core functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_PLAT_FIMC_CORE_H
-#define __ASM_PLAT_FIMC_CORE_H __FILE__
-
-/*
- * These functions are only for use with the core support code, such as
- * the CPU-specific initialization code.
- */
-
-/* Re-define device name to differentiate the subsystem in various SoCs. */
-static inline void s3c_fimc_setname(int id, char *name)
-{
-        switch (id) {
-#ifdef CONFIG_S5P_DEV_FIMC0
-        case 0:
-                s5p_device_fimc0.name = name;
-                break;
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC1
-        case 1:
-                s5p_device_fimc1.name = name;
-                break;
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC2
-        case 2:
-                s5p_device_fimc2.name = name;
-                break;
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC3
-        case 3:
-                s5p_device_fimc3.name = name;
-                break;
-#endif
-        default:
-                break;
-        }
-}
-
-#endif /* __ASM_PLAT_FIMC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 08740eed050c..b5294eff18b5 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -27,7 +27,6 @@
 #include <linux/types.h>
 
 typedef unsigned int __bitwise__ samsung_gpio_pull_t;
-typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
 
 /* forward declaration if gpio-core.h hasn't been included */
 struct samsung_gpio_chip;
@@ -180,67 +179,4 @@ static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
         return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
 }
 
-/* Define values for the drvstr available for each gpio pin.
- *
- * These values control the value of the output signal driver strength,
- * configurable on most pins on the S5P series.
- */
-#define S5P_GPIO_DRVSTR_LV1     ((__force s5p_gpio_drvstr_t)0x0)
-#define S5P_GPIO_DRVSTR_LV2     ((__force s5p_gpio_drvstr_t)0x2)
-#define S5P_GPIO_DRVSTR_LV3     ((__force s5p_gpio_drvstr_t)0x1)
-#define S5P_GPIO_DRVSTR_LV4     ((__force s5p_gpio_drvstr_t)0x3)
-
-/**
- * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
- * @pin: The pin number to get the settings for
- *
- * Read the driver streght value for the specified pin.
-*/
-extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
-
-/**
- * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
- * @pin: The pin number to configure the driver streght value
- * @drvstr: The new value of the driver strength
- *
- * This function sets the driver strength value for the specified pin.
- * It will return 0 if successful, or a negative error code if the pin
- * cannot support the requested setting.
-*/
-extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
-
-/**
- * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
- * @pin: The pin number from the group to be registered
- *
- * This function registers gpio interrupt support for the group that the
- * specified pin belongs to.
- *
- * The total number of gpio pins is quite large ob s5p series. Registering
- * irq support for all of them would be a resource waste. Because of that the
- * interrupt support for standard gpio pins is registered dynamically.
- *
- * It will return the irq number of the interrupt that has been registered
- * or -ENOMEM if no more gpio interrupts can be registered. It is allowed
- * to call this function more than once for the same gpio group (the group
- * will be registered only once).
- */
-extern int s5p_register_gpio_interrupt(int pin);
-
-/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
- * registration (see s5p_register_gpio_interrupt function)
- * @chain_irq: chained irq number for the gpio int handler for this bank
- * @start: start gpio group number of this bank
- * @nr_groups: number of gpio groups handled by this bank
- *
- * This functions registers initial information about gpio banks that
- * can be later used by the s5p_register_gpio_interrupt() function to
- * enable support for gpio interrupt for particular gpio group.
- */
-#ifdef CONFIG_S5P_GPIO_INT
-extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
-#else
-#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
-#endif
-
 #endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h
deleted file mode 100644
index 331d046ac2c5..000000000000
--- a/arch/arm/plat-samsung/include/plat/hdmi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_SAMSUNG_HDMI_H
-#define __PLAT_SAMSUNG_HDMI_H __FILE__
-
-extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
-                                  struct i2c_board_info *mhl_info, int mhl_bus);
-
-#endif /* __PLAT_SAMSUNG_HDMI_H */
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
deleted file mode 100644
index 039001c0ef05..000000000000
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/irqs.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P Common IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_IRQS_H
-#define __PLAT_SAMSUNG_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- *
- * note, since we're using the VICs, our start must be a
- * mulitple of 32 to allow the common code to work
- */
-
-#define S5P_IRQ_OFFSET          (32)
-
-#define S5P_IRQ(x)              ((x) + S5P_IRQ_OFFSET)
-
-#define S5P_VIC0_BASE           S5P_IRQ(0)
-#define S5P_VIC1_BASE           S5P_IRQ(32)
-#define S5P_VIC2_BASE           S5P_IRQ(64)
-#define S5P_VIC3_BASE           S5P_IRQ(96)
-
-#define VIC_BASE(x)             (S5P_VIC0_BASE + ((x)*32))
-
-#define IRQ_VIC0_BASE           S5P_VIC0_BASE
-#define IRQ_VIC1_BASE           S5P_VIC1_BASE
-#define IRQ_VIC2_BASE           S5P_VIC2_BASE
-
-/* VIC based IRQs */
-
-#define S5P_IRQ_VIC0(x)         (S5P_VIC0_BASE + (x))
-#define S5P_IRQ_VIC1(x)         (S5P_VIC1_BASE + (x))
-#define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
-#define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
-
-#define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
-                                        : ((x) - 16 + S5P_EINT_BASE2))
-
-#define EINT_OFFSET(irq)        ((irq) < S5P_EINT_BASE2 ? \
-                                                ((irq) - S5P_EINT_BASE1) : \
-                                                ((irq) + 16 - S5P_EINT_BASE2))
-
-#define IRQ_EINT_BIT(x)         EINT_OFFSET(x)
-
-/* Typically only a few gpio chips require gpio interrupt support.
-   To avoid memory waste irq descriptors are allocated only for
-   S5P_GPIOINT_GROUP_COUNT chips, each with total number of
-   S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
-   to any gpio chip with the s5p_register_gpio_interrupt() function */
-#define S5P_GPIOINT_GROUP_COUNT 4
-#define S5P_GPIOINT_GROUP_SIZE  8
-#define S5P_GPIOINT_COUNT       (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
-
-/* IRQ types common for all s5p platforms */
-#define S5P_IRQ_TYPE_LEVEL_LOW          (0x00)
-#define S5P_IRQ_TYPE_LEVEL_HIGH         (0x01)
-#define S5P_IRQ_TYPE_EDGE_FALLING       (0x02)
-#define S5P_IRQ_TYPE_EDGE_RISING        (0x03)
-#define S5P_IRQ_TYPE_EDGE_BOTH          (0x04)
-
-#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c18678610bc0..f5b9d3ff9cd4 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,7 +15,6 @@
 
 #define S5P_VA_CHIPID           S3C_ADDR(0x02000000)
 #define S5P_VA_CMU              S3C_ADDR(0x02100000)
-#define S5P_VA_PMU              S3C_ADDR(0x02180000)
 #define S5P_VA_GPIO             S3C_ADDR(0x02200000)
 #define S5P_VA_GPIO1            S5P_VA_GPIO
 #define S5P_VA_GPIO2            S3C_ADDR(0x02240000)
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
deleted file mode 100644
index 033654e91e22..000000000000
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_SAMSUNG_MFC_H
-#define __PLAT_SAMSUNG_MFC_H __FILE__
-
-struct s5p_mfc_dt_meminfo {
-        unsigned long   loff;
-        unsigned long   lsize;
-        unsigned long   roff;
-        unsigned long   rsize;
-        char            *compatible;
-};
-
-/**
- * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
- * @rbase:      base address for MFC 'right' memory interface
- * @rsize:      size of the memory reserved for MFC 'right' interface
- * @lbase:      base address for MFC 'left' memory interface
- * @lsize:      size of the memory reserved for MFC 'left' interface
- *
- * This function reserves system memory for both MFC device memory
- * interfaces and registers it to respective struct device entries as
- * coherent memory.
- */
-void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
-                                phys_addr_t lbase, unsigned int lsize);
-
-#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
deleted file mode 100644
index 357af7c1c664..000000000000
--- a/arch/arm/plat-samsung/include/plat/pll.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/pll.h
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * Samsung PLL codes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/div64.h>
-
-#define S3C24XX_PLL_MDIV_MASK           (0xFF)
-#define S3C24XX_PLL_PDIV_MASK           (0x1F)
-#define S3C24XX_PLL_SDIV_MASK           (0x3)
-#define S3C24XX_PLL_MDIV_SHIFT          (12)
-#define S3C24XX_PLL_PDIV_SHIFT          (4)
-#define S3C24XX_PLL_SDIV_SHIFT          (0)
-
-static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
-                                           unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
-        pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
-        sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#define S3C2416_PLL_MDIV_MASK           (0x3FF)
-#define S3C2416_PLL_PDIV_MASK           (0x3F)
-#define S3C2416_PLL_SDIV_MASK           (0x7)
-#define S3C2416_PLL_MDIV_SHIFT          (14)
-#define S3C2416_PLL_PDIV_SHIFT          (5)
-#define S3C2416_PLL_SDIV_SHIFT          (0)
-
-static inline unsigned int s3c2416_get_pll(unsigned int pllval,
-                                           unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
-        pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
-        sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
-
-        fvco = (uint64_t)baseclk * mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned int)fvco;
-}
-
-#define S3C6400_PLL_MDIV_MASK           (0x3FF)
-#define S3C6400_PLL_PDIV_MASK           (0x3F)
-#define S3C6400_PLL_SDIV_MASK           (0x7)
-#define S3C6400_PLL_MDIV_SHIFT          (16)
-#define S3C6400_PLL_PDIV_SHIFT          (8)
-#define S3C6400_PLL_SDIV_SHIFT          (0)
-
-static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
-                                            u32 pllcon)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
-        pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
-        sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
-
-#define PLL6553X_MDIV_MASK      (0x7F)
-#define PLL6553X_PDIV_MASK      (0x1F)
-#define PLL6553X_SDIV_MASK      (0x3)
-#define PLL6553X_KDIV_MASK      (0xFFFF)
-#define PLL6553X_MDIV_SHIFT     (16)
-#define PLL6553X_PDIV_SHIFT     (8)
-#define PLL6553X_SDIV_SHIFT     (0)
-
-static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
-                                             u32 pll_con0, u32 pll_con1)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
-        pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
-        sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
-        kdiv = pll_con1 & PLL6553X_KDIV_MASK;
-
-        /*
-         * We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
-}
-
-#define PLL35XX_MDIV_MASK       (0x3FF)
-#define PLL35XX_PDIV_MASK       (0x3F)
-#define PLL35XX_SDIV_MASK       (0x7)
-#define PLL35XX_MDIV_SHIFT      (16)
-#define PLL35XX_PDIV_SHIFT      (8)
-#define PLL35XX_SDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
-
-#define PLL36XX_KDIV_MASK       (0xFFFF)
-#define PLL36XX_MDIV_MASK       (0x1FF)
-#define PLL36XX_PDIV_MASK       (0x3F)
-#define PLL36XX_SDIV_MASK       (0x7)
-#define PLL36XX_MDIV_SHIFT      (16)
-#define PLL36XX_PDIV_SHIFT      (8)
-#define PLL36XX_SDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
-                                            u32 pll_con0, u32 pll_con1)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
-        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
-        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
-        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
-
-        tmp = baseclk;
-
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
-}
-
-#define PLL45XX_MDIV_MASK       (0x3FF)
-#define PLL45XX_PDIV_MASK       (0x3F)
-#define PLL45XX_SDIV_MASK       (0x7)
-#define PLL45XX_MDIV_SHIFT      (16)
-#define PLL45XX_PDIV_SHIFT      (8)
-#define PLL45XX_SDIV_SHIFT      (0)
-
-enum pll45xx_type_t {
-        pll_4500,
-        pll_4502,
-        pll_4508
-};
-
-static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
-                                            enum pll45xx_type_t pll_type)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
-
-        if (pll_type == pll_4508)
-                sdiv = sdiv - 1;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
-
-/* CON0 bit-fields */
-#define PLL46XX_MDIV_MASK       (0x1FF)
-#define PLL46XX_PDIV_MASK       (0x3F)
-#define PLL46XX_SDIV_MASK       (0x7)
-#define PLL46XX_LOCKED_SHIFT    (29)
-#define PLL46XX_MDIV_SHIFT      (16)
-#define PLL46XX_PDIV_SHIFT      (8)
-#define PLL46XX_SDIV_SHIFT      (0)
-
-/* CON1 bit-fields */
-#define PLL46XX_MRR_MASK        (0x1F)
-#define PLL46XX_MFR_MASK        (0x3F)
-#define PLL46XX_KDIV_MASK       (0xFFFF)
-#define PLL4650C_KDIV_MASK      (0xFFF)
-#define PLL46XX_MRR_SHIFT       (24)
-#define PLL46XX_MFR_SHIFT       (16)
-#define PLL46XX_KDIV_SHIFT      (0)
-
-enum pll46xx_type_t {
-        pll_4600,
-        pll_4650,
-        pll_4650c,
-};
-
-static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
-                                            u32 pll_con0, u32 pll_con1,
-                                            enum pll46xx_type_t pll_type)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
-        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
-        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
-        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
-        if (pll_type == pll_4650c)
-                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
-        else
-                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
-        tmp = baseclk;
-
-        if (pll_type == pll_4600) {
-                tmp *= (mdiv << 16) + kdiv;
-                do_div(tmp, (pdiv << sdiv));
-                result = tmp >> 16;
-        } else {
-                tmp *= (mdiv << 10) + kdiv;
-                do_div(tmp, (pdiv << sdiv));
-                result = tmp >> 10;
-        }
-
-        return result;
-}
-
-#define PLL90XX_MDIV_MASK       (0xFF)
-#define PLL90XX_PDIV_MASK       (0x3F)
-#define PLL90XX_SDIV_MASK       (0x7)
-#define PLL90XX_KDIV_MASK       (0xffff)
-#define PLL90XX_LOCKED_SHIFT    (29)
-#define PLL90XX_MDIV_SHIFT      (16)
-#define PLL90XX_PDIV_SHIFT      (8)
-#define PLL90XX_SDIV_SHIFT      (0)
-#define PLL90XX_KDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
-                                            u32 pll_con, u32 pll_conk)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
-        kdiv = pll_conk & PLL90XX_KDIV_MASK;
-
-        /*
-         * We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
-}
-
-#define PLL65XX_MDIV_MASK       (0x3FF)
-#define PLL65XX_PDIV_MASK       (0x3F)
-#define PLL65XX_SDIV_MASK       (0x7)
-#define PLL65XX_MDIV_SHIFT      (16)
-#define PLL65XX_PDIV_SHIFT      (8)
-#define PLL65XX_SDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
deleted file mode 100644
index acacc4b88a39..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for s5p clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_CLOCK_H
-#define __ASM_PLAT_S5P_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
-
-#define clk_fin_apll clk_ext_xtal_mux
-#define clk_fin_bpll clk_ext_xtal_mux
-#define clk_fin_cpll clk_ext_xtal_mux
-#define clk_fin_mpll clk_ext_xtal_mux
-#define clk_fin_epll clk_ext_xtal_mux
-#define clk_fin_dpll clk_ext_xtal_mux
-#define clk_fin_vpll clk_ext_xtal_mux
-#define clk_fin_hpll clk_ext_xtal_mux
-
-extern struct clk clk_ext_xtal_mux;
-extern struct clk clk_xusbxti;
-extern struct clk clk_48m;
-extern struct clk s5p_clk_27m;
-extern struct clk clk_fout_apll;
-extern struct clk clk_fout_bpll;
-extern struct clk clk_fout_bpll_div2;
-extern struct clk clk_fout_cpll;
-extern struct clk clk_fout_mpll;
-extern struct clk clk_fout_mpll_div2;
-extern struct clk clk_fout_epll;
-extern struct clk clk_fout_dpll;
-extern struct clk clk_fout_vpll;
-extern struct clk clk_arm;
-extern struct clk clk_vpll;
-
-extern struct clksrc_sources clk_src_apll;
-extern struct clksrc_sources clk_src_bpll;
-extern struct clksrc_sources clk_src_bpll_fout;
-extern struct clksrc_sources clk_src_cpll;
-extern struct clksrc_sources clk_src_mpll;
-extern struct clksrc_sources clk_src_mpll_fout;
-extern struct clksrc_sources clk_src_epll;
-extern struct clksrc_sources clk_src_dpll;
-
-extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
-
-/* Common EPLL operations for S5P platform */
-extern int s5p_epll_enable(struct clk *clk, int enable);
-extern unsigned long s5p_epll_get_rate(struct clk *clk);
-
-/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
-extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
-extern unsigned long s5p_spdif_get_rate(struct clk *clk);
-
-extern struct clk_ops s5p_sclk_spdif_ops;
-#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f84b6cbc8745..2787553c3ae2 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -57,14 +57,6 @@ extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
-extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
-extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
-extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
-extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C2416 SDHCI setup */
 
@@ -144,45 +136,6 @@ static inline void s3c6400_default_sdhci2(void) { }
 
 #endif /* CONFIG_S3C64XX_SETUP_SDHCI */
 
-/* S5PV210 SDHCI setup */
-
-#ifdef CONFIG_S5PV210_SETUP_SDHCI
-static inline void s5pv210_default_sdhci0(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
-#endif
-}
-
-static inline void s5pv210_default_sdhci1(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
-#endif
-}
-
-static inline void s5pv210_default_sdhci2(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
-#endif
-}
-
-static inline void s5pv210_default_sdhci3(void)
-{
-#ifdef CONFIG_S3C_DEV_HSMMC3
-        s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
-#endif
-}
-
-#else
-static inline void s5pv210_default_sdhci0(void) { }
-static inline void s5pv210_default_sdhci1(void) { }
-static inline void s5pv210_default_sdhci2(void) { }
-static inline void s5pv210_default_sdhci3(void) { }
-
-#endif /* CONFIG_S5PV210_SETUP_SDHCI */
-
 static inline void s3c_sdhci_setname(int id, char *name)
 {
         switch (id) {
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
deleted file mode 100644
index 3bc34f3ce28f..000000000000
--- a/arch/arm/plat-samsung/include/plat/tv-core.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * arch/arm/plat-samsung/include/plat/tv.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *      Tomasz Stanislawski <t.stanislaws@samsung.com>
- *
- * Samsung TV driver core functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __SAMSUNG_PLAT_TV_H
-#define __SAMSUNG_PLAT_TV_H __FILE__
-
-/*
- * These functions are only for use with the core support code, such as
- * the CPU-specific initialization code.
- */
-
-/* Re-define device name to differentiate the subsystem in various SoCs. */
-static inline void s5p_hdmi_setname(char *name)
-{
-#ifdef CONFIG_S5P_DEV_TV
-        s5p_device_hdmi.name = name;
-#endif
-}
-
-static inline void s5p_mixer_setname(char *name)
-{
-#ifdef CONFIG_S5P_DEV_TV
-        s5p_device_mixer.name = name;
-#endif
-}
-
-static inline void s5p_sdo_setname(char *name)
-{
-#ifdef CONFIG_S5P_DEV_TV
-        s5p_device_sdo.name = name;
-#endif
-}
-
-#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index a1f925f3121f..11fbbc26e49f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -30,7 +30,6 @@
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
 
 static struct cpu_table *cpu;
 
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index adc91662f72b..f9a09262f2fa 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -194,7 +194,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
         .resume = samsung_gpio_pm_2bit_resume,
 };
 
-#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
+#if defined(CONFIG_ARCH_S3C64XX)
 static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -304,7 +304,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
         .save   = samsung_gpio_pm_4bit_save,
         .resume = samsung_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
+#endif /* CONFIG_ARCH_S3C64XX */
 
 /**
  * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
deleted file mode 100644
index 48a159911037..000000000000
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P - Common clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <asm/div64.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/s5p-clock.h>
-
-/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
- * clk_ext_xtal_mux.
-*/
-struct clk clk_ext_xtal_mux = {
-        .name           = "ext_xtal",
-        .id             = -1,
-};
-
-struct clk clk_xusbxti = {
-        .name           = "xusbxti",
-        .id             = -1,
-        .rate           = 24000000,
-};
-
-struct clk s5p_clk_27m = {
-        .name           = "clk_27m",
-        .id             = -1,
-        .rate           = 27000000,
-};
-
-/* 48MHz USB Phy clock output */
-struct clk clk_48m = {
-        .name           = "clk_48m",
-        .id             = -1,
-        .rate           = 48000000,
-};
-
-/* APLL clock output
- * No need .ctrlbit, this is always on
-*/
-struct clk clk_fout_apll = {
-        .name           = "fout_apll",
-        .id             = -1,
-};
-
-/* BPLL clock output */
-
-struct clk clk_fout_bpll = {
-        .name           = "fout_bpll",
-        .id             = -1,
-};
-
-struct clk clk_fout_bpll_div2 = {
-        .name           = "fout_bpll_div2",
-        .id             = -1,
-};
-
-/* CPLL clock output */
-
-struct clk clk_fout_cpll = {
-        .name           = "fout_cpll",
-        .id             = -1,
-};
-
-/* MPLL clock output
- * No need .ctrlbit, this is always on
-*/
-struct clk clk_fout_mpll = {
-        .name           = "fout_mpll",
-        .id             = -1,
-};
-
-struct clk clk_fout_mpll_div2 = {
-        .name           = "fout_mpll_div2",
-        .id             = -1,
-};
-
-/* EPLL clock output */
-struct clk clk_fout_epll = {
-        .name           = "fout_epll",
-        .id             = -1,
-        .ctrlbit        = (1 << 31),
-};
-
-/* DPLL clock output */
-struct clk clk_fout_dpll = {
-        .name           = "fout_dpll",
-        .id             = -1,
-        .ctrlbit        = (1 << 31),
-};
-
-/* VPLL clock output */
-struct clk clk_fout_vpll = {
-        .name           = "fout_vpll",
-        .id             = -1,
-        .ctrlbit        = (1 << 31),
-};
-
-/* Possible clock sources for APLL Mux */
-static struct clk *clk_src_apll_list[] = {
-        [0] = &clk_fin_apll,
-        [1] = &clk_fout_apll,
-};
-
-struct clksrc_sources clk_src_apll = {
-        .sources        = clk_src_apll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
-};
-
-/* Possible clock sources for BPLL Mux */
-static struct clk *clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &clk_fout_bpll,
-};
-
-struct clksrc_sources clk_src_bpll = {
-        .sources        = clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_bpll_list),
-};
-
-static struct clk *clk_src_bpll_fout_list[] = {
-        [0] = &clk_fout_bpll_div2,
-        [1] = &clk_fout_bpll,
-};
-
-struct clksrc_sources clk_src_bpll_fout = {
-        .sources        = clk_src_bpll_fout_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_bpll_fout_list),
-};
-
-/* Possible clock sources for CPLL Mux */
-static struct clk *clk_src_cpll_list[] = {
-        [0] = &clk_fin_cpll,
-        [1] = &clk_fout_cpll,
-};
-
-struct clksrc_sources clk_src_cpll = {
-        .sources        = clk_src_cpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_cpll_list),
-};
-
-/* Possible clock sources for MPLL Mux */
-static struct clk *clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &clk_fout_mpll,
-};
-
-struct clksrc_sources clk_src_mpll = {
-        .sources        = clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-};
-
-static struct clk *clk_src_mpll_fout_list[] = {
-        [0] = &clk_fout_mpll_div2,
-        [1] = &clk_fout_mpll,
-};
-
-struct clksrc_sources clk_src_mpll_fout = {
-        .sources        = clk_src_mpll_fout_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_fout_list),
-};
-
-/* Possible clock sources for EPLL Mux */
-static struct clk *clk_src_epll_list[] = {
-        [0] = &clk_fin_epll,
-        [1] = &clk_fout_epll,
-};
-
-struct clksrc_sources clk_src_epll = {
-        .sources        = clk_src_epll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
-};
-
-/* Possible clock sources for DPLL Mux */
-static struct clk *clk_src_dpll_list[] = {
-        [0] = &clk_fin_dpll,
-        [1] = &clk_fout_dpll,
-};
-
-struct clksrc_sources clk_src_dpll = {
-        .sources        = clk_src_dpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_dpll_list),
-};
-
-struct clk clk_vpll = {
-        .name           = "vpll",
-        .id             = -1,
-};
-
-int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        u32 con;
-
-        con = __raw_readl(reg);
-        con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
-        __raw_writel(con, reg);
-        return 0;
-}
-
-int s5p_epll_enable(struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
-        if (enable)
-                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
-        else
-                __raw_writel(epll_con, S5P_EPLL_CON);
-
-        return 0;
-}
-
-unsigned long s5p_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
-{
-        struct clk *pclk;
-        int ret;
-
-        pclk = clk_get_parent(clk);
-        if (IS_ERR(pclk))
-                return -EINVAL;
-
-        ret = pclk->ops->set_rate(pclk, rate);
-        clk_put(pclk);
-
-        return ret;
-}
-
-unsigned long s5p_spdif_get_rate(struct clk *clk)
-{
-        struct clk *pclk;
-        int rate;
-
-        pclk = clk_get_parent(clk);
-        if (IS_ERR(pclk))
-                return -EINVAL;
-
-        rate = pclk->ops->get_rate(pclk);
-        clk_put(pclk);
-
-        return rate;
-}
-
-struct clk_ops s5p_sclk_spdif_ops = {
-        .set_rate       = s5p_spdif_set_rate,
-        .get_rate       = s5p_spdif_get_rate,
-};
-
-static struct clk *s5p_clks[] __initdata = {
-        &clk_ext_xtal_mux,
-        &clk_48m,
-        &s5p_clk_27m,
-        &clk_fout_apll,
-        &clk_fout_mpll,
-        &clk_fout_epll,
-        &clk_fout_dpll,
-        &clk_fout_vpll,
-        &clk_vpll,
-        &clk_xusbxti,
-};
-
-void __init s5p_register_clocks(unsigned long xtal_freq)
-{
-        int ret;
-
-        clk_ext_xtal_mux.rate = xtal_freq;
-
-        ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register s5p clocks\n");
-}
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 469b86260fe3..0b04b6b0fa30 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,56 +17,16 @@
 #include <linux/of_fdt.h>
 #include <linux/of.h>
 
-#include <plat/mfc.h>
-
-#ifdef CONFIG_SAMSUNG_ATAGS
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <plat/devs.h>
-
-static struct resource s5p_mfc_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
-        [1] = DEFINE_RES_IRQ(IRQ_MFC),
-};
-
-struct platform_device s5p_device_mfc = {
-        .name           = "s5p-mfc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
-        .resource       = s5p_mfc_resource,
-};
-
-/*
- * MFC hardware has 2 memory interfaces which are modelled as two separate
- * platform devices to let dma-mapping distinguish between them.
- *
- * MFC parent device (s5p_device_mfc) must be registered before memory
- * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
- */
-
-struct platform_device s5p_device_mfc_l = {
-        .name           = "s5p-mfc-l",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &s5p_device_mfc_l.dev.coherent_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device s5p_device_mfc_r = {
-        .name           = "s5p-mfc-r",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &s5p_device_mfc_r.dev.coherent_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#else
 static struct platform_device s5p_device_mfc_l;
 static struct platform_device s5p_device_mfc_r;
-#endif
+
+struct s5p_mfc_dt_meminfo {
+        unsigned long   loff;
+        unsigned long   lsize;
+        unsigned long   roff;
+        unsigned long   rsize;
+        char            *compatible;
+};
 
 struct s5p_mfc_reserved_mem {
         phys_addr_t     base;
@@ -77,7 +37,7 @@ struct s5p_mfc_reserved_mem {
 static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
 
 
-void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                 phys_addr_t lbase, unsigned int lsize)
 {
         int i;
@@ -100,28 +60,6 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
         }
 }
 
-#ifdef CONFIG_SAMSUNG_ATAGS
-static int __init s5p_mfc_memory_init(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
-                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
-                if (!area->base)
-                        continue;
-
-                if (dma_declare_coherent_memory(area->dev, area->base,
-                                area->base, area->size,
-                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
-                        printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
-                               area->size, (unsigned long) area->base);
-        }
-        return 0;
-}
-device_initcall(s5p_mfc_memory_init);
-#endif
-
-#ifdef CONFIG_OF
 int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
                                 int depth, void *data)
 {
@@ -154,4 +92,3 @@ int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
 
         return 1;
 }
-#endif
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
deleted file mode 100644
index 8c4487af98c8..000000000000
--- a/arch/arm/plat-samsung/s5p-dev-uart.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Base S5P UART resource and device definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/map.h>
-
-#include <plat/devs.h>
-
- /* Serial port registrations */
-
-static struct resource s5p_uart0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART0),
-};
-
-static struct resource s5p_uart1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART1),
-};
-
-static struct resource s5p_uart2_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART2),
-};
-
-static struct resource s5p_uart3_resource[] = {
-#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
-        [0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART3),
-#endif
-};
-
-static struct resource s5p_uart4_resource[] = {
-#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
-        [0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART4),
-#endif
-};
-
-static struct resource s5p_uart5_resource[] = {
-#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
-        [0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
-        [1] = DEFINE_RES_IRQ(IRQ_UART5),
-#endif
-};
-
-struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = s5p_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart0_resource),
-        },
-        [1] = {
-                .resources      = s5p_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart1_resource),
-        },
-        [2] = {
-                .resources      = s5p_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart2_resource),
-        },
-        [3] = {
-                .resources      = s5p_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart3_resource),
-        },
-        [4] = {
-                .resources      = s5p_uart4_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart4_resource),
-        },
-        [5] = {
-                .resources      = s5p_uart5_resource,
-                .nr_resources   = ARRAY_SIZE(s5p_uart5_resource),
-        },
-};
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
deleted file mode 100644
index dcd8c2cbf5bb..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P - IRQ EINT support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/irqchip/arm-vic.h>
-#include <linux/of.h>
-
-#include <plat/regs-irqtype.h>
-
-#include <mach/map.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-
-#include <plat/gpio-cfg.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
-
-static inline void s5p_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask |= eint_irq_to_bit(data->irq);
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-}
-
-static void s5p_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask &= ~(eint_irq_to_bit(data->irq));
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-}
-
-static inline void s5p_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel(eint_irq_to_bit(data->irq),
-                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
-}
-
-static void s5p_irq_eint_maskack(struct irq_data *data)
-{
-        /* compiler should in-line these */
-        s5p_irq_eint_mask(data);
-        s5p_irq_eint_ack(data);
-}
-
-static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = EINT_OFFSET(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-
-        shift = (offs & 0x7) * 4;
-        mask = 0x7 << shift;
-
-        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
-
-        if ((0 <= offs) && (offs < 8))
-                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-
-        else if ((8 <= offs) && (offs < 16))
-                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-
-        else if ((16 <= offs) && (offs < 24))
-                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-
-        else if ((24 <= offs) && (offs < 32))
-                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-
-        else
-                printk(KERN_ERR "No such irq number %d", offs);
-
-        return 0;
-}
-
-static struct irq_chip s5p_irq_eint = {
-        .name           = "s5p-eint",
-        .irq_mask       = s5p_irq_eint_mask,
-        .irq_unmask     = s5p_irq_eint_unmask,
-        .irq_mask_ack   = s5p_irq_eint_maskack,
-        .irq_ack        = s5p_irq_eint_ack,
-        .irq_set_type   = s5p_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-
-/* s5p_irq_demux_eint
- *
- * This function demuxes the IRQ from the group0 external interrupts,
- * from EINTs 16 to 31. It is designed to be inlined into the specific
- * handler s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void s5p_irq_demux_eint(unsigned int start)
-{
-        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
-        unsigned int irq;
-
-        status &= ~mask;
-        status &= 0xff;
-
-        while (status) {
-                irq = fls(status) - 1;
-                generic_handle_irq(irq + start);
-                status &= ~(1 << irq);
-        }
-}
-
-static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        s5p_irq_demux_eint(IRQ_EINT(16));
-        s5p_irq_demux_eint(IRQ_EINT(24));
-}
-
-static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
-{
-        void __iomem *base = irq_data_get_irq_chip_data(data);
-
-        s5p_irq_eint_mask(data);
-        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
-}
-
-static void s5p_irq_vic_eint_unmask(struct irq_data *data)
-{
-        void __iomem *base = irq_data_get_irq_chip_data(data);
-
-        s5p_irq_eint_unmask(data);
-        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
-}
-
-static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
-{
-        __raw_writel(eint_irq_to_bit(data->irq),
-                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
-}
-
-static void s5p_irq_vic_eint_maskack(struct irq_data *data)
-{
-        s5p_irq_vic_eint_mask(data);
-        s5p_irq_vic_eint_ack(data);
-}
-
-static struct irq_chip s5p_irq_vic_eint = {
-        .name           = "s5p_vic_eint",
-        .irq_mask       = s5p_irq_vic_eint_mask,
-        .irq_unmask     = s5p_irq_vic_eint_unmask,
-        .irq_mask_ack   = s5p_irq_vic_eint_maskack,
-        .irq_ack        = s5p_irq_vic_eint_ack,
-        .irq_set_type   = s5p_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-
-static int __init s5p_init_irq_eint(void)
-{
-        int irq;
-
-        if (of_have_populated_dt())
-                return -ENODEV;
-
-        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
-                irq_set_chip(irq, &s5p_irq_vic_eint);
-
-        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
-                irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-
-        irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
-        return 0;
-}
-
-arch_initcall(s5p_init_irq_eint);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
deleted file mode 100644
index fafdb059043a..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * Author: Kyungmin Park <kyungmin.park@samsung.com>
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- * Author: Marek Szyprowski <m.szyprowski@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-
-#include <mach/map.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-
-#define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
-
-#define CON_OFFSET              0x700
-#define MASK_OFFSET             0x900
-#define PEND_OFFSET             0xA00
-#define REG_OFFSET(x)           ((x) << 2)
-
-struct s5p_gpioint_bank {
-        struct list_head        list;
-        int                     start;
-        int                     nr_groups;
-        int                     irq;
-        struct samsung_gpio_chip        **chips;
-        void                    (*handler)(unsigned int, struct irq_desc *);
-};
-
-static LIST_HEAD(banks);
-
-static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct irq_chip_type *ct = gc->chip_types;
-        unsigned int shift = (d->irq - gc->irq_base) << 2;
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                type = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                type = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                type = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                type = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                type = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-        case IRQ_TYPE_NONE:
-        default:
-                printk(KERN_WARNING "No irq type\n");
-                return -EINVAL;
-        }
-
-        gc->type_cache &= ~(0x7 << shift);
-        gc->type_cache |= type << shift;
-        writel(gc->type_cache, gc->reg_base + ct->regs.type);
-        return 0;
-}
-
-static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
-{
-        struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
-        int group, pend_offset, mask_offset;
-        unsigned int pend, mask;
-
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-
-        for (group = 0; group < bank->nr_groups; group++) {
-                struct samsung_gpio_chip *chip = bank->chips[group];
-                if (!chip)
-                        continue;
-
-                pend_offset = REG_OFFSET(group);
-                pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-                if (!pend)
-                        continue;
-
-                mask_offset = REG_OFFSET(group);
-                mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-                pend &= ~mask;
-
-                while (pend) {
-                        int offset = fls(pend) - 1;
-                        int real_irq = chip->irq_base + offset;
-                        generic_handle_irq(real_irq);
-                        pend &= ~BIT(offset);
-                }
-        }
-        chained_irq_exit(chip, desc);
-}
-
-static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
-{
-        static int used_gpioint_groups = 0;
-        int group = chip->group;
-        struct s5p_gpioint_bank *b, *bank = NULL;
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
-                return -ENOMEM;
-
-        list_for_each_entry(b, &banks, list) {
-                if (group >= b->start && group < b->start + b->nr_groups) {
-                        bank = b;
-                        break;
-                }
-        }
-        if (!bank)
-                return -EINVAL;
-
-        if (!bank->handler) {
-                bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
-                                      bank->nr_groups, GFP_KERNEL);
-                if (!bank->chips)
-                        return -ENOMEM;
-
-                irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
-                irq_set_handler_data(bank->irq, bank);
-                bank->handler = s5p_gpioint_handler;
-                printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
-                       bank->irq);
-        }
-
-        /*
-         * chained GPIO irq has been successfully registered, allocate new gpio
-         * int group and assign irq nubmers
-         */
-        chip->irq_base = S5P_GPIOINT_BASE +
-                         used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
-        used_gpioint_groups++;
-
-        bank->chips[group - bank->start] = chip;
-
-        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
-                                    GPIO_BASE(chip),
-                                    handle_level_irq);
-        if (!gc)
-                return -ENOMEM;
-        ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack_set_bit;
-        ct->chip.irq_mask = irq_gc_mask_set_bit;
-        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
-        ct->chip.irq_set_type = s5p_gpioint_set_type,
-        ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
-        ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
-        ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
-        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
-                               IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-        return 0;
-}
-
-int __init s5p_register_gpio_interrupt(int pin)
-{
-        struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
-        int offset, group;
-        int ret;
-
-        if (!my_chip)
-                return -EINVAL;
-
-        offset = pin - my_chip->chip.base;
-        group = my_chip->group;
-
-        /* check if the group has been already registered */
-        if (my_chip->irq_base)
-                goto success;
-
-        /* register gpio group */
-        ret = s5p_gpioint_add(my_chip);
-        if (ret == 0) {
-                my_chip->chip.to_irq = samsung_gpiolib_to_irq;
-                printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
-                       group);
-                goto success;
-        }
-        return ret;
-success:
-        my_chip->bitmap_gpio_int |= BIT(offset);
-
-        return my_chip->irq_base + offset;
-}
-
-int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
-{
-        struct s5p_gpioint_bank *bank;
-
-        bank = kzalloc(sizeof(*bank), GFP_KERNEL);
-        if (!bank)
-                return -ENOMEM;
-
-        bank->start = start;
-        bank->nr_groups = nr_groups;
-        bank->irq = chain_irq;
-
-        list_add_tail(&bank->list, &banks);
-        return 0;
-}
diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
deleted file mode 100644
index 52b16943617e..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-pm.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Based on arch/arm/plat-s3c24xx/irq-pm.c,
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-
-#include <plat/cpu.h>
-#include <plat/irqs.h>
-#include <plat/pm.h>
-#include <mach/map.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/regs-irq.h>
-
-/* state for IRQs over sleep */
-
-/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
- * as wakeup sources
- *
- * set bit to 1 in allow bitfield to enable the wakeup settings on it
-*/
-
-unsigned long s3c_irqwake_intallow      = 0x00000006L;
-unsigned long s3c_irqwake_eintallow     = 0xffffffffL;
-
-int s3c_irq_wake(struct irq_data *data, unsigned int state)
-{
-        unsigned long irqbit;
-        unsigned int irq_rtc_tic, irq_rtc_alarm;
-
-        irq_rtc_tic = IRQ_RTC_TIC;
-        irq_rtc_alarm = IRQ_RTC_ALARM;
-
-        if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
-                irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
-
-                if (!state)
-                        s3c_irqwake_intmask |= irqbit;
-                else
-                        s3c_irqwake_intmask &= ~irqbit;
-        } else {
-                return -ENOENT;
-        }
-
-        return 0;
-}
-
-static struct sleep_save eint_save[] = {
-        SAVE_ITEM(S5P_EINT_CON(0)),
-        SAVE_ITEM(S5P_EINT_CON(1)),
-        SAVE_ITEM(S5P_EINT_CON(2)),
-        SAVE_ITEM(S5P_EINT_CON(3)),
-
-        SAVE_ITEM(S5P_EINT_FLTCON(0)),
-        SAVE_ITEM(S5P_EINT_FLTCON(1)),
-        SAVE_ITEM(S5P_EINT_FLTCON(2)),
-        SAVE_ITEM(S5P_EINT_FLTCON(3)),
-        SAVE_ITEM(S5P_EINT_FLTCON(4)),
-        SAVE_ITEM(S5P_EINT_FLTCON(5)),
-        SAVE_ITEM(S5P_EINT_FLTCON(6)),
-        SAVE_ITEM(S5P_EINT_FLTCON(7)),
-
-        SAVE_ITEM(S5P_EINT_MASK(0)),
-        SAVE_ITEM(S5P_EINT_MASK(1)),
-        SAVE_ITEM(S5P_EINT_MASK(2)),
-        SAVE_ITEM(S5P_EINT_MASK(3)),
-};
-
-int s3c24xx_irq_suspend(void)
-{
-        s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
-
-        return 0;
-}
-
-void s3c24xx_irq_resume(void)
-{
-        s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
-}
-
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
deleted file mode 100644
index ddfaca9c79d8..000000000000
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P - Interrupt handling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-vic.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-
-void __init s5p_init_irq(u32 *vic, u32 num_vic)
-{
-#ifdef CONFIG_ARM_VIC
-        int irq;
-
-        /* initialize the VICs */
-        for (irq = 0; irq < num_vic; irq++)
-                vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
-#endif
-}
diff --git a/arch/arm/plat-samsung/s5p-pm.c b/arch/arm/plat-samsung/s5p-pm.c
deleted file mode 100644
index 0747468f0936..000000000000
--- a/arch/arm/plat-samsung/s5p-pm.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P Power Manager (Suspend-To-RAM) support
- *
- * Based on arch/arm/plat-s3c24xx/pm.c
- * Copyright (c) 2004,2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/suspend.h>
-#include <plat/pm.h>
-
-#define PFX "s5p pm: "
-
-/* s3c_pm_configure_extint
- *
- * configure all external interrupt pins
-*/
-
-void s3c_pm_configure_extint(void)
-{
-        /* nothing here yet */
-}
-
-void s3c_pm_restore_core(void)
-{
-        /* nothing here yet */
-}
-
-void s3c_pm_save_core(void)
-{
-        /* nothing here yet */
-}
-