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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 15:18:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 15:18:40 -0400
commit50686e8a3aed2f5d295e9d2e79ff43df461c7b76 (patch)
treee5de912d74c6e1d75e6ecf75f2a62c313955baff /arch
parentc5fc249862af862df027030188cc083e072ecd19 (diff)
parent1ec6f701707e4e97e451ff8b662360f1262a6c59 (diff)
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson: "New or improved SoC support: - add support for Atmel's SAMA5D2 SoC - add support for Freescale i.MX6UL - improved support for TI's DM814x platform - misc fixes and improvements for RockChip platforms - Marvell MVEBU suspend/resume support A few driver changes that ideally would belong in the drivers branch are also here (acked by appropriate maintainers): - power key input driver for Freescale platforms (svns) - RTC driver updates for Freescale platforms (svns/mxc) - clk fixes for TI DM814/816X + a bunch of other changes for various platforms" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: rockchip: pm: Fix PTR_ERR() argument ARM: imx: mach-imx6ul: Fix allmodconfig build clk: ti: fix for definition movement ARM: uniphier: drop v7_invalidate_l1 call at secondary entry memory: kill off set_irq_flags usage rtc: snvs: select option REGMAP_MMIO ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE ARM: BCM: Enable ARM erratum 798181 for BRCMSTB ARM: OMAP2+: Fix power domain operations regression caused by 81xx ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend ARM: rockchip: set correct stabilization thresholds in suspend ARM: rockchip: rename osc_switch_to_32k variable ARM: imx6ul: add fec MAC refrence clock and phy fixup init ARM: imx6ul: add fec bits to GPR syscon definition rtc: mxc: add support of device tree dt-binding: document the binding for mxc rtc rtc: mxc: use a second rtc clock ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback soc: mediatek: Fix SCPSYS compilation ARM: at91/soc: add basic support for new sama5d2 SoC ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig.debug15
-rw-r--r--arch/arm/boot/dts/am4372.dtsi1
-rw-r--r--arch/arm/include/debug/at91.S5
-rw-r--r--arch/arm/include/debug/imx-uart.h13
-rw-r--r--arch/arm/include/debug/zynq.S2
-rw-r--r--arch/arm/mach-at91/Kconfig12
-rw-r--r--arch/arm/mach-at91/sama5.c3
-rw-r--r--arch/arm/mach-at91/soc.h3
-rw-r--r--arch/arm/mach-bcm/Kconfig2
-rw-r--r--arch/arm/mach-davinci/cp_intc.c12
-rw-r--r--arch/arm/mach-imx/Kconfig8
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/cpu.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6ul.c88
-rw-r--r--arch/arm/mach-imx/mxc.h6
-rw-r--r--arch/arm/mach-mediatek/Kconfig1
-rw-r--r--arch/arm/mach-mvebu/coherency.c29
-rw-r--r--arch/arm/mach-mvebu/common.h4
-rw-r--r--arch/arm/mach-mvebu/pm-board.c30
-rw-r--r--arch/arm/mach-mvebu/pm.c79
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/board-generic.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain.h3
-rw-r--r--arch/arm/mach-omap2/clockdomains7xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains81xx_data.c23
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/control.c1
-rw-r--r--arch/arm/mach-omap2/io.c70
-rw-r--r--arch/arm/mach-omap2/iomap.h63
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c13
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c2
-rw-r--r--arch/arm/mach-omap2/omap3-restart.c1
-rw-r--r--arch/arm/mach-omap2/omap4-restart.c1
-rw-r--r--arch/arm/mach-omap2/omap54xx.h8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c16
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_81xx_data.c571
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c6
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c126
-rw-r--r--arch/arm/mach-omap2/prcm-common.h8
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h7
-rw-r--r--arch/arm/mach-omap2/prm44xx.c61
-rw-r--r--arch/arm/mach-omap2/prm_common.c1
-rw-r--r--arch/arm/mach-omap2/timer.c18
-rw-r--r--arch/arm/mach-pxa/devices.c37
-rw-r--r--arch/arm/mach-pxa/pxa25x.c1
-rw-r--r--arch/arm/mach-pxa/pxa27x.c1
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c1
-rw-r--r--arch/arm/mach-pxa/sharpsl_pm.c6
-rw-r--r--arch/arm/mach-pxa/tosa-bt.c15
-rw-r--r--arch/arm/mach-rockchip/platsmp.c56
-rw-r--r--arch/arm/mach-rockchip/pm.c78
-rw-r--r--arch/arm/mach-rockchip/pm.h12
-rw-r--r--arch/arm/mach-shmobile/Kconfig5
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c3
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7793.c33
-rw-r--r--arch/arm/mach-socfpga/core.h1
-rw-r--r--arch/arm/mach-socfpga/platsmp.c13
-rw-r--r--arch/arm/mach-socfpga/socfpga.c26
-rw-r--r--arch/arm/mach-sti/headsmp.S1
-rw-r--r--arch/arm/mach-sti/platsmp.c57
-rw-r--r--arch/arm/mach-sti/smp.h2
-rw-r--r--arch/arm/mach-uniphier/platsmp.c8
-rw-r--r--arch/arm/mach-zx/Kconfig1
-rw-r--r--arch/arm/mach-zx/Makefile2
-rw-r--r--arch/arm/mach-zx/zx296702-pm-domain.c202
-rw-r--r--arch/arm/mach-zynq/common.c4
-rw-r--r--arch/arm/mach-zynq/headsmp.S2
-rw-r--r--arch/arm/plat-pxa/dma.c22
-rw-r--r--arch/arm/plat-pxa/include/plat/dma.h15
73 files changed, 1529 insertions, 416 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a2e16f940394..0cfd7f947f6b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -141,6 +141,12 @@ choice
141 depends on ARCH_AT91 141 depends on ARCH_AT91
142 depends on SOC_SAMA5 142 depends on SOC_SAMA5
143 143
144 config AT91_DEBUG_LL_DBGU3
145 bool "Kernel low-level debugging on sama5d2"
146 select DEBUG_AT91_UART
147 depends on ARCH_AT91
148 depends on SOC_SAMA5
149
144 config DEBUG_BCM2835 150 config DEBUG_BCM2835
145 bool "Kernel low-level debugging on BCM2835 PL011 UART" 151 bool "Kernel low-level debugging on BCM2835 PL011 UART"
146 depends on ARCH_BCM2835 152 depends on ARCH_BCM2835
@@ -411,6 +417,13 @@ choice
411 Say Y here if you want kernel low-level debugging support 417 Say Y here if you want kernel low-level debugging support
412 on i.MX6SX. 418 on i.MX6SX.
413 419
420 config DEBUG_IMX6UL_UART
421 bool "i.MX6UL Debug UART"
422 depends on SOC_IMX6UL
423 help
424 Say Y here if you want kernel low-level debugging support
425 on i.MX6UL.
426
414 config DEBUG_IMX7D_UART 427 config DEBUG_IMX7D_UART
415 bool "i.MX7D Debug UART" 428 bool "i.MX7D Debug UART"
416 depends on SOC_IMX7D 429 depends on SOC_IMX7D
@@ -1269,6 +1282,7 @@ config DEBUG_IMX_UART_PORT
1269 DEBUG_IMX6Q_UART || \ 1282 DEBUG_IMX6Q_UART || \
1270 DEBUG_IMX6SL_UART || \ 1283 DEBUG_IMX6SL_UART || \
1271 DEBUG_IMX6SX_UART || \ 1284 DEBUG_IMX6SX_UART || \
1285 DEBUG_IMX6UL_UART || \
1272 DEBUG_IMX7D_UART 1286 DEBUG_IMX7D_UART
1273 default 1 1287 default 1
1274 depends on ARCH_MXC 1288 depends on ARCH_MXC
@@ -1320,6 +1334,7 @@ config DEBUG_LL_INCLUDE
1320 DEBUG_IMX6Q_UART || \ 1334 DEBUG_IMX6Q_UART || \
1321 DEBUG_IMX6SL_UART || \ 1335 DEBUG_IMX6SL_UART || \
1322 DEBUG_IMX6SX_UART || \ 1336 DEBUG_IMX6SX_UART || \
1337 DEBUG_IMX6UL_UART || \
1323 DEBUG_IMX7D_UART 1338 DEBUG_IMX7D_UART
1324 default "debug/ks8695.S" if DEBUG_KS8695_UART 1339 default "debug/ks8695.S" if DEBUG_KS8695_UART
1325 default "debug/msm.S" if DEBUG_QCOM_UARTDM 1340 default "debug/msm.S" if DEBUG_QCOM_UARTDM
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ade28c790f4b..359a3b6daf4f 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -86,6 +86,7 @@
86 prcm: prcm@1f0000 { 86 prcm: prcm@1f0000 {
87 compatible = "ti,am4-prcm"; 87 compatible = "ti,am4-prcm";
88 reg = <0x1f0000 0x11000>; 88 reg = <0x1f0000 0x11000>;
89 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 90
90 prcm_clocks: clocks { 91 prcm_clocks: clocks {
91 #address-cells = <1>; 92 #address-cells = <1>;
diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index c3c45e628e33..2556a8801c8c 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -13,9 +13,12 @@
13#define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */ 13#define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */
14#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1) 14#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
15#define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */ 15#define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */
16#else 16#elif defined(CONFIG_AT91_DEBUG_LL_DBGU2)
17/* On sama5d4, use USART3 as low level serial console */ 17/* On sama5d4, use USART3 as low level serial console */
18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ 18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
19#else
20/* On sama5d2, use UART1 as low level serial console */
21#define AT91_DBGU 0xf8020000
19#endif 22#endif
20 23
21#ifdef CONFIG_MMU 24#ifdef CONFIG_MMU
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 66f736f74684..bce58e975ad1 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -90,6 +90,17 @@
90#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR 90#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
91#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) 91#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
92 92
93#define IMX6UL_UART1_BASE_ADDR 0x02020000
94#define IMX6UL_UART2_BASE_ADDR 0x021e8000
95#define IMX6UL_UART3_BASE_ADDR 0x021ec000
96#define IMX6UL_UART4_BASE_ADDR 0x021f0000
97#define IMX6UL_UART5_BASE_ADDR 0x021f4000
98#define IMX6UL_UART6_BASE_ADDR 0x021fc000
99#define IMX6UL_UART7_BASE_ADDR 0x02018000
100#define IMX6UL_UART8_BASE_ADDR 0x02024000
101#define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR
102#define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n)
103
93#define IMX7D_UART1_BASE_ADDR 0x30860000 104#define IMX7D_UART1_BASE_ADDR 0x30860000
94#define IMX7D_UART2_BASE_ADDR 0x30890000 105#define IMX7D_UART2_BASE_ADDR 0x30890000
95#define IMX7D_UART3_BASE_ADDR 0x30880000 106#define IMX7D_UART3_BASE_ADDR 0x30880000
@@ -124,6 +135,8 @@
124#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) 135#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
125#elif defined(CONFIG_DEBUG_IMX6SX_UART) 136#elif defined(CONFIG_DEBUG_IMX6SX_UART)
126#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) 137#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
138#elif defined(CONFIG_DEBUG_IMX6UL_UART)
139#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL)
127#elif defined(CONFIG_DEBUG_IMX7D_UART) 140#elif defined(CONFIG_DEBUG_IMX7D_UART)
128#define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) 141#define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D)
129 142
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index bd13dedbdeff..de86b9247564 100644
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -38,7 +38,7 @@
38 .endm 38 .endm
39 39
40 .macro senduart,rd,rx 40 .macro senduart,rd,rx
41 str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 41 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
42 .endm 42 .endm
43 43
44 .macro waituart,rd,rx 44 .macro waituart,rd,rx
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index fd95f34945f4..89a755b90db2 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -8,6 +8,18 @@ menuconfig ARCH_AT91
8 select SOC_BUS 8 select SOC_BUS
9 9
10if ARCH_AT91 10if ARCH_AT91
11config SOC_SAMA5D2
12 bool "SAMA5D2 family" if ARCH_MULTI_V7
13 select SOC_SAMA5
14 select CACHE_L2X0
15 select HAVE_FB_ATMEL
16 select HAVE_AT91_UTMI
17 select HAVE_AT91_USB_CLK
18 select HAVE_AT91_H32MX
19 select HAVE_AT91_GENERATED_CLK
20 help
21 Select this if ou are using one of Atmel's SAMA5D2 family SoC.
22
11config SOC_SAMA5D3 23config SOC_SAMA5D3
12 bool "SAMA5D3 family" if ARCH_MULTI_V7 24 bool "SAMA5D3 family" if ARCH_MULTI_V7
13 select SOC_SAMA5 25 select SOC_SAMA5
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index 8fc47630bbc8..d9cf6799aec0 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -18,6 +18,8 @@
18#include "soc.h" 18#include "soc.h"
19 19
20static const struct at91_soc sama5_socs[] = { 20static const struct at91_soc sama5_socs[] = {
21 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27_EXID_MATCH,
22 "sama5d27", "sama5d2"),
21 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, 23 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
22 "sama5d31", "sama5d3"), 24 "sama5d31", "sama5d3"),
23 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, 25 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
@@ -64,6 +66,7 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
64MACHINE_END 66MACHINE_END
65 67
66static const char *const sama5_alt_dt_board_compat[] __initconst = { 68static const char *const sama5_alt_dt_board_compat[] __initconst = {
69 "atmel,sama5d2",
67 "atmel,sama5d4", 70 "atmel,sama5d4",
68 NULL 71 NULL
69}; 72};
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index be23c400596b..8ede0ef86172 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -62,6 +62,9 @@ at91_soc_init(const struct at91_soc *socs);
62#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 62#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0
63#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 63#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0
64 64
65#define SAMA5D2_CIDR_MATCH 0x0a5c08c0
66#define SAMA5D27_EXID_MATCH 0x00000021
67
65#define SAMA5D3_CIDR_MATCH 0x0a5c07c0 68#define SAMA5D3_CIDR_MATCH 0x0a5c07c0
66#define SAMA5D31_EXID_MATCH 0x00444300 69#define SAMA5D31_EXID_MATCH 0x00444300
67#define SAMA5D33_EXID_MATCH 0x00414300 70#define SAMA5D33_EXID_MATCH 0x00414300
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 0ac9e4b3b265..1319c3c14327 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -140,10 +140,12 @@ config ARCH_BCM_63XX
140config ARCH_BRCMSTB 140config ARCH_BRCMSTB
141 bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7 141 bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
142 select ARM_GIC 142 select ARM_GIC
143 select ARM_ERRATA_798181 if SMP
143 select HAVE_ARM_ARCH_TIMER 144 select HAVE_ARM_ARCH_TIMER
144 select BRCMSTB_GISB_ARB 145 select BRCMSTB_GISB_ARB
145 select BRCMSTB_L2_IRQ 146 select BRCMSTB_L2_IRQ
146 select BCM7120_L2_IRQ 147 select BCM7120_L2_IRQ
148 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
147 select ARCH_WANT_OPTIONAL_GPIOLIB 149 select ARCH_WANT_OPTIONAL_GPIOLIB
148 help 150 help
149 Say Y if you intend to run the kernel on a Broadcom ARM-based STB 151 Say Y if you intend to run the kernel on a Broadcom ARM-based STB
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index bf12ce64407a..507aad4b8dd9 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -85,23 +85,13 @@ static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
85 return 0; 85 return 0;
86} 86}
87 87
88/*
89 * Faking this allows us to to work with suspend functions of
90 * generic drivers which call {enable|disable}_irq_wake for
91 * wake up interrupt sources (eg RTC on DA850).
92 */
93static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
94{
95 return 0;
96}
97
98static struct irq_chip cp_intc_irq_chip = { 88static struct irq_chip cp_intc_irq_chip = {
99 .name = "cp_intc", 89 .name = "cp_intc",
100 .irq_ack = cp_intc_ack_irq, 90 .irq_ack = cp_intc_ack_irq,
101 .irq_mask = cp_intc_mask_irq, 91 .irq_mask = cp_intc_mask_irq,
102 .irq_unmask = cp_intc_unmask_irq, 92 .irq_unmask = cp_intc_unmask_irq,
103 .irq_set_type = cp_intc_set_irq_type, 93 .irq_set_type = cp_intc_set_irq_type,
104 .irq_set_wake = cp_intc_set_wake, 94 .flags = IRQCHIP_SKIP_SET_WAKE,
105}; 95};
106 96
107static struct irq_domain *cp_intc_domain; 97static struct irq_domain *cp_intc_domain;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 573536f1bb73..8ceda2844c4f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -548,6 +548,14 @@ config SOC_IMX6SX
548 help 548 help
549 This enables support for Freescale i.MX6 SoloX processor. 549 This enables support for Freescale i.MX6 SoloX processor.
550 550
551config SOC_IMX6UL
552 bool "i.MX6 UltraLite support"
553 select PINCTRL_IMX6UL
554 select SOC_IMX6
555
556 help
557 This enables support for Freescale i.MX6 UltraLite processor.
558
551config SOC_IMX7D 559config SOC_IMX7D
552 bool "i.MX7 Dual support" 560 bool "i.MX7 Dual support"
553 select PINCTRL_IMX7D 561 select PINCTRL_IMX7D
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 37c502ac9595..fb689d813b09 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,6 +83,7 @@ endif
83obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o 83obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
84obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o 84obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
85obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o 85obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
86obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
86obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o 87obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
87 88
88ifeq ($(CONFIG_SUSPEND),y) 89ifeq ($(CONFIG_SUSPEND),y)
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a7fa92a7b1d7..5b0f752d5507 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -130,6 +130,9 @@ struct device * __init imx_soc_device_init(void)
130 case MXC_CPU_IMX6Q: 130 case MXC_CPU_IMX6Q:
131 soc_id = "i.MX6Q"; 131 soc_id = "i.MX6Q";
132 break; 132 break;
133 case MXC_CPU_IMX6UL:
134 soc_id = "i.MX6UL";
135 break;
133 case MXC_CPU_IMX7D: 136 case MXC_CPU_IMX7D:
134 soc_id = "i.MX7D"; 137 soc_id = "i.MX7D";
135 break; 138 break;
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
new file mode 100644
index 000000000000..1b97fe133cef
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/irqchip.h>
9#include <linux/mfd/syscon.h>
10#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
11#include <linux/micrel_phy.h>
12#include <linux/of_platform.h>
13#include <linux/phy.h>
14#include <linux/regmap.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17
18#include "common.h"
19
20static void __init imx6ul_enet_clk_init(void)
21{
22 struct regmap *gpr;
23
24 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
25 if (!IS_ERR(gpr))
26 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
27 IMX6UL_GPR1_ENET_CLK_OUTPUT);
28 else
29 pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
30
31}
32
33static int ksz8081_phy_fixup(struct phy_device *dev)
34{
35 if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
36 phy_write(dev, 0x1f, 0x8110);
37 phy_write(dev, 0x16, 0x201);
38 } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
39 phy_write(dev, 0x1f, 0x8190);
40 phy_write(dev, 0x16, 0x202);
41 }
42
43 return 0;
44}
45
46static void __init imx6ul_enet_phy_init(void)
47{
48 if (IS_BUILTIN(CONFIG_PHYLIB))
49 phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff,
50 ksz8081_phy_fixup);
51}
52
53static inline void imx6ul_enet_init(void)
54{
55 imx6ul_enet_clk_init();
56 imx6ul_enet_phy_init();
57}
58
59static void __init imx6ul_init_machine(void)
60{
61 struct device *parent;
62
63 parent = imx_soc_device_init();
64 if (parent == NULL)
65 pr_warn("failed to initialize soc device\n");
66
67 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
68 imx6ul_enet_init();
69 imx_anatop_init();
70}
71
72static void __init imx6ul_init_irq(void)
73{
74 imx_init_revision_from_anatop();
75 imx_src_init();
76 irqchip_init();
77}
78
79static const char *imx6ul_dt_compat[] __initconst = {
80 "fsl,imx6ul",
81 NULL,
82};
83
84DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
85 .init_irq = imx6ul_init_irq,
86 .init_machine = imx6ul_init_machine,
87 .dt_compat = imx6ul_dt_compat,
88MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index c4436d4fd6fd..a5b1af6d7441 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -38,6 +38,7 @@
38#define MXC_CPU_IMX6DL 0x61 38#define MXC_CPU_IMX6DL 0x61
39#define MXC_CPU_IMX6SX 0x62 39#define MXC_CPU_IMX6SX 0x62
40#define MXC_CPU_IMX6Q 0x63 40#define MXC_CPU_IMX6Q 0x63
41#define MXC_CPU_IMX6UL 0x64
41#define MXC_CPU_IMX7D 0x72 42#define MXC_CPU_IMX7D 0x72
42 43
43#define IMX_DDR_TYPE_LPDDR2 1 44#define IMX_DDR_TYPE_LPDDR2 1
@@ -165,6 +166,11 @@ static inline bool cpu_is_imx6sx(void)
165 return __mxc_cpu_type == MXC_CPU_IMX6SX; 166 return __mxc_cpu_type == MXC_CPU_IMX6SX;
166} 167}
167 168
169static inline bool cpu_is_imx6ul(void)
170{
171 return __mxc_cpu_type == MXC_CPU_IMX6UL;
172}
173
168static inline bool cpu_is_imx6q(void) 174static inline bool cpu_is_imx6q(void)
169{ 175{
170 return __mxc_cpu_type == MXC_CPU_IMX6Q; 176 return __mxc_cpu_type == MXC_CPU_IMX6Q;
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 9f59e58da3a4..aeece17e5cea 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -3,6 +3,7 @@ menuconfig ARCH_MEDIATEK
3 select ARM_GIC 3 select ARM_GIC
4 select PINCTRL 4 select PINCTRL
5 select MTK_TIMER 5 select MTK_TIMER
6 select MFD_SYSCON
6 help 7 help
7 Support for Mediatek MT65xx & MT81xx SoCs 8 Support for Mediatek MT65xx & MT81xx SoCs
8 9
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index e46e9ea1e187..44eedf331ae7 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = {
65int ll_enable_coherency(void); 65int ll_enable_coherency(void);
66void ll_add_cpu_to_smp_group(void); 66void ll_add_cpu_to_smp_group(void);
67 67
68int set_cpu_coherent(void)
69{
70 if (!coherency_base) {
71 pr_warn("Can't make current CPU cache coherent.\n");
72 pr_warn("Coherency fabric is not initialized\n");
73 return 1;
74 }
75
76 ll_add_cpu_to_smp_group();
77 return ll_enable_coherency();
78}
79
80static int mvebu_hwcc_notifier(struct notifier_block *nb, 68static int mvebu_hwcc_notifier(struct notifier_block *nb,
81 unsigned long event, void *__dev) 69 unsigned long event, void *__dev)
82{ 70{
@@ -206,6 +194,23 @@ static int coherency_type(void)
206 return type; 194 return type;
207} 195}
208 196
197int set_cpu_coherent(void)
198{
199 int type = coherency_type();
200
201 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
202 if (!coherency_base) {
203 pr_warn("Can't make current CPU cache coherent.\n");
204 pr_warn("Coherency fabric is not initialized\n");
205 return 1;
206 }
207 ll_add_cpu_to_smp_group();
208 return ll_enable_coherency();
209 }
210
211 return 0;
212}
213
209int coherency_available(void) 214int coherency_available(void)
210{ 215{
211 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; 216 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 3e0aca1f288a..6b775492cfad 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -25,6 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
25 25
26void __iomem *mvebu_get_scu_base(void); 26void __iomem *mvebu_get_scu_base(void);
27 27
28int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)); 28int mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
29 29 u32 srcmd));
30#endif 30#endif
diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 301ab38d38ba..db17121d7d63 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Board-level suspend/resume support. 2 * Board-level suspend/resume support.
3 * 3 *
4 * Copyright (C) 2014 Marvell 4 * Copyright (C) 2014-2015 Marvell
5 * 5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 7 *
@@ -20,27 +20,27 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include "common.h" 21#include "common.h"
22 22
23#define ARMADA_XP_GP_PIC_NR_GPIOS 3 23#define ARMADA_PIC_NR_GPIOS 3
24 24
25static void __iomem *gpio_ctrl; 25static void __iomem *gpio_ctrl;
26static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; 26static int pic_gpios[ARMADA_PIC_NR_GPIOS];
27static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; 27static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
28 28
29static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd) 29static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
30{ 30{
31 u32 reg, ackcmd; 31 u32 reg, ackcmd;
32 int i; 32 int i;
33 33
34 /* Put 001 as value on the GPIOs */ 34 /* Put 001 as value on the GPIOs */
35 reg = readl(gpio_ctrl); 35 reg = readl(gpio_ctrl);
36 for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) 36 for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
37 reg &= ~BIT(pic_raw_gpios[i]); 37 reg &= ~BIT(pic_raw_gpios[i]);
38 reg |= BIT(pic_raw_gpios[0]); 38 reg |= BIT(pic_raw_gpios[0]);
39 writel(reg, gpio_ctrl); 39 writel(reg, gpio_ctrl);
40 40
41 /* Prepare writing 111 to the GPIOs */ 41 /* Prepare writing 111 to the GPIOs */
42 ackcmd = readl(gpio_ctrl); 42 ackcmd = readl(gpio_ctrl);
43 for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) 43 for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
44 ackcmd |= BIT(pic_raw_gpios[i]); 44 ackcmd |= BIT(pic_raw_gpios[i]);
45 45
46 srcmd = cpu_to_le32(srcmd); 46 srcmd = cpu_to_le32(srcmd);
@@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
76 [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1"); 76 [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
77} 77}
78 78
79static int mvebu_armada_xp_gp_pm_init(void) 79static int __init mvebu_armada_pm_init(void)
80{ 80{
81 struct device_node *np; 81 struct device_node *np;
82 struct device_node *gpio_ctrl_np; 82 struct device_node *gpio_ctrl_np;
@@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void)
89 if (!np) 89 if (!np)
90 return -ENODEV; 90 return -ENODEV;
91 91
92 for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) { 92 for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
93 char *name; 93 char *name;
94 struct of_phandle_args args; 94 struct of_phandle_args args;
95 95
@@ -134,11 +134,19 @@ static int mvebu_armada_xp_gp_pm_init(void)
134 if (!gpio_ctrl) 134 if (!gpio_ctrl)
135 return -ENOMEM; 135 return -ENOMEM;
136 136
137 mvebu_pm_init(mvebu_armada_xp_gp_pm_enter); 137 mvebu_pm_suspend_init(mvebu_armada_pm_enter);
138 138
139out: 139out:
140 of_node_put(np); 140 of_node_put(np);
141 return ret; 141 return ret;
142} 142}
143 143
144late_initcall(mvebu_armada_xp_gp_pm_init); 144/*
145 * Registering the mvebu_board_pm_enter callback must be done before
146 * the platform_suspend_ops will be registered. In the same time we
147 * also need to have the gpio devices registered. That's why we use a
148 * device_initcall_sync which is called after all the device_initcall
149 * (used by the gpio device) but before the late_initcall (used to
150 * register the platform_suspend_ops)
151 */
152device_initcall_sync(mvebu_armada_pm_init);
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 6573a8f11f70..8d32bf762b86 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -105,12 +105,10 @@ static phys_addr_t mvebu_internal_reg_base(void)
105 return of_translate_address(np, in_addr); 105 return of_translate_address(np, in_addr);
106} 106}
107 107
108static void mvebu_pm_store_bootinfo(void) 108static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
109{ 109{
110 u32 *store_addr;
111 phys_addr_t resume_pc; 110 phys_addr_t resume_pc;
112 111
113 store_addr = phys_to_virt(BOOT_INFO_ADDR);
114 resume_pc = virt_to_phys(armada_370_xp_cpu_resume); 112 resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
115 113
116 /* 114 /*
@@ -151,14 +149,30 @@ static void mvebu_pm_store_bootinfo(void)
151 writel(BOOT_MAGIC_LIST_END, store_addr); 149 writel(BOOT_MAGIC_LIST_END, store_addr);
152} 150}
153 151
154static int mvebu_pm_enter(suspend_state_t state) 152static int mvebu_pm_store_bootinfo(void)
155{ 153{
156 if (state != PM_SUSPEND_MEM) 154 u32 *store_addr;
157 return -EINVAL; 155
156 store_addr = phys_to_virt(BOOT_INFO_ADDR);
157
158 if (of_machine_is_compatible("marvell,armadaxp"))
159 mvebu_pm_store_armadaxp_bootinfo(store_addr);
160 else
161 return -ENODEV;
162
163 return 0;
164}
165
166static int mvebu_enter_suspend(void)
167{
168 int ret;
169
170 ret = mvebu_pm_store_bootinfo();
171 if (ret)
172 return ret;
158 173
159 cpu_pm_enter(); 174 cpu_pm_enter();
160 175
161 mvebu_pm_store_bootinfo();
162 cpu_suspend(0, mvebu_pm_powerdown); 176 cpu_suspend(0, mvebu_pm_powerdown);
163 177
164 outer_resume(); 178 outer_resume();
@@ -168,23 +182,62 @@ static int mvebu_pm_enter(suspend_state_t state)
168 set_cpu_coherent(); 182 set_cpu_coherent();
169 183
170 cpu_pm_exit(); 184 cpu_pm_exit();
185 return 0;
186}
187
188static int mvebu_pm_enter(suspend_state_t state)
189{
190 switch (state) {
191 case PM_SUSPEND_STANDBY:
192 cpu_do_idle();
193 break;
194 case PM_SUSPEND_MEM:
195 pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n");
196 return mvebu_enter_suspend();
197 default:
198 return -EINVAL;
199 }
200 return 0;
201}
202
203static int mvebu_pm_valid(suspend_state_t state)
204{
205 if (state == PM_SUSPEND_STANDBY)
206 return 1;
207
208 if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL)
209 return 1;
171 210
172 return 0; 211 return 0;
173} 212}
174 213
175static const struct platform_suspend_ops mvebu_pm_ops = { 214static const struct platform_suspend_ops mvebu_pm_ops = {
176 .enter = mvebu_pm_enter, 215 .enter = mvebu_pm_enter,
177 .valid = suspend_valid_only_mem, 216 .valid = mvebu_pm_valid,
178}; 217};
179 218
180int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)) 219static int __init mvebu_pm_init(void)
220{
221 if (!of_machine_is_compatible("marvell,armadaxp") &&
222 !of_machine_is_compatible("marvell,armada370") &&
223 !of_machine_is_compatible("marvell,armada380") &&
224 !of_machine_is_compatible("marvell,armada390"))
225 return -ENODEV;
226
227 suspend_set_ops(&mvebu_pm_ops);
228
229 return 0;
230}
231
232
233late_initcall(mvebu_pm_init);
234
235int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
236 u32 srcmd))
181{ 237{
182 struct device_node *np; 238 struct device_node *np;
183 struct resource res; 239 struct resource res;
184 240
185 if (!of_machine_is_compatible("marvell,armadaxp"))
186 return -ENODEV;
187
188 np = of_find_compatible_node(NULL, NULL, 241 np = of_find_compatible_node(NULL, NULL,
189 "marvell,armada-xp-sdram-controller"); 242 "marvell,armada-xp-sdram-controller");
190 if (!np) 243 if (!np)
@@ -212,7 +265,5 @@ int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
212 265
213 mvebu_board_pm_enter = board_pm_enter; 266 mvebu_board_pm_enter = board_pm_enter;
214 267
215 suspend_set_ops(&mvebu_pm_ops);
216
217 return 0; 268 return 0;
218} 269}
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8a7a6065ec21..935869698cbc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -226,8 +226,7 @@ obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
226# EMU peripherals 226# EMU peripherals
227obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o 227obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
228 228
229iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 229obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
230obj-y += $(iommu-m) $(iommu-y)
231 230
232# OMAP2420 MSDI controller integration support ("MMC") 231# OMAP2420 MSDI controller integration support ("MMC")
233obj-$(CONFIG_SOC_OMAP2420) += msdi.o 232obj-$(CONFIG_SOC_OMAP2420) += msdi.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 34ff14b7beab..24c9afc9e8a7 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -169,7 +169,7 @@ static const char *const ti814x_boards_compat[] __initconst = {
169 NULL, 169 NULL,
170}; 170};
171 171
172DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)") 172DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
173 .reserve = omap_reserve, 173 .reserve = omap_reserve,
174 .map_io = ti81xx_map_io, 174 .map_io = ti81xx_map_io,
175 .init_early = ti814x_init_early, 175 .init_early = ti814x_init_early,
@@ -297,7 +297,7 @@ static const char *const dra74x_boards_compat[] __initconst = {
297DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") 297DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
298 .reserve = omap_reserve, 298 .reserve = omap_reserve,
299 .smp = smp_ops(omap4_smp_ops), 299 .smp = smp_ops(omap4_smp_ops),
300 .map_io = omap5_map_io, 300 .map_io = dra7xx_map_io,
301 .init_early = dra7xx_init_early, 301 .init_early = dra7xx_init_early,
302 .init_late = dra7xx_init_late, 302 .init_late = dra7xx_init_late,
303 .init_irq = omap_gic_of_init, 303 .init_irq = omap_gic_of_init,
@@ -316,7 +316,7 @@ static const char *const dra72x_boards_compat[] __initconst = {
316 316
317DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)") 317DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
318 .reserve = omap_reserve, 318 .reserve = omap_reserve,
319 .map_io = omap5_map_io, 319 .map_io = dra7xx_map_io,
320 .init_early = dra7xx_init_early, 320 .init_early = dra7xx_init_early,
321 .init_late = dra7xx_init_late, 321 .init_late = dra7xx_init_late,
322 .init_irq = omap_gic_of_init, 322 .init_irq = omap_gic_of_init,
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 77bab5fb6814..2c398ce1a0f2 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,7 +216,8 @@ extern void __init omap242x_clockdomains_init(void);
216extern void __init omap243x_clockdomains_init(void); 216extern void __init omap243x_clockdomains_init(void);
217extern void __init omap3xxx_clockdomains_init(void); 217extern void __init omap3xxx_clockdomains_init(void);
218extern void __init am33xx_clockdomains_init(void); 218extern void __init am33xx_clockdomains_init(void);
219extern void __init ti81xx_clockdomains_init(void); 219extern void __init ti814x_clockdomains_init(void);
220extern void __init ti816x_clockdomains_init(void);
220extern void __init omap44xx_clockdomains_init(void); 221extern void __init omap44xx_clockdomains_init(void);
221extern void __init omap54xx_clockdomains_init(void); 222extern void __init omap54xx_clockdomains_init(void);
222extern void __init dra7xx_clockdomains_init(void); 223extern void __init dra7xx_clockdomains_init(void);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 57d5df0c1fbd..7581e036bda6 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -331,7 +331,7 @@ static struct clockdomain l4per2_7xx_clkdm = {
331 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT, 331 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
332 .wkdep_srcs = l4per2_wkup_sleep_deps, 332 .wkdep_srcs = l4per2_wkup_sleep_deps,
333 .sleepdep_srcs = l4per2_wkup_sleep_deps, 333 .sleepdep_srcs = l4per2_wkup_sleep_deps,
334 .flags = CLKDM_CAN_HWSUP_SWSUP, 334 .flags = CLKDM_CAN_SWSUP,
335}; 335};
336 336
337static struct clockdomain mpu0_7xx_clkdm = { 337static struct clockdomain mpu0_7xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index ce2a82001d0d..53442c86a820 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -165,7 +165,24 @@ static struct clockdomain default_l3_slow_816x_clkdm = {
165 .flags = CLKDM_CAN_SWSUP, 165 .flags = CLKDM_CAN_SWSUP,
166}; 166};
167 167
168static struct clockdomain *clockdomains_ti81xx[] __initdata = { 168static struct clockdomain *clockdomains_ti814x[] __initdata = {
169 &alwon_l3_slow_81xx_clkdm,
170 &alwon_l3_med_81xx_clkdm,
171 &alwon_l3_fast_81xx_clkdm,
172 &alwon_ethernet_81xx_clkdm,
173 &mmu_81xx_clkdm,
174 &mmu_cfg_81xx_clkdm,
175 NULL,
176};
177
178void __init ti814x_clockdomains_init(void)
179{
180 clkdm_register_platform_funcs(&am33xx_clkdm_operations);
181 clkdm_register_clkdms(clockdomains_ti814x);
182 clkdm_complete_init();
183}
184
185static struct clockdomain *clockdomains_ti816x[] __initdata = {
169 &alwon_mpu_816x_clkdm, 186 &alwon_mpu_816x_clkdm,
170 &alwon_l3_slow_81xx_clkdm, 187 &alwon_l3_slow_81xx_clkdm,
171 &alwon_l3_med_81xx_clkdm, 188 &alwon_l3_med_81xx_clkdm,
@@ -185,10 +202,10 @@ static struct clockdomain *clockdomains_ti81xx[] __initdata = {
185 NULL, 202 NULL,
186}; 203};
187 204
188void __init ti81xx_clockdomains_init(void) 205void __init ti816x_clockdomains_init(void)
189{ 206{
190 clkdm_register_platform_funcs(&am33xx_clkdm_operations); 207 clkdm_register_platform_funcs(&am33xx_clkdm_operations);
191 clkdm_register_clkdms(clockdomains_ti81xx); 208 clkdm_register_clkdms(clockdomains_ti816x);
192 clkdm_complete_init(); 209 clkdm_complete_init();
193} 210}
194#endif 211#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index cf3cf22ecd42..749d50bb4ca5 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -198,6 +198,7 @@ void __init omap3_map_io(void);
198void __init am33xx_map_io(void); 198void __init am33xx_map_io(void);
199void __init omap4_map_io(void); 199void __init omap4_map_io(void);
200void __init omap5_map_io(void); 200void __init omap5_map_io(void);
201void __init dra7xx_map_io(void);
201void __init ti81xx_map_io(void); 202void __init ti81xx_map_io(void);
202 203
203/** 204/**
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index f008930277ed..cf5855174c93 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -652,6 +652,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
652 { .compatible = "ti,am4-scm", .data = &ctrl_data }, 652 { .compatible = "ti,am4-scm", .data = &ctrl_data },
653 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, 653 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
654 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, 654 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
655 { .compatible = "ti,dm814-scm", .data = &ctrl_data },
655 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 656 { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
656 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, 657 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
657 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, 658 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a253aafbb9a2..6a4822dbb4ea 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -235,7 +235,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
235}; 235};
236#endif 236#endif
237 237
238#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 238#ifdef CONFIG_SOC_OMAP5
239static struct map_desc omap54xx_io_desc[] __initdata = { 239static struct map_desc omap54xx_io_desc[] __initdata = {
240 { 240 {
241 .virtual = L3_54XX_VIRT, 241 .virtual = L3_54XX_VIRT,
@@ -264,6 +264,53 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
264}; 264};
265#endif 265#endif
266 266
267#ifdef CONFIG_SOC_DRA7XX
268static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311};
312#endif
313
267#ifdef CONFIG_SOC_OMAP2420 314#ifdef CONFIG_SOC_OMAP2420
268void __init omap242x_map_io(void) 315void __init omap242x_map_io(void)
269{ 316{
@@ -308,12 +355,19 @@ void __init omap4_map_io(void)
308} 355}
309#endif 356#endif
310 357
311#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 358#ifdef CONFIG_SOC_OMAP5
312void __init omap5_map_io(void) 359void __init omap5_map_io(void)
313{ 360{
314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 361 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
315} 362}
316#endif 363#endif
364
365#ifdef CONFIG_SOC_DRA7XX
366void __init dra7xx_map_io(void)
367{
368 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
369}
370#endif
317/* 371/*
318 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
319 * 373 *
@@ -553,11 +607,11 @@ void __init ti814x_init_early(void)
553 omap2_prcm_base_init(); 607 omap2_prcm_base_init();
554 omap3xxx_voltagedomains_init(); 608 omap3xxx_voltagedomains_init();
555 omap3xxx_powerdomains_init(); 609 omap3xxx_powerdomains_init();
556 ti81xx_clockdomains_init(); 610 ti814x_clockdomains_init();
557 ti81xx_hwmod_init(); 611 dm814x_hwmod_init();
558 omap_hwmod_init_postsetup(); 612 omap_hwmod_init_postsetup();
559 if (of_have_populated_dt()) 613 if (of_have_populated_dt())
560 omap_clk_soc_init = ti81xx_dt_clk_init; 614 omap_clk_soc_init = dm814x_dt_clk_init;
561} 615}
562 616
563void __init ti816x_init_early(void) 617void __init ti816x_init_early(void)
@@ -570,11 +624,11 @@ void __init ti816x_init_early(void)
570 omap2_prcm_base_init(); 624 omap2_prcm_base_init();
571 omap3xxx_voltagedomains_init(); 625 omap3xxx_voltagedomains_init();
572 omap3xxx_powerdomains_init(); 626 omap3xxx_powerdomains_init();
573 ti81xx_clockdomains_init(); 627 ti816x_clockdomains_init();
574 ti81xx_hwmod_init(); 628 dm816x_hwmod_init();
575 omap_hwmod_init_postsetup(); 629 omap_hwmod_init_postsetup();
576 if (of_have_populated_dt()) 630 if (of_have_populated_dt())
577 omap_clk_soc_init = ti81xx_dt_clk_init; 631 omap_clk_soc_init = dm816x_dt_clk_init;
578} 632}
579#endif 633#endif
580 634
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index cce2b65039f1..6191d244438a 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -194,3 +194,66 @@
194#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ 194#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
195#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) 195#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
196#define L4_PER_54XX_SIZE SZ_4M 196#define L4_PER_54XX_SIZE SZ_4M
197
198/*
199 * ----------------------------------------------------------------------------
200 * DRA7xx specific IO mapping
201 * ----------------------------------------------------------------------------
202 */
203/*
204 * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000
205 * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping
206 * everything is just inefficient, since, there are too many address holes.
207 */
208#define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE
209#define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET)
210#define L3_MAIN_SN_DRA7XX_SIZE SZ_1M
211
212/*
213 * L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB)
214 * (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000)
215 */
216#define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE
217#define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
218#define L4_PER1_DRA7XX_SIZE SZ_1M
219
220/*
221 * L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB)
222 * (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000)
223 * NOTE: This is a bit of an orphan memory map sitting isolated in TRM
224 */
225#define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE
226#define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
227#define L4_CFG_MPU_DRA7XX_SIZE SZ_1M
228
229/*
230 * L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB)
231 * (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000)
232 */
233#define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE
234#define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
235#define L4_PER2_DRA7XX_SIZE SZ_1M
236
237/*
238 * L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB)
239 * (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000)
240 */
241#define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE
242#define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
243#define L4_PER3_DRA7XX_SIZE SZ_2M
244
245/*
246 * L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)?
247 * (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000)
248 */
249#define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE
250#define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
251#define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M)
252
253/*
254 * L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)?
255 * (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000)
256 */
257#define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE
258#define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
259#define L4_WKUP_DRA7XX_SIZE SZ_1M
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 4068350f9059..8867eb4025bf 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -11,7 +11,6 @@
11 */ 11 */
12 12
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/module.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/err.h> 15#include <linux/err.h>
17#include <linux/slab.h> 16#include <linux/slab.h>
@@ -63,15 +62,5 @@ static int __init omap_iommu_init(void)
63 62
64 return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL); 63 return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
65} 64}
66/* must be ready before omap3isp is probed */
67omap_subsys_initcall(omap_iommu_init); 65omap_subsys_initcall(omap_iommu_init);
68 66/* must be ready before omap3isp is probed */
69static void __exit omap_iommu_exit(void)
70{
71 /* Do nothing */
72}
73module_exit(omap_iommu_exit);
74
75MODULE_AUTHOR("Hiroshi DOYU");
76MODULE_DESCRIPTION("omap iommu: omap device registration");
77MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 79f49d904a06..65024af169d3 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -105,7 +105,7 @@ static void dummy_cpu_resume(void)
105static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) 105static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
106{} 106{}
107 107
108struct cpu_pm_ops omap_pm_ops = { 108static struct cpu_pm_ops omap_pm_ops = {
109 .finish_suspend = default_finish_suspend, 109 .finish_suspend = default_finish_suspend,
110 .resume = dummy_cpu_resume, 110 .resume = dummy_cpu_resume,
111 .scu_prepare = dummy_scu_prepare, 111 .scu_prepare = dummy_scu_prepare,
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 103a49f68bcb..4bdd22edb96b 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/reboot.h> 15#include <linux/reboot.h>
16 16
17#include "common.h"
17#include "control.h" 18#include "control.h"
18#include "prm.h" 19#include "prm.h"
19 20
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
index a99e7f7fb5be..e17136a50e27 100644
--- a/arch/arm/mach-omap2/omap4-restart.c
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -9,6 +9,7 @@
9 9
10#include <linux/types.h> 10#include <linux/types.h>
11#include <linux/reboot.h> 11#include <linux/reboot.h>
12#include "common.h"
12#include "prm.h" 13#include "prm.h"
13 14
14/** 15/**
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index 2d35c5709408..0ca8e938096b 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -30,6 +30,14 @@
30#define OMAP54XX_CTRL_BASE 0x4a002800 30#define OMAP54XX_CTRL_BASE 0x4a002800
31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
32 32
33/* DRA7 specific base addresses */
34#define L3_MAIN_SN_DRA7XX_BASE 0x44000000
35#define L4_PER1_DRA7XX_BASE 0x48000000
36#define L4_CFG_MPU_DRA7XX_BASE 0x48210000
37#define L4_PER2_DRA7XX_BASE 0x48400000
38#define L4_PER3_DRA7XX_BASE 0x48800000
39#define L4_CFG_DRA7XX_BASE 0x4A000000
40#define L4_WKUP_DRA7XX_BASE 0x4ae00000
33#define DRA7XX_CM_CORE_AON_BASE 0x4a005000 41#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
34#define DRA7XX_CTRL_BASE 0x4a003400 42#define DRA7XX_CTRL_BASE 0x4a003400
35#define DRA7XX_TAP_BASE 0x4ae0c000 43#define DRA7XX_TAP_BASE 0x4ae0c000
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ef9e6341d96..cc8a987149e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -300,7 +300,20 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
300 300
301 /* Module might have lost context, always update cache and register */ 301 /* Module might have lost context, always update cache and register */
302 oh->_sysc_cache = v; 302 oh->_sysc_cache = v;
303
304 /*
305 * Some IP blocks (such as RTC) require unlocking of IP before
306 * accessing its registers. If a function pointer is present
307 * to unlock, then call it before accessing sysconfig and
308 * call lock after writing sysconfig.
309 */
310 if (oh->class->unlock)
311 oh->class->unlock(oh);
312
303 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); 313 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
314
315 if (oh->class->lock)
316 oh->class->lock(oh);
304} 317}
305 318
306/** 319/**
@@ -3887,7 +3900,8 @@ void __init omap_hwmod_init(void)
3887 soc_ops.init_clkdm = _init_clkdm; 3900 soc_ops.init_clkdm = _init_clkdm;
3888 soc_ops.update_context_lost = _omap4_update_context_lost; 3901 soc_ops.update_context_lost = _omap4_update_context_lost;
3889 soc_ops.get_context_lost = _omap4_get_context_lost; 3902 soc_ops.get_context_lost = _omap4_get_context_lost;
3890 } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) { 3903 } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
3904 soc_is_am43xx()) {
3891 soc_ops.enable_module = _omap4_enable_module; 3905 soc_ops.enable_module = _omap4_enable_module;
3892 soc_ops.disable_module = _omap4_disable_module; 3906 soc_ops.disable_module = _omap4_disable_module;
3893 soc_ops.wait_target_ready = _omap4_wait_target_ready; 3907 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index b5d27ec81610..ca6df1a73475 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -576,6 +576,8 @@ struct omap_hwmod_omap4_prcm {
576 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown 576 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
577 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn 577 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
578 * @enable_preprogram: ptr to fn to be executed during device enable 578 * @enable_preprogram: ptr to fn to be executed during device enable
579 * @lock: ptr to fn to be executed to lock IP registers
580 * @unlock: ptr to fn to be executed to unlock IP registers
579 * 581 *
580 * Represent the class of a OMAP hardware "modules" (e.g. timer, 582 * Represent the class of a OMAP hardware "modules" (e.g. timer,
581 * smartreflex, gpio, uart...) 583 * smartreflex, gpio, uart...)
@@ -600,6 +602,8 @@ struct omap_hwmod_class {
600 int (*pre_shutdown)(struct omap_hwmod *oh); 602 int (*pre_shutdown)(struct omap_hwmod *oh);
601 int (*reset)(struct omap_hwmod *oh); 603 int (*reset)(struct omap_hwmod *oh);
602 int (*enable_preprogram)(struct omap_hwmod *oh); 604 int (*enable_preprogram)(struct omap_hwmod *oh);
605 void (*lock)(struct omap_hwmod *oh);
606 void (*unlock)(struct omap_hwmod *oh);
603}; 607};
604 608
605/** 609/**
@@ -755,7 +759,8 @@ extern int omap3xxx_hwmod_init(void);
755extern int omap44xx_hwmod_init(void); 759extern int omap44xx_hwmod_init(void);
756extern int omap54xx_hwmod_init(void); 760extern int omap54xx_hwmod_init(void);
757extern int am33xx_hwmod_init(void); 761extern int am33xx_hwmod_init(void);
758extern int ti81xx_hwmod_init(void); 762extern int dm814x_hwmod_init(void);
763extern int dm816x_hwmod_init(void);
759extern int dra7xx_hwmod_init(void); 764extern int dra7xx_hwmod_init(void);
760int am43xx_hwmod_init(void); 765int am43xx_hwmod_init(void);
761 766
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 6dcfd03ced8f..36bcd2e75422 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,7 +20,7 @@
20#include "prm-regbits-24xx.h" 20#include "prm-regbits-24xx.h"
21#include "wd_timer.h" 21#include "wd_timer.h"
22 22
23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 23static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
24 { .name = "dispc", .dma_req = 5 }, 24 { .name = "dispc", .dma_req = 5 },
25 { .dma_req = -1, }, 25 { .dma_req = -1, },
26}; 26};
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 215d5efa0dba..e97a894b5f88 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -480,7 +480,7 @@ static struct omap_hwmod am43xx_dss_core_hwmod = {
480 480
481/* dispc */ 481/* dispc */
482 482
483struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { 483static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
484 .manager_count = 1, 484 .manager_count = 1,
485 .has_framedonetv_irq = 0 485 .has_framedonetv_irq = 0
486}; 486};
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index c92413769144..b1288f56d509 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -32,21 +32,59 @@
32 */ 32 */
33 33
34/* 34/*
35 * The alwon .clkctrl_offs field is offset from the CM_ALWON, that's 35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
36 * TRM 18.7.17 CM_ALWON device register values minus 0x1400. 36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
37 */ 37 */
38#define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
39#define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
40#define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
41#define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
42#define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
43#define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
44#define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
45#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
46#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
47#define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
48#define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
49#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
50#define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
51#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
52#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
53#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
54#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
55#define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
56#define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
57#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
58#define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
59#define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
60#define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
61#define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
62#define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
63#define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
64#define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
65#define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
66#define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
67
68/* Registers specific to dm814x */
69#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
70#define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
71#define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
72#define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
73#define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
74#define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
75#define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
76#define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
77#define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
78#define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
79#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
80#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
81#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
82#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
83#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
84#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
85
86/* Registers specific to dm816x */
38#define DM816X_DM_ALWON_BASE 0x1400 87#define DM816X_DM_ALWON_BASE 0x1400
39#define DM816X_CM_ALWON_MCASP0_CLKCTRL (0x1540 - DM816X_DM_ALWON_BASE)
40#define DM816X_CM_ALWON_MCASP1_CLKCTRL (0x1544 - DM816X_DM_ALWON_BASE)
41#define DM816X_CM_ALWON_MCASP2_CLKCTRL (0x1548 - DM816X_DM_ALWON_BASE)
42#define DM816X_CM_ALWON_MCBSP_CLKCTRL (0x154c - DM816X_DM_ALWON_BASE)
43#define DM816X_CM_ALWON_UART_0_CLKCTRL (0x1550 - DM816X_DM_ALWON_BASE)
44#define DM816X_CM_ALWON_UART_1_CLKCTRL (0x1554 - DM816X_DM_ALWON_BASE)
45#define DM816X_CM_ALWON_UART_2_CLKCTRL (0x1558 - DM816X_DM_ALWON_BASE)
46#define DM816X_CM_ALWON_GPIO_0_CLKCTRL (0x155c - DM816X_DM_ALWON_BASE)
47#define DM816X_CM_ALWON_GPIO_1_CLKCTRL (0x1560 - DM816X_DM_ALWON_BASE)
48#define DM816X_CM_ALWON_I2C_0_CLKCTRL (0x1564 - DM816X_DM_ALWON_BASE)
49#define DM816X_CM_ALWON_I2C_1_CLKCTRL (0x1568 - DM816X_DM_ALWON_BASE)
50#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 88#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
51#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 89#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
52#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 90#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
@@ -54,29 +92,11 @@
54#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 92#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
55#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 93#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
56#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 94#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
57#define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE)
58#define DM816X_CM_ALWON_SPI_CLKCTRL (0x1590 - DM816X_DM_ALWON_BASE)
59#define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE)
60#define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE)
61#define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE)
62#define DM816X_CM_ALWON_MMUCFG_CLKCTRL (0x15a8 - DM816X_DM_ALWON_BASE)
63#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 95#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
64#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 96#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
65#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 97#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
66#define DM816X_CM_ALWON_CONTRL_CLKCTRL (0x15c4 - DM816X_DM_ALWON_BASE)
67#define DM816X_CM_ALWON_GPMC_CLKCTRL (0x15d0 - DM816X_DM_ALWON_BASE)
68#define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE)
69#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 98#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
70#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 99#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
71#define DM816X_CM_ALWON_L3_CLKCTRL (0x15e4 - DM816X_DM_ALWON_BASE)
72#define DM816X_CM_ALWON_L4HS_CLKCTRL (0x15e8 - DM816X_DM_ALWON_BASE)
73#define DM816X_CM_ALWON_L4LS_CLKCTRL (0x15ec - DM816X_DM_ALWON_BASE)
74#define DM816X_CM_ALWON_RTC_CLKCTRL (0x15f0 - DM816X_DM_ALWON_BASE)
75#define DM816X_CM_ALWON_TPCC_CLKCTRL (0x15f4 - DM816X_DM_ALWON_BASE)
76#define DM816X_CM_ALWON_TPTC0_CLKCTRL (0x15f8 - DM816X_DM_ALWON_BASE)
77#define DM816X_CM_ALWON_TPTC1_CLKCTRL (0x15fc - DM816X_DM_ALWON_BASE)
78#define DM816X_CM_ALWON_TPTC2_CLKCTRL (0x1600 - DM816X_DM_ALWON_BASE)
79#define DM816X_CM_ALWON_TPTC3_CLKCTRL (0x1604 - DM816X_DM_ALWON_BASE)
80#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 100#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
81#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 101#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
82 102
@@ -88,28 +108,28 @@
88#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) 108#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
89 109
90/* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 110/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
91static struct omap_hwmod dm816x_alwon_l3_slow_hwmod = { 111static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
92 .name = "alwon_l3_slow", 112 .name = "alwon_l3_slow",
93 .clkdm_name = "alwon_l3s_clkdm", 113 .clkdm_name = "alwon_l3s_clkdm",
94 .class = &l3_hwmod_class, 114 .class = &l3_hwmod_class,
95 .flags = HWMOD_NO_IDLEST, 115 .flags = HWMOD_NO_IDLEST,
96}; 116};
97 117
98static struct omap_hwmod dm816x_default_l3_slow_hwmod = { 118static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
99 .name = "default_l3_slow", 119 .name = "default_l3_slow",
100 .clkdm_name = "default_l3_slow_clkdm", 120 .clkdm_name = "default_l3_slow_clkdm",
101 .class = &l3_hwmod_class, 121 .class = &l3_hwmod_class,
102 .flags = HWMOD_NO_IDLEST, 122 .flags = HWMOD_NO_IDLEST,
103}; 123};
104 124
105static struct omap_hwmod dm816x_alwon_l3_med_hwmod = { 125static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
106 .name = "l3_med", 126 .name = "l3_med",
107 .clkdm_name = "alwon_l3_med_clkdm", 127 .clkdm_name = "alwon_l3_med_clkdm",
108 .class = &l3_hwmod_class, 128 .class = &l3_hwmod_class,
109 .flags = HWMOD_NO_IDLEST, 129 .flags = HWMOD_NO_IDLEST,
110}; 130};
111 131
112static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = { 132static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
113 .name = "l3_fast", 133 .name = "l3_fast",
114 .clkdm_name = "alwon_l3_fast_clkdm", 134 .clkdm_name = "alwon_l3_fast_clkdm",
115 .class = &l3_hwmod_class, 135 .class = &l3_hwmod_class,
@@ -120,7 +140,7 @@ static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = {
120 * L4 standard peripherals, see TRM table 1-12 for devices using this. 140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
121 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
122 */ 142 */
123static struct omap_hwmod dm816x_l4_ls_hwmod = { 143static struct omap_hwmod dm81xx_l4_ls_hwmod = {
124 .name = "l4_ls", 144 .name = "l4_ls",
125 .clkdm_name = "alwon_l3s_clkdm", 145 .clkdm_name = "alwon_l3s_clkdm",
126 .class = &l4_hwmod_class, 146 .class = &l4_hwmod_class,
@@ -131,27 +151,54 @@ static struct omap_hwmod dm816x_l4_ls_hwmod = {
131 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 151 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
132 * table 1-73 for devices using 250MHz SYSCLK5 clock. 152 * table 1-73 for devices using 250MHz SYSCLK5 clock.
133 */ 153 */
134static struct omap_hwmod dm816x_l4_hs_hwmod = { 154static struct omap_hwmod dm81xx_l4_hs_hwmod = {
135 .name = "l4_hs", 155 .name = "l4_hs",
136 .clkdm_name = "alwon_l3_med_clkdm", 156 .clkdm_name = "alwon_l3_med_clkdm",
137 .class = &l4_hwmod_class, 157 .class = &l4_hwmod_class,
138}; 158};
139 159
140/* L3 slow -> L4 ls peripheral interface running at 125MHz */ 160/* L3 slow -> L4 ls peripheral interface running at 125MHz */
141static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls = { 161static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
142 .master = &dm816x_alwon_l3_slow_hwmod, 162 .master = &dm81xx_alwon_l3_slow_hwmod,
143 .slave = &dm816x_l4_ls_hwmod, 163 .slave = &dm81xx_l4_ls_hwmod,
144 .user = OCP_USER_MPU, 164 .user = OCP_USER_MPU,
145}; 165};
146 166
147/* L3 med -> L4 fast peripheral interface running at 250MHz */ 167/* L3 med -> L4 fast peripheral interface running at 250MHz */
148static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs = { 168static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
149 .master = &dm816x_alwon_l3_med_hwmod, 169 .master = &dm81xx_alwon_l3_med_hwmod,
150 .slave = &dm816x_l4_hs_hwmod, 170 .slave = &dm81xx_l4_hs_hwmod,
151 .user = OCP_USER_MPU, 171 .user = OCP_USER_MPU,
152}; 172};
153 173
154/* MPU */ 174/* MPU */
175static struct omap_hwmod dm814x_mpu_hwmod = {
176 .name = "mpu",
177 .clkdm_name = "alwon_l3s_clkdm",
178 .class = &mpu_hwmod_class,
179 .flags = HWMOD_INIT_NO_IDLE,
180 .main_clk = "mpu_ck",
181 .prcm = {
182 .omap4 = {
183 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
184 .modulemode = MODULEMODE_SWCTRL,
185 },
186 },
187};
188
189static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
190 .master = &dm814x_mpu_hwmod,
191 .slave = &dm81xx_alwon_l3_slow_hwmod,
192 .user = OCP_USER_MPU,
193};
194
195/* L3 med peripheral interface running at 200MHz */
196static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
197 .master = &dm814x_mpu_hwmod,
198 .slave = &dm81xx_alwon_l3_med_hwmod,
199 .user = OCP_USER_MPU,
200};
201
155static struct omap_hwmod dm816x_mpu_hwmod = { 202static struct omap_hwmod dm816x_mpu_hwmod = {
156 .name = "mpu", 203 .name = "mpu",
157 .clkdm_name = "alwon_mpu_clkdm", 204 .clkdm_name = "alwon_mpu_clkdm",
@@ -168,14 +215,14 @@ static struct omap_hwmod dm816x_mpu_hwmod = {
168 215
169static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 216static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
170 .master = &dm816x_mpu_hwmod, 217 .master = &dm816x_mpu_hwmod,
171 .slave = &dm816x_alwon_l3_slow_hwmod, 218 .slave = &dm81xx_alwon_l3_slow_hwmod,
172 .user = OCP_USER_MPU, 219 .user = OCP_USER_MPU,
173}; 220};
174 221
175/* L3 med peripheral interface running at 250MHz */ 222/* L3 med peripheral interface running at 250MHz */
176static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 223static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
177 .master = &dm816x_mpu_hwmod, 224 .master = &dm816x_mpu_hwmod,
178 .slave = &dm816x_alwon_l3_med_hwmod, 225 .slave = &dm81xx_alwon_l3_med_hwmod,
179 .user = OCP_USER_MPU, 226 .user = OCP_USER_MPU,
180}; 227};
181 228
@@ -197,13 +244,13 @@ static struct omap_hwmod_class uart_class = {
197 .sysc = &uart_sysc, 244 .sysc = &uart_sysc,
198}; 245};
199 246
200static struct omap_hwmod dm816x_uart1_hwmod = { 247static struct omap_hwmod dm81xx_uart1_hwmod = {
201 .name = "uart1", 248 .name = "uart1",
202 .clkdm_name = "alwon_l3s_clkdm", 249 .clkdm_name = "alwon_l3s_clkdm",
203 .main_clk = "sysclk10_ck", 250 .main_clk = "sysclk10_ck",
204 .prcm = { 251 .prcm = {
205 .omap4 = { 252 .omap4 = {
206 .clkctrl_offs = DM816X_CM_ALWON_UART_0_CLKCTRL, 253 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
207 .modulemode = MODULEMODE_SWCTRL, 254 .modulemode = MODULEMODE_SWCTRL,
208 }, 255 },
209 }, 256 },
@@ -211,20 +258,20 @@ static struct omap_hwmod dm816x_uart1_hwmod = {
211 .flags = DEBUG_TI81XXUART1_FLAGS, 258 .flags = DEBUG_TI81XXUART1_FLAGS,
212}; 259};
213 260
214static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1 = { 261static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
215 .master = &dm816x_l4_ls_hwmod, 262 .master = &dm81xx_l4_ls_hwmod,
216 .slave = &dm816x_uart1_hwmod, 263 .slave = &dm81xx_uart1_hwmod,
217 .clk = "sysclk6_ck", 264 .clk = "sysclk6_ck",
218 .user = OCP_USER_MPU, 265 .user = OCP_USER_MPU,
219}; 266};
220 267
221static struct omap_hwmod dm816x_uart2_hwmod = { 268static struct omap_hwmod dm81xx_uart2_hwmod = {
222 .name = "uart2", 269 .name = "uart2",
223 .clkdm_name = "alwon_l3s_clkdm", 270 .clkdm_name = "alwon_l3s_clkdm",
224 .main_clk = "sysclk10_ck", 271 .main_clk = "sysclk10_ck",
225 .prcm = { 272 .prcm = {
226 .omap4 = { 273 .omap4 = {
227 .clkctrl_offs = DM816X_CM_ALWON_UART_1_CLKCTRL, 274 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
228 .modulemode = MODULEMODE_SWCTRL, 275 .modulemode = MODULEMODE_SWCTRL,
229 }, 276 },
230 }, 277 },
@@ -232,20 +279,20 @@ static struct omap_hwmod dm816x_uart2_hwmod = {
232 .flags = DEBUG_TI81XXUART2_FLAGS, 279 .flags = DEBUG_TI81XXUART2_FLAGS,
233}; 280};
234 281
235static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2 = { 282static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
236 .master = &dm816x_l4_ls_hwmod, 283 .master = &dm81xx_l4_ls_hwmod,
237 .slave = &dm816x_uart2_hwmod, 284 .slave = &dm81xx_uart2_hwmod,
238 .clk = "sysclk6_ck", 285 .clk = "sysclk6_ck",
239 .user = OCP_USER_MPU, 286 .user = OCP_USER_MPU,
240}; 287};
241 288
242static struct omap_hwmod dm816x_uart3_hwmod = { 289static struct omap_hwmod dm81xx_uart3_hwmod = {
243 .name = "uart3", 290 .name = "uart3",
244 .clkdm_name = "alwon_l3s_clkdm", 291 .clkdm_name = "alwon_l3s_clkdm",
245 .main_clk = "sysclk10_ck", 292 .main_clk = "sysclk10_ck",
246 .prcm = { 293 .prcm = {
247 .omap4 = { 294 .omap4 = {
248 .clkctrl_offs = DM816X_CM_ALWON_UART_2_CLKCTRL, 295 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
249 .modulemode = MODULEMODE_SWCTRL, 296 .modulemode = MODULEMODE_SWCTRL,
250 }, 297 },
251 }, 298 },
@@ -253,9 +300,9 @@ static struct omap_hwmod dm816x_uart3_hwmod = {
253 .flags = DEBUG_TI81XXUART3_FLAGS, 300 .flags = DEBUG_TI81XXUART3_FLAGS,
254}; 301};
255 302
256static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3 = { 303static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
257 .master = &dm816x_l4_ls_hwmod, 304 .master = &dm81xx_l4_ls_hwmod,
258 .slave = &dm816x_uart3_hwmod, 305 .slave = &dm81xx_uart3_hwmod,
259 .clk = "sysclk6_ck", 306 .clk = "sysclk6_ck",
260 .user = OCP_USER_MPU, 307 .user = OCP_USER_MPU,
261}; 308};
@@ -276,23 +323,23 @@ static struct omap_hwmod_class wd_timer_class = {
276 .reset = &omap2_wd_timer_reset, 323 .reset = &omap2_wd_timer_reset,
277}; 324};
278 325
279static struct omap_hwmod dm816x_wd_timer_hwmod = { 326static struct omap_hwmod dm81xx_wd_timer_hwmod = {
280 .name = "wd_timer", 327 .name = "wd_timer",
281 .clkdm_name = "alwon_l3s_clkdm", 328 .clkdm_name = "alwon_l3s_clkdm",
282 .main_clk = "sysclk18_ck", 329 .main_clk = "sysclk18_ck",
283 .flags = HWMOD_NO_IDLEST, 330 .flags = HWMOD_NO_IDLEST,
284 .prcm = { 331 .prcm = {
285 .omap4 = { 332 .omap4 = {
286 .clkctrl_offs = DM816X_CM_ALWON_WDTIMER_CLKCTRL, 333 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
287 .modulemode = MODULEMODE_SWCTRL, 334 .modulemode = MODULEMODE_SWCTRL,
288 }, 335 },
289 }, 336 },
290 .class = &wd_timer_class, 337 .class = &wd_timer_class,
291}; 338};
292 339
293static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1 = { 340static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
294 .master = &dm816x_l4_ls_hwmod, 341 .master = &dm81xx_l4_ls_hwmod,
295 .slave = &dm816x_wd_timer_hwmod, 342 .slave = &dm81xx_wd_timer_hwmod,
296 .clk = "sysclk6_ck", 343 .clk = "sysclk6_ck",
297 .user = OCP_USER_MPU, 344 .user = OCP_USER_MPU,
298}; 345};
@@ -320,27 +367,27 @@ static struct omap_hwmod dm81xx_i2c1_hwmod = {
320 .main_clk = "sysclk10_ck", 367 .main_clk = "sysclk10_ck",
321 .prcm = { 368 .prcm = {
322 .omap4 = { 369 .omap4 = {
323 .clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL, 370 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
324 .modulemode = MODULEMODE_SWCTRL, 371 .modulemode = MODULEMODE_SWCTRL,
325 }, 372 },
326 }, 373 },
327 .class = &i2c_class, 374 .class = &i2c_class,
328}; 375};
329 376
330static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1 = { 377static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
331 .master = &dm816x_l4_ls_hwmod, 378 .master = &dm81xx_l4_ls_hwmod,
332 .slave = &dm81xx_i2c1_hwmod, 379 .slave = &dm81xx_i2c1_hwmod,
333 .clk = "sysclk6_ck", 380 .clk = "sysclk6_ck",
334 .user = OCP_USER_MPU, 381 .user = OCP_USER_MPU,
335}; 382};
336 383
337static struct omap_hwmod dm816x_i2c2_hwmod = { 384static struct omap_hwmod dm81xx_i2c2_hwmod = {
338 .name = "i2c2", 385 .name = "i2c2",
339 .clkdm_name = "alwon_l3s_clkdm", 386 .clkdm_name = "alwon_l3s_clkdm",
340 .main_clk = "sysclk10_ck", 387 .main_clk = "sysclk10_ck",
341 .prcm = { 388 .prcm = {
342 .omap4 = { 389 .omap4 = {
343 .clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL, 390 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
344 .modulemode = MODULEMODE_SWCTRL, 391 .modulemode = MODULEMODE_SWCTRL,
345 }, 392 },
346 }, 393 },
@@ -358,9 +405,9 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
358 .sysc_fields = &omap_hwmod_sysc_type1, 405 .sysc_fields = &omap_hwmod_sysc_type1,
359}; 406};
360 407
361static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2 = { 408static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
362 .master = &dm816x_l4_ls_hwmod, 409 .master = &dm81xx_l4_ls_hwmod,
363 .slave = &dm816x_i2c2_hwmod, 410 .slave = &dm81xx_i2c2_hwmod,
364 .clk = "sysclk6_ck", 411 .clk = "sysclk6_ck",
365 .user = OCP_USER_MPU, 412 .user = OCP_USER_MPU,
366}; 413};
@@ -378,7 +425,7 @@ static struct omap_hwmod dm81xx_elm_hwmod = {
378}; 425};
379 426
380static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 427static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
381 .master = &dm816x_l4_ls_hwmod, 428 .master = &dm81xx_l4_ls_hwmod,
382 .slave = &dm81xx_elm_hwmod, 429 .slave = &dm81xx_elm_hwmod,
383 .user = OCP_USER_MPU, 430 .user = OCP_USER_MPU,
384}; 431};
@@ -417,7 +464,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
417 .main_clk = "sysclk6_ck", 464 .main_clk = "sysclk6_ck",
418 .prcm = { 465 .prcm = {
419 .omap4 = { 466 .omap4 = {
420 .clkctrl_offs = DM816X_CM_ALWON_GPIO_0_CLKCTRL, 467 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
421 .modulemode = MODULEMODE_SWCTRL, 468 .modulemode = MODULEMODE_SWCTRL,
422 }, 469 },
423 }, 470 },
@@ -427,7 +474,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
427}; 474};
428 475
429static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 476static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
430 .master = &dm816x_l4_ls_hwmod, 477 .master = &dm81xx_l4_ls_hwmod,
431 .slave = &dm81xx_gpio1_hwmod, 478 .slave = &dm81xx_gpio1_hwmod,
432 .user = OCP_USER_MPU, 479 .user = OCP_USER_MPU,
433}; 480};
@@ -443,7 +490,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
443 .main_clk = "sysclk6_ck", 490 .main_clk = "sysclk6_ck",
444 .prcm = { 491 .prcm = {
445 .omap4 = { 492 .omap4 = {
446 .clkctrl_offs = DM816X_CM_ALWON_GPIO_1_CLKCTRL, 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
447 .modulemode = MODULEMODE_SWCTRL, 494 .modulemode = MODULEMODE_SWCTRL,
448 }, 495 },
449 }, 496 },
@@ -453,7 +500,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
453}; 500};
454 501
455static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 502static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
456 .master = &dm816x_l4_ls_hwmod, 503 .master = &dm81xx_l4_ls_hwmod,
457 .slave = &dm81xx_gpio2_hwmod, 504 .slave = &dm81xx_gpio2_hwmod,
458 .user = OCP_USER_MPU, 505 .user = OCP_USER_MPU,
459}; 506};
@@ -482,14 +529,14 @@ static struct omap_hwmod dm81xx_gpmc_hwmod = {
482 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 529 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
483 .prcm = { 530 .prcm = {
484 .omap4 = { 531 .omap4 = {
485 .clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL, 532 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
486 .modulemode = MODULEMODE_SWCTRL, 533 .modulemode = MODULEMODE_SWCTRL,
487 }, 534 },
488 }, 535 },
489}; 536};
490 537
491struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 538static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
492 .master = &dm816x_alwon_l3_slow_hwmod, 539 .master = &dm81xx_alwon_l3_slow_hwmod,
493 .slave = &dm81xx_gpmc_hwmod, 540 .slave = &dm81xx_gpmc_hwmod,
494 .user = OCP_USER_MPU, 541 .user = OCP_USER_MPU,
495}; 542};
@@ -522,7 +569,7 @@ static struct omap_hwmod dm81xx_usbss_hwmod = {
522}; 569};
523 570
524static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { 571static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
525 .master = &dm816x_default_l3_slow_hwmod, 572 .master = &dm81xx_default_l3_slow_hwmod,
526 .slave = &dm81xx_usbss_hwmod, 573 .slave = &dm81xx_usbss_hwmod,
527 .clk = "sysclk6_ck", 574 .clk = "sysclk6_ck",
528 .user = OCP_USER_MPU, 575 .user = OCP_USER_MPU,
@@ -547,6 +594,22 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
547 .timer_capability = OMAP_TIMER_ALWON, 594 .timer_capability = OMAP_TIMER_ALWON,
548}; 595};
549 596
597static struct omap_hwmod dm814x_timer1_hwmod = {
598 .name = "timer1",
599 .clkdm_name = "alwon_l3s_clkdm",
600 .main_clk = "timer_sys_ck",
601 .dev_attr = &capability_alwon_dev_attr,
602 .class = &dm816x_timer_hwmod_class,
603 .flags = HWMOD_NO_IDLEST,
604};
605
606static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
607 .master = &dm81xx_l4_ls_hwmod,
608 .slave = &dm814x_timer1_hwmod,
609 .clk = "timer_sys_ck",
610 .user = OCP_USER_MPU,
611};
612
550static struct omap_hwmod dm816x_timer1_hwmod = { 613static struct omap_hwmod dm816x_timer1_hwmod = {
551 .name = "timer1", 614 .name = "timer1",
552 .clkdm_name = "alwon_l3s_clkdm", 615 .clkdm_name = "alwon_l3s_clkdm",
@@ -562,12 +625,28 @@ static struct omap_hwmod dm816x_timer1_hwmod = {
562}; 625};
563 626
564static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 627static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
565 .master = &dm816x_l4_ls_hwmod, 628 .master = &dm81xx_l4_ls_hwmod,
566 .slave = &dm816x_timer1_hwmod, 629 .slave = &dm816x_timer1_hwmod,
567 .clk = "sysclk6_ck", 630 .clk = "sysclk6_ck",
568 .user = OCP_USER_MPU, 631 .user = OCP_USER_MPU,
569}; 632};
570 633
634static struct omap_hwmod dm814x_timer2_hwmod = {
635 .name = "timer2",
636 .clkdm_name = "alwon_l3s_clkdm",
637 .main_clk = "timer_sys_ck",
638 .dev_attr = &capability_alwon_dev_attr,
639 .class = &dm816x_timer_hwmod_class,
640 .flags = HWMOD_NO_IDLEST,
641};
642
643static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
644 .master = &dm81xx_l4_ls_hwmod,
645 .slave = &dm814x_timer2_hwmod,
646 .clk = "timer_sys_ck",
647 .user = OCP_USER_MPU,
648};
649
571static struct omap_hwmod dm816x_timer2_hwmod = { 650static struct omap_hwmod dm816x_timer2_hwmod = {
572 .name = "timer2", 651 .name = "timer2",
573 .clkdm_name = "alwon_l3s_clkdm", 652 .clkdm_name = "alwon_l3s_clkdm",
@@ -583,7 +662,7 @@ static struct omap_hwmod dm816x_timer2_hwmod = {
583}; 662};
584 663
585static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 664static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
586 .master = &dm816x_l4_ls_hwmod, 665 .master = &dm81xx_l4_ls_hwmod,
587 .slave = &dm816x_timer2_hwmod, 666 .slave = &dm816x_timer2_hwmod,
588 .clk = "sysclk6_ck", 667 .clk = "sysclk6_ck",
589 .user = OCP_USER_MPU, 668 .user = OCP_USER_MPU,
@@ -604,7 +683,7 @@ static struct omap_hwmod dm816x_timer3_hwmod = {
604}; 683};
605 684
606static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 685static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
607 .master = &dm816x_l4_ls_hwmod, 686 .master = &dm81xx_l4_ls_hwmod,
608 .slave = &dm816x_timer3_hwmod, 687 .slave = &dm816x_timer3_hwmod,
609 .clk = "sysclk6_ck", 688 .clk = "sysclk6_ck",
610 .user = OCP_USER_MPU, 689 .user = OCP_USER_MPU,
@@ -625,7 +704,7 @@ static struct omap_hwmod dm816x_timer4_hwmod = {
625}; 704};
626 705
627static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 706static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
628 .master = &dm816x_l4_ls_hwmod, 707 .master = &dm81xx_l4_ls_hwmod,
629 .slave = &dm816x_timer4_hwmod, 708 .slave = &dm816x_timer4_hwmod,
630 .clk = "sysclk6_ck", 709 .clk = "sysclk6_ck",
631 .user = OCP_USER_MPU, 710 .user = OCP_USER_MPU,
@@ -646,7 +725,7 @@ static struct omap_hwmod dm816x_timer5_hwmod = {
646}; 725};
647 726
648static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 727static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
649 .master = &dm816x_l4_ls_hwmod, 728 .master = &dm81xx_l4_ls_hwmod,
650 .slave = &dm816x_timer5_hwmod, 729 .slave = &dm816x_timer5_hwmod,
651 .clk = "sysclk6_ck", 730 .clk = "sysclk6_ck",
652 .user = OCP_USER_MPU, 731 .user = OCP_USER_MPU,
@@ -667,7 +746,7 @@ static struct omap_hwmod dm816x_timer6_hwmod = {
667}; 746};
668 747
669static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 748static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
670 .master = &dm816x_l4_ls_hwmod, 749 .master = &dm81xx_l4_ls_hwmod,
671 .slave = &dm816x_timer6_hwmod, 750 .slave = &dm816x_timer6_hwmod,
672 .clk = "sysclk6_ck", 751 .clk = "sysclk6_ck",
673 .user = OCP_USER_MPU, 752 .user = OCP_USER_MPU,
@@ -688,12 +767,68 @@ static struct omap_hwmod dm816x_timer7_hwmod = {
688}; 767};
689 768
690static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 769static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
691 .master = &dm816x_l4_ls_hwmod, 770 .master = &dm81xx_l4_ls_hwmod,
692 .slave = &dm816x_timer7_hwmod, 771 .slave = &dm816x_timer7_hwmod,
693 .clk = "sysclk6_ck", 772 .clk = "sysclk6_ck",
694 .user = OCP_USER_MPU, 773 .user = OCP_USER_MPU,
695}; 774};
696 775
776/* CPSW on dm814x */
777static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
778 .rev_offs = 0x0,
779 .sysc_offs = 0x8,
780 .syss_offs = 0x4,
781 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
782 SYSS_HAS_RESET_STATUS,
783 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
784 MSTANDBY_NO,
785 .sysc_fields = &omap_hwmod_sysc_type3,
786};
787
788static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
789 .name = "cpgmac0",
790 .sysc = &dm814x_cpgmac_sysc,
791};
792
793static struct omap_hwmod dm814x_cpgmac0_hwmod = {
794 .name = "cpgmac0",
795 .class = &dm814x_cpgmac0_hwmod_class,
796 .clkdm_name = "alwon_ethernet_clkdm",
797 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
798 .main_clk = "cpsw_125mhz_gclk",
799 .prcm = {
800 .omap4 = {
801 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
802 .modulemode = MODULEMODE_SWCTRL,
803 },
804 },
805};
806
807static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
808 .name = "davinci_mdio",
809};
810
811static struct omap_hwmod dm814x_mdio_hwmod = {
812 .name = "davinci_mdio",
813 .class = &dm814x_mdio_hwmod_class,
814 .clkdm_name = "alwon_ethernet_clkdm",
815 .main_clk = "cpsw_125mhz_gclk",
816};
817
818static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
819 .master = &dm81xx_l4_hs_hwmod,
820 .slave = &dm814x_cpgmac0_hwmod,
821 .clk = "cpsw_125mhz_gclk",
822 .user = OCP_USER_MPU,
823};
824
825static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
826 .master = &dm814x_cpgmac0_hwmod,
827 .slave = &dm814x_mdio_hwmod,
828 .user = OCP_USER_MPU,
829 .flags = HWMOD_NO_IDLEST,
830};
831
697/* EMAC Ethernet */ 832/* EMAC Ethernet */
698static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 833static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
699 .rev_offs = 0x0, 834 .rev_offs = 0x0,
@@ -717,21 +852,21 @@ static struct omap_hwmod dm816x_emac0_hwmod = {
717 .class = &dm816x_emac_hwmod_class, 852 .class = &dm816x_emac_hwmod_class,
718}; 853};
719 854
720static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0 = { 855static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
721 .master = &dm816x_l4_hs_hwmod, 856 .master = &dm81xx_l4_hs_hwmod,
722 .slave = &dm816x_emac0_hwmod, 857 .slave = &dm816x_emac0_hwmod,
723 .clk = "sysclk5_ck", 858 .clk = "sysclk5_ck",
724 .user = OCP_USER_MPU, 859 .user = OCP_USER_MPU,
725}; 860};
726 861
727static struct omap_hwmod_class dm816x_mdio_hwmod_class = { 862static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
728 .name = "davinci_mdio", 863 .name = "davinci_mdio",
729 .sysc = &dm816x_emac_sysc, 864 .sysc = &dm816x_emac_sysc,
730}; 865};
731 866
732struct omap_hwmod dm816x_emac0_mdio_hwmod = { 867static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
733 .name = "davinci_mdio", 868 .name = "davinci_mdio",
734 .class = &dm816x_mdio_hwmod_class, 869 .class = &dm81xx_mdio_hwmod_class,
735 .clkdm_name = "alwon_ethernet_clkdm", 870 .clkdm_name = "alwon_ethernet_clkdm",
736 .main_clk = "sysclk24_ck", 871 .main_clk = "sysclk24_ck",
737 .flags = HWMOD_NO_IDLEST, 872 .flags = HWMOD_NO_IDLEST,
@@ -741,15 +876,15 @@ struct omap_hwmod dm816x_emac0_mdio_hwmod = {
741 */ 876 */
742 .prcm = { 877 .prcm = {
743 .omap4 = { 878 .omap4 = {
744 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_0_CLKCTRL, 879 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
745 .modulemode = MODULEMODE_SWCTRL, 880 .modulemode = MODULEMODE_SWCTRL,
746 }, 881 },
747 }, 882 },
748}; 883};
749 884
750struct omap_hwmod_ocp_if dm816x_emac0__mdio = { 885static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
751 .master = &dm816x_l4_hs_hwmod, 886 .master = &dm81xx_l4_hs_hwmod,
752 .slave = &dm816x_emac0_mdio_hwmod, 887 .slave = &dm81xx_emac0_mdio_hwmod,
753 .user = OCP_USER_MPU, 888 .user = OCP_USER_MPU,
754}; 889};
755 890
@@ -768,7 +903,7 @@ static struct omap_hwmod dm816x_emac1_hwmod = {
768}; 903};
769 904
770static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 905static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
771 .master = &dm816x_l4_hs_hwmod, 906 .master = &dm81xx_l4_hs_hwmod,
772 .slave = &dm816x_emac1_hwmod, 907 .slave = &dm816x_emac1_hwmod,
773 .clk = "sysclk5_ck", 908 .clk = "sysclk5_ck",
774 .user = OCP_USER_MPU, 909 .user = OCP_USER_MPU,
@@ -815,7 +950,7 @@ static struct omap_hwmod dm816x_mmc1_hwmod = {
815}; 950};
816 951
817static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 952static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
818 .master = &dm816x_l4_ls_hwmod, 953 .master = &dm81xx_l4_ls_hwmod,
819 .slave = &dm816x_mmc1_hwmod, 954 .slave = &dm816x_mmc1_hwmod,
820 .clk = "sysclk6_ck", 955 .clk = "sysclk6_ck",
821 .user = OCP_USER_MPU, 956 .user = OCP_USER_MPU,
@@ -843,13 +978,13 @@ static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
843 .num_chipselect = 4, 978 .num_chipselect = 4,
844}; 979};
845 980
846static struct omap_hwmod dm816x_mcspi1_hwmod = { 981static struct omap_hwmod dm81xx_mcspi1_hwmod = {
847 .name = "mcspi1", 982 .name = "mcspi1",
848 .clkdm_name = "alwon_l3s_clkdm", 983 .clkdm_name = "alwon_l3s_clkdm",
849 .main_clk = "sysclk10_ck", 984 .main_clk = "sysclk10_ck",
850 .prcm = { 985 .prcm = {
851 .omap4 = { 986 .omap4 = {
852 .clkctrl_offs = DM816X_CM_ALWON_SPI_CLKCTRL, 987 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
853 .modulemode = MODULEMODE_SWCTRL, 988 .modulemode = MODULEMODE_SWCTRL,
854 }, 989 },
855 }, 990 },
@@ -857,14 +992,14 @@ static struct omap_hwmod dm816x_mcspi1_hwmod = {
857 .dev_attr = &dm816x_mcspi1_dev_attr, 992 .dev_attr = &dm816x_mcspi1_dev_attr,
858}; 993};
859 994
860static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1 = { 995static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
861 .master = &dm816x_l4_ls_hwmod, 996 .master = &dm81xx_l4_ls_hwmod,
862 .slave = &dm816x_mcspi1_hwmod, 997 .slave = &dm81xx_mcspi1_hwmod,
863 .clk = "sysclk6_ck", 998 .clk = "sysclk6_ck",
864 .user = OCP_USER_MPU, 999 .user = OCP_USER_MPU,
865}; 1000};
866 1001
867static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = { 1002static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
868 .rev_offs = 0x000, 1003 .rev_offs = 0x000,
869 .sysc_offs = 0x010, 1004 .sysc_offs = 0x010,
870 .syss_offs = 0x014, 1005 .syss_offs = 0x014,
@@ -874,55 +1009,55 @@ static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = {
874 .sysc_fields = &omap_hwmod_sysc_type1, 1009 .sysc_fields = &omap_hwmod_sysc_type1,
875}; 1010};
876 1011
877static struct omap_hwmod_class dm816x_mailbox_hwmod_class = { 1012static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
878 .name = "mailbox", 1013 .name = "mailbox",
879 .sysc = &dm816x_mailbox_sysc, 1014 .sysc = &dm81xx_mailbox_sysc,
880}; 1015};
881 1016
882static struct omap_hwmod dm816x_mailbox_hwmod = { 1017static struct omap_hwmod dm81xx_mailbox_hwmod = {
883 .name = "mailbox", 1018 .name = "mailbox",
884 .clkdm_name = "alwon_l3s_clkdm", 1019 .clkdm_name = "alwon_l3s_clkdm",
885 .class = &dm816x_mailbox_hwmod_class, 1020 .class = &dm81xx_mailbox_hwmod_class,
886 .main_clk = "sysclk6_ck", 1021 .main_clk = "sysclk6_ck",
887 .prcm = { 1022 .prcm = {
888 .omap4 = { 1023 .omap4 = {
889 .clkctrl_offs = DM816X_CM_ALWON_MAILBOX_CLKCTRL, 1024 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
890 .modulemode = MODULEMODE_SWCTRL, 1025 .modulemode = MODULEMODE_SWCTRL,
891 }, 1026 },
892 }, 1027 },
893}; 1028};
894 1029
895static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox = { 1030static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
896 .master = &dm816x_l4_ls_hwmod, 1031 .master = &dm81xx_l4_ls_hwmod,
897 .slave = &dm816x_mailbox_hwmod, 1032 .slave = &dm81xx_mailbox_hwmod,
898 .user = OCP_USER_MPU, 1033 .user = OCP_USER_MPU,
899}; 1034};
900 1035
901static struct omap_hwmod_class dm816x_tpcc_hwmod_class = { 1036static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
902 .name = "tpcc", 1037 .name = "tpcc",
903}; 1038};
904 1039
905struct omap_hwmod dm816x_tpcc_hwmod = { 1040static struct omap_hwmod dm81xx_tpcc_hwmod = {
906 .name = "tpcc", 1041 .name = "tpcc",
907 .class = &dm816x_tpcc_hwmod_class, 1042 .class = &dm81xx_tpcc_hwmod_class,
908 .clkdm_name = "alwon_l3s_clkdm", 1043 .clkdm_name = "alwon_l3s_clkdm",
909 .main_clk = "sysclk4_ck", 1044 .main_clk = "sysclk4_ck",
910 .prcm = { 1045 .prcm = {
911 .omap4 = { 1046 .omap4 = {
912 .clkctrl_offs = DM816X_CM_ALWON_TPCC_CLKCTRL, 1047 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
913 .modulemode = MODULEMODE_SWCTRL, 1048 .modulemode = MODULEMODE_SWCTRL,
914 }, 1049 },
915 }, 1050 },
916}; 1051};
917 1052
918struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc = { 1053static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
919 .master = &dm816x_alwon_l3_fast_hwmod, 1054 .master = &dm81xx_alwon_l3_fast_hwmod,
920 .slave = &dm816x_tpcc_hwmod, 1055 .slave = &dm81xx_tpcc_hwmod,
921 .clk = "sysclk4_ck", 1056 .clk = "sysclk4_ck",
922 .user = OCP_USER_MPU, 1057 .user = OCP_USER_MPU,
923}; 1058};
924 1059
925static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = { 1060static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
926 { 1061 {
927 .pa_start = 0x49800000, 1062 .pa_start = 0x49800000,
928 .pa_end = 0x49800000 + SZ_8K - 1, 1063 .pa_end = 0x49800000 + SZ_8K - 1,
@@ -931,40 +1066,40 @@ static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = {
931 { }, 1066 { },
932}; 1067};
933 1068
934static struct omap_hwmod_class dm816x_tptc0_hwmod_class = { 1069static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
935 .name = "tptc0", 1070 .name = "tptc0",
936}; 1071};
937 1072
938struct omap_hwmod dm816x_tptc0_hwmod = { 1073static struct omap_hwmod dm81xx_tptc0_hwmod = {
939 .name = "tptc0", 1074 .name = "tptc0",
940 .class = &dm816x_tptc0_hwmod_class, 1075 .class = &dm81xx_tptc0_hwmod_class,
941 .clkdm_name = "alwon_l3s_clkdm", 1076 .clkdm_name = "alwon_l3s_clkdm",
942 .main_clk = "sysclk4_ck", 1077 .main_clk = "sysclk4_ck",
943 .prcm = { 1078 .prcm = {
944 .omap4 = { 1079 .omap4 = {
945 .clkctrl_offs = DM816X_CM_ALWON_TPTC0_CLKCTRL, 1080 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
946 .modulemode = MODULEMODE_SWCTRL, 1081 .modulemode = MODULEMODE_SWCTRL,
947 }, 1082 },
948 }, 1083 },
949}; 1084};
950 1085
951struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0 = { 1086static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
952 .master = &dm816x_alwon_l3_fast_hwmod, 1087 .master = &dm81xx_alwon_l3_fast_hwmod,
953 .slave = &dm816x_tptc0_hwmod, 1088 .slave = &dm81xx_tptc0_hwmod,
954 .clk = "sysclk4_ck", 1089 .clk = "sysclk4_ck",
955 .addr = dm816x_tptc0_addr_space, 1090 .addr = dm81xx_tptc0_addr_space,
956 .user = OCP_USER_MPU, 1091 .user = OCP_USER_MPU,
957}; 1092};
958 1093
959struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast = { 1094static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
960 .master = &dm816x_tptc0_hwmod, 1095 .master = &dm81xx_tptc0_hwmod,
961 .slave = &dm816x_alwon_l3_fast_hwmod, 1096 .slave = &dm81xx_alwon_l3_fast_hwmod,
962 .clk = "sysclk4_ck", 1097 .clk = "sysclk4_ck",
963 .addr = dm816x_tptc0_addr_space, 1098 .addr = dm81xx_tptc0_addr_space,
964 .user = OCP_USER_MPU, 1099 .user = OCP_USER_MPU,
965}; 1100};
966 1101
967static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = { 1102static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
968 { 1103 {
969 .pa_start = 0x49900000, 1104 .pa_start = 0x49900000,
970 .pa_end = 0x49900000 + SZ_8K - 1, 1105 .pa_end = 0x49900000 + SZ_8K - 1,
@@ -973,40 +1108,40 @@ static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = {
973 { }, 1108 { },
974}; 1109};
975 1110
976static struct omap_hwmod_class dm816x_tptc1_hwmod_class = { 1111static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
977 .name = "tptc1", 1112 .name = "tptc1",
978}; 1113};
979 1114
980struct omap_hwmod dm816x_tptc1_hwmod = { 1115static struct omap_hwmod dm81xx_tptc1_hwmod = {
981 .name = "tptc1", 1116 .name = "tptc1",
982 .class = &dm816x_tptc1_hwmod_class, 1117 .class = &dm81xx_tptc1_hwmod_class,
983 .clkdm_name = "alwon_l3s_clkdm", 1118 .clkdm_name = "alwon_l3s_clkdm",
984 .main_clk = "sysclk4_ck", 1119 .main_clk = "sysclk4_ck",
985 .prcm = { 1120 .prcm = {
986 .omap4 = { 1121 .omap4 = {
987 .clkctrl_offs = DM816X_CM_ALWON_TPTC1_CLKCTRL, 1122 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
988 .modulemode = MODULEMODE_SWCTRL, 1123 .modulemode = MODULEMODE_SWCTRL,
989 }, 1124 },
990 }, 1125 },
991}; 1126};
992 1127
993struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1 = { 1128static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
994 .master = &dm816x_alwon_l3_fast_hwmod, 1129 .master = &dm81xx_alwon_l3_fast_hwmod,
995 .slave = &dm816x_tptc1_hwmod, 1130 .slave = &dm81xx_tptc1_hwmod,
996 .clk = "sysclk4_ck", 1131 .clk = "sysclk4_ck",
997 .addr = dm816x_tptc1_addr_space, 1132 .addr = dm81xx_tptc1_addr_space,
998 .user = OCP_USER_MPU, 1133 .user = OCP_USER_MPU,
999}; 1134};
1000 1135
1001struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast = { 1136static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1002 .master = &dm816x_tptc1_hwmod, 1137 .master = &dm81xx_tptc1_hwmod,
1003 .slave = &dm816x_alwon_l3_fast_hwmod, 1138 .slave = &dm81xx_alwon_l3_fast_hwmod,
1004 .clk = "sysclk4_ck", 1139 .clk = "sysclk4_ck",
1005 .addr = dm816x_tptc1_addr_space, 1140 .addr = dm81xx_tptc1_addr_space,
1006 .user = OCP_USER_MPU, 1141 .user = OCP_USER_MPU,
1007}; 1142};
1008 1143
1009static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = { 1144static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1010 { 1145 {
1011 .pa_start = 0x49a00000, 1146 .pa_start = 0x49a00000,
1012 .pa_end = 0x49a00000 + SZ_8K - 1, 1147 .pa_end = 0x49a00000 + SZ_8K - 1,
@@ -1015,40 +1150,40 @@ static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = {
1015 { }, 1150 { },
1016}; 1151};
1017 1152
1018static struct omap_hwmod_class dm816x_tptc2_hwmod_class = { 1153static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1019 .name = "tptc2", 1154 .name = "tptc2",
1020}; 1155};
1021 1156
1022struct omap_hwmod dm816x_tptc2_hwmod = { 1157static struct omap_hwmod dm81xx_tptc2_hwmod = {
1023 .name = "tptc2", 1158 .name = "tptc2",
1024 .class = &dm816x_tptc2_hwmod_class, 1159 .class = &dm81xx_tptc2_hwmod_class,
1025 .clkdm_name = "alwon_l3s_clkdm", 1160 .clkdm_name = "alwon_l3s_clkdm",
1026 .main_clk = "sysclk4_ck", 1161 .main_clk = "sysclk4_ck",
1027 .prcm = { 1162 .prcm = {
1028 .omap4 = { 1163 .omap4 = {
1029 .clkctrl_offs = DM816X_CM_ALWON_TPTC2_CLKCTRL, 1164 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1030 .modulemode = MODULEMODE_SWCTRL, 1165 .modulemode = MODULEMODE_SWCTRL,
1031 }, 1166 },
1032 }, 1167 },
1033}; 1168};
1034 1169
1035struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2 = { 1170static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1036 .master = &dm816x_alwon_l3_fast_hwmod, 1171 .master = &dm81xx_alwon_l3_fast_hwmod,
1037 .slave = &dm816x_tptc2_hwmod, 1172 .slave = &dm81xx_tptc2_hwmod,
1038 .clk = "sysclk4_ck", 1173 .clk = "sysclk4_ck",
1039 .addr = dm816x_tptc2_addr_space, 1174 .addr = dm81xx_tptc2_addr_space,
1040 .user = OCP_USER_MPU, 1175 .user = OCP_USER_MPU,
1041}; 1176};
1042 1177
1043struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast = { 1178static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1044 .master = &dm816x_tptc2_hwmod, 1179 .master = &dm81xx_tptc2_hwmod,
1045 .slave = &dm816x_alwon_l3_fast_hwmod, 1180 .slave = &dm81xx_alwon_l3_fast_hwmod,
1046 .clk = "sysclk4_ck", 1181 .clk = "sysclk4_ck",
1047 .addr = dm816x_tptc2_addr_space, 1182 .addr = dm81xx_tptc2_addr_space,
1048 .user = OCP_USER_MPU, 1183 .user = OCP_USER_MPU,
1049}; 1184};
1050 1185
1051static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = { 1186static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1052 { 1187 {
1053 .pa_start = 0x49b00000, 1188 .pa_start = 0x49b00000,
1054 .pa_end = 0x49b00000 + SZ_8K - 1, 1189 .pa_end = 0x49b00000 + SZ_8K - 1,
@@ -1057,50 +1192,96 @@ static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = {
1057 { }, 1192 { },
1058}; 1193};
1059 1194
1060static struct omap_hwmod_class dm816x_tptc3_hwmod_class = { 1195static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1061 .name = "tptc3", 1196 .name = "tptc3",
1062}; 1197};
1063 1198
1064struct omap_hwmod dm816x_tptc3_hwmod = { 1199static struct omap_hwmod dm81xx_tptc3_hwmod = {
1065 .name = "tptc3", 1200 .name = "tptc3",
1066 .class = &dm816x_tptc3_hwmod_class, 1201 .class = &dm81xx_tptc3_hwmod_class,
1067 .clkdm_name = "alwon_l3s_clkdm", 1202 .clkdm_name = "alwon_l3s_clkdm",
1068 .main_clk = "sysclk4_ck", 1203 .main_clk = "sysclk4_ck",
1069 .prcm = { 1204 .prcm = {
1070 .omap4 = { 1205 .omap4 = {
1071 .clkctrl_offs = DM816X_CM_ALWON_TPTC3_CLKCTRL, 1206 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1072 .modulemode = MODULEMODE_SWCTRL, 1207 .modulemode = MODULEMODE_SWCTRL,
1073 }, 1208 },
1074 }, 1209 },
1075}; 1210};
1076 1211
1077struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3 = { 1212static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1078 .master = &dm816x_alwon_l3_fast_hwmod, 1213 .master = &dm81xx_alwon_l3_fast_hwmod,
1079 .slave = &dm816x_tptc3_hwmod, 1214 .slave = &dm81xx_tptc3_hwmod,
1080 .clk = "sysclk4_ck", 1215 .clk = "sysclk4_ck",
1081 .addr = dm816x_tptc3_addr_space, 1216 .addr = dm81xx_tptc3_addr_space,
1082 .user = OCP_USER_MPU, 1217 .user = OCP_USER_MPU,
1083}; 1218};
1084 1219
1085struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast = { 1220static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1086 .master = &dm816x_tptc3_hwmod, 1221 .master = &dm81xx_tptc3_hwmod,
1087 .slave = &dm816x_alwon_l3_fast_hwmod, 1222 .slave = &dm81xx_alwon_l3_fast_hwmod,
1088 .clk = "sysclk4_ck", 1223 .clk = "sysclk4_ck",
1089 .addr = dm816x_tptc3_addr_space, 1224 .addr = dm81xx_tptc3_addr_space,
1090 .user = OCP_USER_MPU, 1225 .user = OCP_USER_MPU,
1091}; 1226};
1092 1227
1228/*
1229 * REVISIT: Test and enable the following once clocks work:
1230 * dm81xx_l4_ls__gpio1
1231 * dm81xx_l4_ls__gpio2
1232 * dm81xx_l4_ls__mailbox
1233 * dm81xx_alwon_l3_slow__gpmc
1234 * dm81xx_default_l3_slow__usbss
1235 *
1236 * Also note that some devices share a single clkctrl_offs..
1237 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1238 */
1239static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1240 &dm814x_mpu__alwon_l3_slow,
1241 &dm814x_mpu__alwon_l3_med,
1242 &dm81xx_alwon_l3_slow__l4_ls,
1243 &dm81xx_alwon_l3_slow__l4_hs,
1244 &dm81xx_l4_ls__uart1,
1245 &dm81xx_l4_ls__uart2,
1246 &dm81xx_l4_ls__uart3,
1247 &dm81xx_l4_ls__wd_timer1,
1248 &dm81xx_l4_ls__i2c1,
1249 &dm81xx_l4_ls__i2c2,
1250 &dm81xx_l4_ls__elm,
1251 &dm81xx_l4_ls__mcspi1,
1252 &dm81xx_alwon_l3_fast__tpcc,
1253 &dm81xx_alwon_l3_fast__tptc0,
1254 &dm81xx_alwon_l3_fast__tptc1,
1255 &dm81xx_alwon_l3_fast__tptc2,
1256 &dm81xx_alwon_l3_fast__tptc3,
1257 &dm81xx_tptc0__alwon_l3_fast,
1258 &dm81xx_tptc1__alwon_l3_fast,
1259 &dm81xx_tptc2__alwon_l3_fast,
1260 &dm81xx_tptc3__alwon_l3_fast,
1261 &dm814x_l4_ls__timer1,
1262 &dm814x_l4_ls__timer2,
1263 &dm814x_l4_hs__cpgmac0,
1264 &dm814x_cpgmac0__mdio,
1265 NULL,
1266};
1267
1268int __init dm814x_hwmod_init(void)
1269{
1270 omap_hwmod_init();
1271 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1272}
1273
1093static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1274static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1094 &dm816x_mpu__alwon_l3_slow, 1275 &dm816x_mpu__alwon_l3_slow,
1095 &dm816x_mpu__alwon_l3_med, 1276 &dm816x_mpu__alwon_l3_med,
1096 &dm816x_alwon_l3_slow__l4_ls, 1277 &dm81xx_alwon_l3_slow__l4_ls,
1097 &dm816x_alwon_l3_slow__l4_hs, 1278 &dm81xx_alwon_l3_slow__l4_hs,
1098 &dm816x_l4_ls__uart1, 1279 &dm81xx_l4_ls__uart1,
1099 &dm816x_l4_ls__uart2, 1280 &dm81xx_l4_ls__uart2,
1100 &dm816x_l4_ls__uart3, 1281 &dm81xx_l4_ls__uart3,
1101 &dm816x_l4_ls__wd_timer1, 1282 &dm81xx_l4_ls__wd_timer1,
1102 &dm816x_l4_ls__i2c1, 1283 &dm81xx_l4_ls__i2c1,
1103 &dm816x_l4_ls__i2c2, 1284 &dm81xx_l4_ls__i2c2,
1104 &dm81xx_l4_ls__gpio1, 1285 &dm81xx_l4_ls__gpio1,
1105 &dm81xx_l4_ls__gpio2, 1286 &dm81xx_l4_ls__gpio2,
1106 &dm81xx_l4_ls__elm, 1287 &dm81xx_l4_ls__elm,
@@ -1112,26 +1293,26 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1112 &dm816x_l4_ls__timer5, 1293 &dm816x_l4_ls__timer5,
1113 &dm816x_l4_ls__timer6, 1294 &dm816x_l4_ls__timer6,
1114 &dm816x_l4_ls__timer7, 1295 &dm816x_l4_ls__timer7,
1115 &dm816x_l4_ls__mcspi1, 1296 &dm81xx_l4_ls__mcspi1,
1116 &dm816x_l4_ls__mailbox, 1297 &dm81xx_l4_ls__mailbox,
1117 &dm816x_l4_hs__emac0, 1298 &dm81xx_l4_hs__emac0,
1118 &dm816x_emac0__mdio, 1299 &dm81xx_emac0__mdio,
1119 &dm816x_l4_hs__emac1, 1300 &dm816x_l4_hs__emac1,
1120 &dm816x_alwon_l3_fast__tpcc, 1301 &dm81xx_alwon_l3_fast__tpcc,
1121 &dm816x_alwon_l3_fast__tptc0, 1302 &dm81xx_alwon_l3_fast__tptc0,
1122 &dm816x_alwon_l3_fast__tptc1, 1303 &dm81xx_alwon_l3_fast__tptc1,
1123 &dm816x_alwon_l3_fast__tptc2, 1304 &dm81xx_alwon_l3_fast__tptc2,
1124 &dm816x_alwon_l3_fast__tptc3, 1305 &dm81xx_alwon_l3_fast__tptc3,
1125 &dm816x_tptc0__alwon_l3_fast, 1306 &dm81xx_tptc0__alwon_l3_fast,
1126 &dm816x_tptc1__alwon_l3_fast, 1307 &dm81xx_tptc1__alwon_l3_fast,
1127 &dm816x_tptc2__alwon_l3_fast, 1308 &dm81xx_tptc2__alwon_l3_fast,
1128 &dm816x_tptc3__alwon_l3_fast, 1309 &dm81xx_tptc3__alwon_l3_fast,
1129 &dm81xx_alwon_l3_slow__gpmc, 1310 &dm81xx_alwon_l3_slow__gpmc,
1130 &dm81xx_default_l3_slow__usbss, 1311 &dm81xx_default_l3_slow__usbss,
1131 NULL, 1312 NULL,
1132}; 1313};
1133 1314
1134int __init ti81xx_hwmod_init(void) 1315int __init dm816x_hwmod_init(void)
1135{ 1316{
1136 omap_hwmod_init(); 1317 omap_hwmod_init();
1137 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1318 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 821171cf6b7d..1a352f561113 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -31,7 +31,7 @@ struct pdata_init {
31 void (*fn)(void); 31 void (*fn)(void);
32}; 32};
33 33
34struct of_dev_auxdata omap_auxdata_lookup[]; 34static struct of_dev_auxdata omap_auxdata_lookup[];
35static struct twl4030_gpio_platform_data twl_gpio_auxdata; 35static struct twl4030_gpio_platform_data twl_gpio_auxdata;
36 36
37#ifdef CONFIG_MACH_NOKIA_N8X0 37#ifdef CONFIG_MACH_NOKIA_N8X0
@@ -128,7 +128,7 @@ static void __init omap3_sbc_t3530_legacy_init(void)
128 omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); 128 omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
129} 129}
130 130
131struct ti_st_plat_data wilink_pdata = { 131static struct ti_st_plat_data wilink_pdata = {
132 .nshutdown_gpio = 137, 132 .nshutdown_gpio = 137,
133 .dev_name = "/dev/ttyO1", 133 .dev_name = "/dev/ttyO1",
134 .flow_cntrl = 1, 134 .flow_cntrl = 1,
@@ -323,7 +323,7 @@ static struct pdata_init auxdata_quirks[] __initdata = {
323 { /* sentinel */ }, 323 { /* sentinel */ },
324}; 324};
325 325
326struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { 326static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
327#ifdef CONFIG_MACH_NOKIA_N8X0 327#ifdef CONFIG_MACH_NOKIA_N8X0
328 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), 328 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
329 OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data), 329 OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 70bc7066a4c2..d31c495175c1 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -349,6 +349,41 @@ static struct powerdomain device_81xx_pwrdm = {
349 .voltdm = { .name = "core" }, 349 .voltdm = { .name = "core" },
350}; 350};
351 351
352static struct powerdomain gem_814x_pwrdm = {
353 .name = "gem_pwrdm",
354 .prcm_offs = TI814X_PRM_DSP_MOD,
355 .pwrsts = PWRSTS_OFF_ON,
356 .voltdm = { .name = "dsp" },
357};
358
359static struct powerdomain ivahd_814x_pwrdm = {
360 .name = "ivahd_pwrdm",
361 .prcm_offs = TI814X_PRM_HDVICP_MOD,
362 .pwrsts = PWRSTS_OFF_ON,
363 .voltdm = { .name = "iva" },
364};
365
366static struct powerdomain hdvpss_814x_pwrdm = {
367 .name = "hdvpss_pwrdm",
368 .prcm_offs = TI814X_PRM_HDVPSS_MOD,
369 .pwrsts = PWRSTS_OFF_ON,
370 .voltdm = { .name = "dsp" },
371};
372
373static struct powerdomain sgx_814x_pwrdm = {
374 .name = "sgx_pwrdm",
375 .prcm_offs = TI814X_PRM_GFX_MOD,
376 .pwrsts = PWRSTS_OFF_ON,
377 .voltdm = { .name = "core" },
378};
379
380static struct powerdomain isp_814x_pwrdm = {
381 .name = "isp_pwrdm",
382 .prcm_offs = TI814X_PRM_ISP_MOD,
383 .pwrsts = PWRSTS_OFF_ON,
384 .voltdm = { .name = "core" },
385};
386
352static struct powerdomain active_816x_pwrdm = { 387static struct powerdomain active_816x_pwrdm = {
353 .name = "active_pwrdm", 388 .name = "active_pwrdm",
354 .prcm_offs = TI816X_PRM_ACTIVE_MOD, 389 .prcm_offs = TI816X_PRM_ACTIVE_MOD,
@@ -448,7 +483,18 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
448 NULL 483 NULL
449}; 484};
450 485
451static struct powerdomain *powerdomains_ti81xx[] __initdata = { 486static struct powerdomain *powerdomains_ti814x[] __initdata = {
487 &alwon_81xx_pwrdm,
488 &device_81xx_pwrdm,
489 &gem_814x_pwrdm,
490 &ivahd_814x_pwrdm,
491 &hdvpss_814x_pwrdm,
492 &sgx_814x_pwrdm,
493 &isp_814x_pwrdm,
494 NULL
495};
496
497static struct powerdomain *powerdomains_ti816x[] __initdata = {
452 &alwon_81xx_pwrdm, 498 &alwon_81xx_pwrdm,
453 &device_81xx_pwrdm, 499 &device_81xx_pwrdm,
454 &active_816x_pwrdm, 500 &active_816x_pwrdm,
@@ -460,6 +506,73 @@ static struct powerdomain *powerdomains_ti81xx[] __initdata = {
460 NULL 506 NULL
461}; 507};
462 508
509/* TI81XX specific ops */
510#define TI81XX_PM_PWSTCTRL 0x0000
511#define TI81XX_RM_RSTCTRL 0x0010
512#define TI81XX_PM_PWSTST 0x0004
513
514static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
515{
516 omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
517 (pwrst << OMAP_POWERSTATE_SHIFT),
518 pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
519 return 0;
520}
521
522static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
523{
524 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
525 TI81XX_PM_PWSTCTRL,
526 OMAP_POWERSTATE_MASK);
527}
528
529static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
530{
531 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
532 (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
533 TI81XX_PM_PWSTST,
534 OMAP_POWERSTATEST_MASK);
535}
536
537static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
538{
539 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
540 (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
541 TI81XX_PM_PWSTST,
542 OMAP3430_LOGICSTATEST_MASK);
543}
544
545static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
546{
547 u32 c = 0;
548
549 while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
550 (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
551 TI81XX_PM_PWSTST) &
552 OMAP_INTRANSITION_MASK) &&
553 (c++ < PWRDM_TRANSITION_BAILOUT))
554 udelay(1);
555
556 if (c > PWRDM_TRANSITION_BAILOUT) {
557 pr_err("powerdomain: %s timeout waiting for transition\n",
558 pwrdm->name);
559 return -EAGAIN;
560 }
561
562 pr_debug("powerdomain: completed transition in %d loops\n", c);
563
564 return 0;
565}
566
567/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
568static struct pwrdm_ops ti81xx_pwrdm_operations = {
569 .pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
570 .pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
571 .pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
572 .pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
573 .pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
574};
575
463void __init omap3xxx_powerdomains_init(void) 576void __init omap3xxx_powerdomains_init(void)
464{ 577{
465 unsigned int rev; 578 unsigned int rev;
@@ -467,15 +580,22 @@ void __init omap3xxx_powerdomains_init(void)
467 if (!cpu_is_omap34xx() && !cpu_is_ti81xx()) 580 if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
468 return; 581 return;
469 582
470 pwrdm_register_platform_funcs(&omap3_pwrdm_operations); 583 /* Only 81xx needs custom pwrdm_operations */
584 if (!cpu_is_ti81xx())
585 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);;
471 586
472 rev = omap_rev(); 587 rev = omap_rev();
473 588
474 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 589 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
475 pwrdm_register_pwrdms(powerdomains_am35x); 590 pwrdm_register_pwrdms(powerdomains_am35x);
591 } else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
592 rev == TI8148_REV_ES2_1) {
593 pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
594 pwrdm_register_pwrdms(powerdomains_ti814x);
476 } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1 595 } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
477 || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) { 596 || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
478 pwrdm_register_pwrdms(powerdomains_ti81xx); 597 pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
598 pwrdm_register_pwrdms(powerdomains_ti816x);
479 } else { 599 } else {
480 pwrdm_register_pwrdms(powerdomains_omap3430_common); 600 pwrdm_register_pwrdms(powerdomains_omap3430_common);
481 601
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6ae0b3a1781e..c8f590b7c32d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -51,6 +51,12 @@
51/* 51/*
52 * TI81XX PRM module offsets 52 * TI81XX PRM module offsets
53 */ 53 */
54#define TI814X_PRM_DSP_MOD 0x0a00
55#define TI814X_PRM_HDVICP_MOD 0x0c00
56#define TI814X_PRM_ISP_MOD 0x0d00
57#define TI814X_PRM_HDVPSS_MOD 0x0e00
58#define TI814X_PRM_GFX_MOD 0x0f00
59
54#define TI81XX_PRM_DEVICE_MOD 0x0000 60#define TI81XX_PRM_DEVICE_MOD 0x0000
55#define TI816X_PRM_ACTIVE_MOD 0x0a00 61#define TI816X_PRM_ACTIVE_MOD 0x0a00
56#define TI81XX_PRM_DEFAULT_MOD 0x0b00 62#define TI81XX_PRM_DEFAULT_MOD 0x0b00
@@ -472,6 +478,7 @@ struct omap_prcm_irq {
472 * struct omap_prcm_irq_setup - PRCM interrupt controller details 478 * struct omap_prcm_irq_setup - PRCM interrupt controller details
473 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register 479 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
474 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register 480 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
481 * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register
475 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers 482 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
476 * @nr_irqs: number of entries in the @irqs array 483 * @nr_irqs: number of entries in the @irqs array
477 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) 484 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
@@ -494,6 +501,7 @@ struct omap_prcm_irq {
494struct omap_prcm_irq_setup { 501struct omap_prcm_irq_setup {
495 u16 ack; 502 u16 ack;
496 u16 mask; 503 u16 mask;
504 u16 pm_ctrl;
497 u8 nr_regs; 505 u8 nr_regs;
498 u8 nr_irqs; 506 u8 nr_irqs;
499 const struct omap_prcm_irq *irqs; 507 const struct omap_prcm_irq *irqs;
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7eebc27fa892..7c34c44eb0ae 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -25,6 +25,13 @@
25#define AM43XX_PRM_WKUP_INST 0x2000 25#define AM43XX_PRM_WKUP_INST 0x2000
26#define AM43XX_PRM_DEVICE_INST 0x4000 26#define AM43XX_PRM_DEVICE_INST 0x4000
27 27
28/* PRM_IRQ offsets */
29#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
30#define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
31
32/* Other PRM offsets */
33#define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024
34
28/* RM RSTCTRL offsets */ 35/* RM RSTCTRL offsets */
29#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 36#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
30#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 37#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 4541700f743a..30768003f854 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -18,13 +18,14 @@
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/of_irq.h> 20#include <linux/of_irq.h>
21 21#include <linux/of.h>
22 22
23#include "soc.h" 23#include "soc.h"
24#include "iomap.h" 24#include "iomap.h"
25#include "common.h" 25#include "common.h"
26#include "vp.h" 26#include "vp.h"
27#include "prm44xx.h" 27#include "prm44xx.h"
28#include "prcm43xx.h"
28#include "prm-regbits-44xx.h" 29#include "prm-regbits-44xx.h"
29#include "prcm44xx.h" 30#include "prcm44xx.h"
30#include "prminst44xx.h" 31#include "prminst44xx.h"
@@ -45,6 +46,7 @@ static const struct omap_prcm_irq omap4_prcm_irqs[] = {
45static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { 46static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
46 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, 47 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
47 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, 48 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
49 .pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET,
48 .nr_regs = 2, 50 .nr_regs = 2,
49 .irqs = omap4_prcm_irqs, 51 .irqs = omap4_prcm_irqs,
50 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), 52 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
@@ -216,11 +218,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
216 */ 218 */
217static void omap44xx_prm_read_pending_irqs(unsigned long *events) 219static void omap44xx_prm_read_pending_irqs(unsigned long *events)
218{ 220{
219 events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, 221 int i;
220 OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
221 222
222 events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, 223 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
223 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 224 events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
225 i * 4, omap4_prcm_irq_setup.ack + i * 4);
224} 226}
225 227
226/** 228/**
@@ -250,17 +252,17 @@ static void omap44xx_prm_ocp_barrier(void)
250 */ 252 */
251static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) 253static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
252{ 254{
253 saved_mask[0] = 255 int i;
254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 256 u16 reg;
255 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 257
256 saved_mask[1] = 258 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 259 reg = omap4_prcm_irq_setup.mask + i * 4;
258 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
259 260
260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, 261 saved_mask[i] =
261 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 262 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
262 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, 263 reg);
263 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); 264 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
265 }
264 266
265 /* OCP barrier */ 267 /* OCP barrier */
266 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 268 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
@@ -279,10 +281,12 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
279 */ 281 */
280static void omap44xx_prm_restore_irqen(u32 *saved_mask) 282static void omap44xx_prm_restore_irqen(u32 *saved_mask)
281{ 283{
282 omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, 284 int i;
283 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 285
284 omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST, 286 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
285 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); 287 omap4_prm_write_inst_reg(saved_mask[i],
288 OMAP4430_PRM_OCP_SOCKET_INST,
289 omap4_prcm_irq_setup.mask + i * 4);
286} 290}
287 291
288/** 292/**
@@ -306,10 +310,10 @@ static void omap44xx_prm_reconfigure_io_chain(void)
306 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 310 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
307 OMAP4430_WUCLK_CTRL_MASK, 311 OMAP4430_WUCLK_CTRL_MASK,
308 inst, 312 inst,
309 OMAP4_PRM_IO_PMCTRL_OFFSET); 313 omap4_prcm_irq_setup.pm_ctrl);
310 omap_test_timeout( 314 omap_test_timeout(
311 (((omap4_prm_read_inst_reg(inst, 315 (((omap4_prm_read_inst_reg(inst,
312 OMAP4_PRM_IO_PMCTRL_OFFSET) & 316 omap4_prcm_irq_setup.pm_ctrl) &
313 OMAP4430_WUCLK_STATUS_MASK) >> 317 OMAP4430_WUCLK_STATUS_MASK) >>
314 OMAP4430_WUCLK_STATUS_SHIFT) == 1), 318 OMAP4430_WUCLK_STATUS_SHIFT) == 1),
315 MAX_IOPAD_LATCH_TIME, i); 319 MAX_IOPAD_LATCH_TIME, i);
@@ -319,10 +323,10 @@ static void omap44xx_prm_reconfigure_io_chain(void)
319 /* Trigger WUCLKIN disable */ 323 /* Trigger WUCLKIN disable */
320 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, 324 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
321 inst, 325 inst,
322 OMAP4_PRM_IO_PMCTRL_OFFSET); 326 omap4_prcm_irq_setup.pm_ctrl);
323 omap_test_timeout( 327 omap_test_timeout(
324 (((omap4_prm_read_inst_reg(inst, 328 (((omap4_prm_read_inst_reg(inst,
325 OMAP4_PRM_IO_PMCTRL_OFFSET) & 329 omap4_prcm_irq_setup.pm_ctrl) &
326 OMAP4430_WUCLK_STATUS_MASK) >> 330 OMAP4430_WUCLK_STATUS_MASK) >>
327 OMAP4430_WUCLK_STATUS_SHIFT) == 0), 331 OMAP4430_WUCLK_STATUS_SHIFT) == 0),
328 MAX_IOPAD_LATCH_TIME, i); 332 MAX_IOPAD_LATCH_TIME, i);
@@ -350,7 +354,7 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
350 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, 354 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
351 OMAP4430_GLOBAL_WUEN_MASK, 355 OMAP4430_GLOBAL_WUEN_MASK,
352 inst, 356 inst,
353 OMAP4_PRM_IO_PMCTRL_OFFSET); 357 omap4_prcm_irq_setup.pm_ctrl);
354} 358}
355 359
356/** 360/**
@@ -719,6 +723,15 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
719 723
720 omap4_prminst_set_prm_dev_inst(data->device_inst_offset); 724 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
721 725
726 /* Add AM437X specific differences */
727 if (of_device_is_compatible(data->np, "ti,am4-prcm")) {
728 omap4_prcm_irq_setup.nr_irqs = 1;
729 omap4_prcm_irq_setup.nr_regs = 1;
730 omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET;
731 omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET;
732 omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
733 }
734
722 return prm_register(&omap44xx_prm_ll_data); 735 return prm_register(&omap44xx_prm_ll_data);
723} 736}
724 737
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index f62f8326aa5f..257e98c26618 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -696,6 +696,7 @@ static struct omap_prcm_init_data am4_prm_data __initdata = {
696 .index = TI_CLKM_PRM, 696 .index = TI_CLKM_PRM,
697 .init = omap44xx_prm_init, 697 .init = omap44xx_prm_init,
698 .device_inst_offset = AM43XX_PRM_DEVICE_INST, 698 .device_inst_offset = AM43XX_PRM_DEVICE_INST,
699 .flags = PRM_HAS_IO_WAKEUP,
699}; 700};
700#endif 701#endif
701 702
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 16b37e7196f5..e4d8701f99f9 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -208,8 +208,7 @@ static void __init omap_dmtimer_init(void)
208 /* If we are a secure device, remove any secure timer nodes */ 208 /* If we are a secure device, remove any secure timer nodes */
209 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 209 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
210 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 210 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
211 if (np) 211 of_node_put(np);
212 of_node_put(np);
213 } 212 }
214} 213}
215 214
@@ -649,23 +648,10 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
649 648
650#ifdef CONFIG_ARCH_OMAP4 649#ifdef CONFIG_ARCH_OMAP4
651#ifdef CONFIG_HAVE_ARM_TWD 650#ifdef CONFIG_HAVE_ARM_TWD
652static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
653void __init omap4_local_timer_init(void) 651void __init omap4_local_timer_init(void)
654{ 652{
655 omap4_sync32k_timer_init(); 653 omap4_sync32k_timer_init();
656 /* Local timers are not supprted on OMAP4430 ES1.0 */ 654 clocksource_of_init();
657 if (omap_rev() != OMAP4430_REV_ES1_0) {
658 int err;
659
660 if (of_have_populated_dt()) {
661 clocksource_of_init();
662 return;
663 }
664
665 err = twd_local_timer_register(&twd_local_timer);
666 if (err)
667 pr_err("twd_local_timer_register failed %d\n", err);
668 }
669} 655}
670#else 656#else
671void __init omap4_local_timer_init(void) 657void __init omap4_local_timer_init(void)
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 35434662dc7c..e6ce669b54af 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -17,6 +17,7 @@
17#include <linux/platform_data/camera-pxa.h> 17#include <linux/platform_data/camera-pxa.h>
18#include <mach/audio.h> 18#include <mach/audio.h>
19#include <mach/hardware.h> 19#include <mach/hardware.h>
20#include <linux/platform_data/mmp_dma.h>
20#include <linux/platform_data/mtd-nand-pxa3xx.h> 21#include <linux/platform_data/mtd-nand-pxa3xx.h>
21 22
22#include "devices.h" 23#include "devices.h"
@@ -1193,3 +1194,39 @@ void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1193 pd->dev.platform_data = info; 1194 pd->dev.platform_data = info;
1194 platform_device_add(pd); 1195 platform_device_add(pd);
1195} 1196}
1197
1198static struct mmp_dma_platdata pxa_dma_pdata = {
1199 .dma_channels = 0,
1200};
1201
1202static struct resource pxa_dma_resource[] = {
1203 [0] = {
1204 .start = 0x40000000,
1205 .end = 0x4000ffff,
1206 .flags = IORESOURCE_MEM,
1207 },
1208 [1] = {
1209 .start = IRQ_DMA,
1210 .end = IRQ_DMA,
1211 .flags = IORESOURCE_IRQ,
1212 },
1213};
1214
1215static u64 pxadma_dmamask = 0xffffffffUL;
1216
1217static struct platform_device pxa2xx_pxa_dma = {
1218 .name = "pxa-dma",
1219 .id = 0,
1220 .dev = {
1221 .dma_mask = &pxadma_dmamask,
1222 .coherent_dma_mask = 0xffffffff,
1223 },
1224 .num_resources = ARRAY_SIZE(pxa_dma_resource),
1225 .resource = pxa_dma_resource,
1226};
1227
1228void __init pxa2xx_set_dmac_info(int nb_channels)
1229{
1230 pxa_dma_pdata.dma_channels = nb_channels;
1231 pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
1232}
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 23a90c62ec11..1dc85ffc3e20 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -206,6 +206,7 @@ static int __init pxa25x_init(void)
206 register_syscore_ops(&pxa_irq_syscore_ops); 206 register_syscore_ops(&pxa_irq_syscore_ops);
207 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 207 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
208 208
209 pxa2xx_set_dmac_info(16);
209 pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); 210 pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
210 ret = platform_add_devices(pxa25x_devices, 211 ret = platform_add_devices(pxa25x_devices,
211 ARRAY_SIZE(pxa25x_devices)); 212 ARRAY_SIZE(pxa25x_devices));
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index b5abdeb5bb2d..e6aae9e8adfb 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -310,6 +310,7 @@ static int __init pxa27x_init(void)
310 if (!of_have_populated_dt()) { 310 if (!of_have_populated_dt()) {
311 pxa_register_device(&pxa27x_device_gpio, 311 pxa_register_device(&pxa27x_device_gpio,
312 &pxa27x_gpio_info); 312 &pxa27x_gpio_info);
313 pxa2xx_set_dmac_info(32);
313 ret = platform_add_devices(devices, 314 ret = platform_add_devices(devices,
314 ARRAY_SIZE(devices)); 315 ARRAY_SIZE(devices));
315 } 316 }
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index e1362c0eeafc..165638462a2f 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -431,6 +431,7 @@ static int __init pxa3xx_init(void)
431 if (of_have_populated_dt()) 431 if (of_have_populated_dt())
432 return 0; 432 return 0;
433 433
434 pxa2xx_set_dmac_info(32);
434 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 435 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
435 if (ret) 436 if (ret)
436 return ret; 437 return ret;
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 051a6555cbf9..bdc0c41bc4fd 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -841,11 +841,9 @@ static int sharpsl_pm_probe(struct platform_device *pdev)
841 sharpsl_pm.charge_mode = CHRG_OFF; 841 sharpsl_pm.charge_mode = CHRG_OFF;
842 sharpsl_pm.flags = 0; 842 sharpsl_pm.flags = 0;
843 843
844 init_timer(&sharpsl_pm.ac_timer); 844 setup_timer(&sharpsl_pm.ac_timer, sharpsl_ac_timer, 0UL);
845 sharpsl_pm.ac_timer.function = sharpsl_ac_timer;
846 845
847 init_timer(&sharpsl_pm.chrg_full_timer); 846 setup_timer(&sharpsl_pm.chrg_full_timer, sharpsl_chrg_full_timer, 0UL);
848 sharpsl_pm.chrg_full_timer.function = sharpsl_chrg_full_timer;
849 847
850 led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger); 848 led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
851 849
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index 685deff861d2..e0a53208880a 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -131,17 +131,4 @@ static struct platform_driver tosa_bt_driver = {
131 .name = "tosa-bt", 131 .name = "tosa-bt",
132 }, 132 },
133}; 133};
134 134module_platform_driver(tosa_bt_driver);
135
136static int __init tosa_bt_init(void)
137{
138 return platform_driver_register(&tosa_bt_driver);
139}
140
141static void __exit tosa_bt_exit(void)
142{
143 platform_driver_unregister(&tosa_bt_driver);
144}
145
146module_init(tosa_bt_init);
147module_exit(tosa_bt_exit);
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 8fcec1cc101e..3e7a4b761a95 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -72,29 +72,22 @@ static struct reset_control *rockchip_get_core_reset(int cpu)
72static int pmu_set_power_domain(int pd, bool on) 72static int pmu_set_power_domain(int pd, bool on)
73{ 73{
74 u32 val = (on) ? 0 : BIT(pd); 74 u32 val = (on) ? 0 : BIT(pd);
75 struct reset_control *rstc = rockchip_get_core_reset(pd);
75 int ret; 76 int ret;
76 77
78 if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
79 pr_err("%s: could not get reset control for core %d\n",
80 __func__, pd);
81 return PTR_ERR(rstc);
82 }
83
77 /* 84 /*
78 * We need to soft reset the cpu when we turn off the cpu power domain, 85 * We need to soft reset the cpu when we turn off the cpu power domain,
79 * or else the active processors might be stalled when the individual 86 * or else the active processors might be stalled when the individual
80 * processor is powered down. 87 * processor is powered down.
81 */ 88 */
82 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 89 if (!IS_ERR(rstc) && !on)
83 struct reset_control *rstc = rockchip_get_core_reset(pd); 90 reset_control_assert(rstc);
84
85 if (IS_ERR(rstc)) {
86 pr_err("%s: could not get reset control for core %d\n",
87 __func__, pd);
88 return PTR_ERR(rstc);
89 }
90
91 if (on)
92 reset_control_deassert(rstc);
93 else
94 reset_control_assert(rstc);
95
96 reset_control_put(rstc);
97 }
98 91
99 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); 92 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
100 if (ret < 0) { 93 if (ret < 0) {
@@ -107,11 +100,17 @@ static int pmu_set_power_domain(int pd, bool on)
107 ret = pmu_power_domain_is_on(pd); 100 ret = pmu_power_domain_is_on(pd);
108 if (ret < 0) { 101 if (ret < 0) {
109 pr_err("%s: could not read power domain state\n", 102 pr_err("%s: could not read power domain state\n",
110 __func__); 103 __func__);
111 return ret; 104 return ret;
112 } 105 }
113 } 106 }
114 107
108 if (!IS_ERR(rstc)) {
109 if (on)
110 reset_control_deassert(rstc);
111 reset_control_put(rstc);
112 }
113
115 return 0; 114 return 0;
116} 115}
117 116
@@ -130,7 +129,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
130 129
131 if (cpu >= ncores) { 130 if (cpu >= ncores) {
132 pr_err("%s: cpu %d outside maximum number of cpus %d\n", 131 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
133 __func__, cpu, ncores); 132 __func__, cpu, ncores);
134 return -ENXIO; 133 return -ENXIO;
135 } 134 }
136 135
@@ -140,14 +139,19 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
140 return ret; 139 return ret;
141 140
142 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { 141 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
143 /* We communicate with the bootrom to active the cpus other 142 /*
143 * We communicate with the bootrom to active the cpus other
144 * than cpu0, after a blob of initialize code, they will 144 * than cpu0, after a blob of initialize code, they will
145 * stay at wfe state, once they are actived, they will check 145 * stay at wfe state, once they are actived, they will check
146 * the mailbox: 146 * the mailbox:
147 * sram_base_addr + 4: 0xdeadbeaf 147 * sram_base_addr + 4: 0xdeadbeaf
148 * sram_base_addr + 8: start address for pc 148 * sram_base_addr + 8: start address for pc
149 * */ 149 * The cpu0 need to wait the other cpus other than cpu0 entering
150 udelay(10); 150 * the wfe state.The wait time is affected by many aspects.
151 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
152 */
153 mdelay(1); /* ensure the cpus other than cpu0 to startup */
154
151 writel(virt_to_phys(secondary_startup), sram_base_addr + 8); 155 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
152 writel(0xDEADBEAF, sram_base_addr + 4); 156 writel(0xDEADBEAF, sram_base_addr + 4);
153 dsb_sev(); 157 dsb_sev();
@@ -317,6 +321,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
317#ifdef CONFIG_HOTPLUG_CPU 321#ifdef CONFIG_HOTPLUG_CPU
318static int rockchip_cpu_kill(unsigned int cpu) 322static int rockchip_cpu_kill(unsigned int cpu)
319{ 323{
324 /*
325 * We need a delay here to ensure that the dying CPU can finish
326 * executing v7_coherency_exit() and reach the WFI/WFE state
327 * prior to having the power domain disabled.
328 */
329 mdelay(1);
330
320 pmu_set_power_domain(0 + cpu, false); 331 pmu_set_power_domain(0 + cpu, false);
321 return 1; 332 return 1;
322} 333}
@@ -324,7 +335,7 @@ static int rockchip_cpu_kill(unsigned int cpu)
324static void rockchip_cpu_die(unsigned int cpu) 335static void rockchip_cpu_die(unsigned int cpu)
325{ 336{
326 v7_exit_coherency_flush(louis); 337 v7_exit_coherency_flush(louis);
327 while(1) 338 while (1)
328 cpu_do_idle(); 339 cpu_do_idle();
329} 340}
330#endif 341#endif
@@ -337,4 +348,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
337 .cpu_die = rockchip_cpu_die, 348 .cpu_die = rockchip_cpu_die,
338#endif 349#endif
339}; 350};
351
340CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); 352CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index b0dcbe28f78c..bee8c8051929 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -45,9 +45,11 @@ static phys_addr_t rk3288_bootram_phy;
45 45
46static struct regmap *pmu_regmap; 46static struct regmap *pmu_regmap;
47static struct regmap *sgrf_regmap; 47static struct regmap *sgrf_regmap;
48static struct regmap *grf_regmap;
48 49
49static u32 rk3288_pmu_pwr_mode_con; 50static u32 rk3288_pmu_pwr_mode_con;
50static u32 rk3288_sgrf_soc_con0; 51static u32 rk3288_sgrf_soc_con0;
52static u32 rk3288_sgrf_cpu_con0;
51 53
52static inline u32 rk3288_l2_config(void) 54static inline u32 rk3288_l2_config(void)
53{ 55{
@@ -66,10 +68,37 @@ static void rk3288_config_bootdata(void)
66 rkpm_bootdata_l2ctlr = rk3288_l2_config(); 68 rkpm_bootdata_l2ctlr = rk3288_l2_config();
67} 69}
68 70
71#define GRF_UOC0_CON0 0x320
72#define GRF_UOC1_CON0 0x334
73#define GRF_UOC2_CON0 0x348
74#define GRF_SIDDQ BIT(13)
75
76static bool rk3288_slp_disable_osc(void)
77{
78 static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
79 GRF_UOC2_CON0 };
80 u32 reg, i;
81
82 /*
83 * if any usb phy is still on(GRF_SIDDQ==0), that means we need the
84 * function of usb wakeup, so do not switch to 32khz, since the usb phy
85 * clk does not connect to 32khz osc
86 */
87 for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
88 regmap_read(grf_regmap, reg_offset[i], &reg);
89 if (!(reg & GRF_SIDDQ))
90 return false;
91 }
92
93 return true;
94}
95
69static void rk3288_slp_mode_set(int level) 96static void rk3288_slp_mode_set(int level)
70{ 97{
71 u32 mode_set, mode_set1; 98 u32 mode_set, mode_set1;
99 bool osc_disable = rk3288_slp_disable_osc();
72 100
101 regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
73 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); 102 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
74 103
75 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 104 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
@@ -94,9 +123,6 @@ static void rk3288_slp_mode_set(int level)
94 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, 123 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
95 rk3288_bootram_phy); 124 rk3288_bootram_phy);
96 125
97 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
98 PMU_ARMINT_WAKEUP_EN);
99
100 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | 126 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
101 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | 127 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
102 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | 128 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
@@ -107,13 +133,31 @@ static void rk3288_slp_mode_set(int level)
107 133
108 if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { 134 if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
109 /* arm off, logic deep sleep */ 135 /* arm off, logic deep sleep */
110 mode_set |= BIT(PMU_BUS_PD_EN) | 136 mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
111 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | 137 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
112 BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
113 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); 138 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
114 139
140 if (osc_disable)
141 mode_set |= BIT(PMU_OSC_24M_DIS);
142
115 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | 143 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
116 BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); 144 BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
145
146 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
147 PMU_ARMINT_WAKEUP_EN);
148
149 /*
150 * In deep suspend we use PMU_PMU_USE_LF to let the rk3288
151 * switch its main clock supply to the alternative 32kHz
152 * source. Therefore set 30ms on a 32kHz clock for pmic
153 * stabilization. Similar 30ms on 24MHz for the other
154 * mode below.
155 */
156 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
157
158 /* only wait for stabilization, if we turned the osc off */
159 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
160 osc_disable ? 32 * 30 : 0);
117 } else { 161 } else {
118 /* 162 /*
119 * arm off, logic normal 163 * arm off, logic normal
@@ -121,6 +165,15 @@ static void rk3288_slp_mode_set(int level)
121 * wakeup will be error 165 * wakeup will be error
122 */ 166 */
123 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); 167 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
168
169 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
170 PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
171
172 /* 30ms on a 24MHz clock for pmic stabilization */
173 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
174
175 /* oscillator is still running, so no need to wait */
176 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
124 } 177 }
125 178
126 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); 179 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
@@ -129,6 +182,9 @@ static void rk3288_slp_mode_set(int level)
129 182
130static void rk3288_slp_mode_set_resume(void) 183static void rk3288_slp_mode_set_resume(void)
131{ 184{
185 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
186 rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
187
132 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, 188 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
133 rk3288_pmu_pwr_mode_con); 189 rk3288_pmu_pwr_mode_con);
134 190
@@ -190,7 +246,14 @@ static int rk3288_suspend_init(struct device_node *np)
190 "rockchip,rk3288-sgrf"); 246 "rockchip,rk3288-sgrf");
191 if (IS_ERR(sgrf_regmap)) { 247 if (IS_ERR(sgrf_regmap)) {
192 pr_err("%s: could not find sgrf regmap\n", __func__); 248 pr_err("%s: could not find sgrf regmap\n", __func__);
193 return PTR_ERR(pmu_regmap); 249 return PTR_ERR(sgrf_regmap);
250 }
251
252 grf_regmap = syscon_regmap_lookup_by_compatible(
253 "rockchip,rk3288-grf");
254 if (IS_ERR(grf_regmap)) {
255 pr_err("%s: could not find grf regmap\n", __func__);
256 return PTR_ERR(grf_regmap);
194 } 257 }
195 258
196 sram_np = of_find_compatible_node(NULL, NULL, 259 sram_np = of_find_compatible_node(NULL, NULL,
@@ -221,9 +284,6 @@ static int rk3288_suspend_init(struct device_node *np)
221 memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, 284 memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
222 rk3288_bootram_sz); 285 rk3288_bootram_sz);
223 286
224 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
225 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
226
227 return 0; 287 return 0;
228} 288}
229 289
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 3e8d39c0c3d5..b5af26f8336e 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -59,19 +59,9 @@ static inline void rockchip_suspend_init(void)
59#define SGRF_DAPDEVICEEN BIT(0) 59#define SGRF_DAPDEVICEEN BIT(0)
60#define SGRF_DAPDEVICEEN_WRITE BIT(16) 60#define SGRF_DAPDEVICEEN_WRITE BIT(16)
61 61
62#define RK3288_CRU_MODE_CON 0x50
63#define RK3288_CRU_SEL0_CON 0x60
64#define RK3288_CRU_SEL1_CON 0x64
65#define RK3288_CRU_SEL10_CON 0x88
66#define RK3288_CRU_SEL33_CON 0xe4
67#define RK3288_CRU_SEL37_CON 0xf4
68
69/* PMU_WAKEUP_CFG1 bits */ 62/* PMU_WAKEUP_CFG1 bits */
70#define PMU_ARMINT_WAKEUP_EN BIT(0) 63#define PMU_ARMINT_WAKEUP_EN BIT(0)
71 64#define PMU_GPIOINT_WAKEUP_EN BIT(3)
72/* wait 30ms for OSC stable and 30ms for pmic stable */
73#define OSC_STABL_CNT_THRESH (32 * 30)
74#define PMU_STABL_CNT_THRESH (32 * 30)
75 65
76enum rk3288_pwr_mode_con { 66enum rk3288_pwr_mode_con {
77 PMU_PWR_MODE_EN = 0, 67 PMU_PWR_MODE_EN = 0,
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 26505d4efa80..aa38a438af89 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -80,6 +80,11 @@ config ARCH_R8A7791
80 select ARCH_RCAR_GEN2 80 select ARCH_RCAR_GEN2
81 select I2C 81 select I2C
82 82
83config ARCH_R8A7793
84 bool "R-Car M2-N (R8A7793)"
85 select ARCH_RCAR_GEN2
86 select I2C
87
83config ARCH_R8A7794 88config ARCH_R8A7794
84 bool "R-Car E2 (R8A77940)" 89 bool "R-Car E2 (R8A77940)"
85 select ARCH_RCAR_GEN2 90 select ARCH_RCAR_GEN2
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 9fd0fac92dd1..476de30798d7 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
13obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o 13obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
14obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o 14obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
15obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o 15obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o
16obj-$(CONFIG_ARCH_R8A7793) += setup-r8a7793.o
16obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o 17obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o
17obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 18obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
18obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 19obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
@@ -31,6 +32,7 @@ obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
31CFLAGS_setup-rcar-gen2.o += -march=armv7-a 32CFLAGS_setup-rcar-gen2.o += -march=armv7-a
32obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o 33obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o
33obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o 34obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o
35obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o
34 36
35# SMP objects 37# SMP objects
36smp-y := $(cpu-y) 38smp-y := $(cpu-y)
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index 384e6e934b87..62437b57813e 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -123,7 +123,8 @@ static int __init rcar_gen2_regulator_quirk(void)
123 u32 mon; 123 u32 mon;
124 124
125 if (!of_machine_is_compatible("renesas,koelsch") && 125 if (!of_machine_is_compatible("renesas,koelsch") &&
126 !of_machine_is_compatible("renesas,lager")) 126 !of_machine_is_compatible("renesas,lager") &&
127 !of_machine_is_compatible("renesas,gose"))
127 return -ENODEV; 128 return -ENODEV;
128 129
129 irqc = ioremap(IRQC_BASE, PAGE_SIZE); 130 irqc = ioremap(IRQC_BASE, PAGE_SIZE);
diff --git a/arch/arm/mach-shmobile/setup-r8a7793.c b/arch/arm/mach-shmobile/setup-r8a7793.c
new file mode 100644
index 000000000000..1d2825cb7a65
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7793.c
@@ -0,0 +1,33 @@
1/*
2 * r8a7793 processor support
3 *
4 * Copyright (C) 2015 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/init.h>
17#include <asm/mach/arch.h>
18
19#include "common.h"
20#include "rcar-gen2.h"
21
22static const char *r8a7793_boards_compat_dt[] __initconst = {
23 "renesas,r8a7793",
24 NULL,
25};
26
27DT_MACHINE_START(R8A7793_DT, "Generic R8A7793 (Flattened Device Tree)")
28 .init_early = shmobile_init_delay,
29 .init_time = rcar_gen2_timer_init,
30 .init_late = shmobile_init_late,
31 .reserve = rcar_gen2_reserve,
32 .dt_compat = r8a7793_boards_compat_dt,
33MACHINE_END
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 7259c3732702..5bc6ea87cdf7 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,7 @@
25#define SOCFPGA_RSTMGR_MODPERRST 0x14 25#define SOCFPGA_RSTMGR_MODPERRST 0x14
26#define SOCFPGA_RSTMGR_BRGMODRST 0x1c 26#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
27 27
28#define SOCFPGA_A10_RSTMGR_CTRL 0xC
28#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 29#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
29 30
30/* System Manager bits */ 31/* System Manager bits */
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index c6f1df89f9af..15c8ce8965f4 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -106,11 +106,23 @@ static void socfpga_cpu_die(unsigned int cpu)
106 cpu_do_idle(); 106 cpu_do_idle();
107} 107}
108 108
109/*
110 * We need a dummy function so that platform_can_cpu_hotplug() knows
111 * we support CPU hotplug. However, the function does not need to do
112 * anything, because CPUs going offline just do WFI. We could reset
113 * the CPUs but it would increase power consumption.
114 */
115static int socfpga_cpu_kill(unsigned int cpu)
116{
117 return 1;
118}
119
109static struct smp_operations socfpga_smp_ops __initdata = { 120static struct smp_operations socfpga_smp_ops __initdata = {
110 .smp_prepare_cpus = socfpga_smp_prepare_cpus, 121 .smp_prepare_cpus = socfpga_smp_prepare_cpus,
111 .smp_boot_secondary = socfpga_boot_secondary, 122 .smp_boot_secondary = socfpga_boot_secondary,
112#ifdef CONFIG_HOTPLUG_CPU 123#ifdef CONFIG_HOTPLUG_CPU
113 .cpu_die = socfpga_cpu_die, 124 .cpu_die = socfpga_cpu_die,
125 .cpu_kill = socfpga_cpu_kill,
114#endif 126#endif
115}; 127};
116 128
@@ -119,6 +131,7 @@ static struct smp_operations socfpga_a10_smp_ops __initdata = {
119 .smp_boot_secondary = socfpga_a10_boot_secondary, 131 .smp_boot_secondary = socfpga_a10_boot_secondary,
120#ifdef CONFIG_HOTPLUG_CPU 132#ifdef CONFIG_HOTPLUG_CPU
121 .cpu_die = socfpga_cpu_die, 133 .cpu_die = socfpga_cpu_die,
134 .cpu_kill = socfpga_cpu_kill,
122#endif 135#endif
123}; 136};
124 137
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 19643a756c48..a1c0efaa8794 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -74,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
74 writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); 74 writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
75} 75}
76 76
77static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
78{
79 u32 temp;
80
81 temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
82
83 if (mode == REBOOT_HARD)
84 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
85 else
86 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
87 writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
88}
89
77static const char *altera_dt_match[] = { 90static const char *altera_dt_match[] = {
78 "altr,socfpga", 91 "altr,socfpga",
79 NULL 92 NULL
@@ -86,3 +99,16 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
86 .restart = socfpga_cyclone5_restart, 99 .restart = socfpga_cyclone5_restart,
87 .dt_compat = altera_dt_match, 100 .dt_compat = altera_dt_match,
88MACHINE_END 101MACHINE_END
102
103static const char *altera_a10_dt_match[] = {
104 "altr,socfpga-arria10",
105 NULL
106};
107
108DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
109 .l2c_aux_val = 0,
110 .l2c_aux_mask = ~0,
111 .init_irq = socfpga_init_irq,
112 .restart = socfpga_arria10_restart,
113 .dt_compat = altera_a10_dt_match,
114MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
index 4c09bae86edf..e0ad451700d5 100644
--- a/arch/arm/mach-sti/headsmp.S
+++ b/arch/arm/mach-sti/headsmp.S
@@ -37,6 +37,7 @@ pen: ldr r7, [r6]
37 * should now contain the SVC stack for this core 37 * should now contain the SVC stack for this core
38 */ 38 */
39 b secondary_startup 39 b secondary_startup
40ENDPROC(sti_secondary_startup)
40 41
411: .long . 421: .long .
42 .long pen_release 43 .long pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index d4b624f8dfcb..c4ad6eae67fa 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/memblock.h>
23 24
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25#include <asm/smp_plat.h> 26#include <asm/smp_plat.h>
@@ -38,8 +39,6 @@ static DEFINE_SPINLOCK(boot_lock);
38 39
39static void sti_secondary_init(unsigned int cpu) 40static void sti_secondary_init(unsigned int cpu)
40{ 41{
41 trace_hardirqs_off();
42
43 /* 42 /*
44 * let the primary processor know we're out of the 43 * let the primary processor know we're out of the
45 * pen, then head off into the C entry point 44 * pen, then head off into the C entry point
@@ -99,14 +98,62 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
99 98
100static void __init sti_smp_prepare_cpus(unsigned int max_cpus) 99static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
101{ 100{
102 void __iomem *scu_base = NULL; 101 struct device_node *np;
103 struct device_node *np = of_find_compatible_node( 102 void __iomem *scu_base;
104 NULL, NULL, "arm,cortex-a9-scu"); 103 u32 __iomem *cpu_strt_ptr;
104 u32 release_phys;
105 int cpu;
106 unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
107
108 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
109
105 if (np) { 110 if (np) {
106 scu_base = of_iomap(np, 0); 111 scu_base = of_iomap(np, 0);
107 scu_enable(scu_base); 112 scu_enable(scu_base);
108 of_node_put(np); 113 of_node_put(np);
109 } 114 }
115
116 if (max_cpus <= 1)
117 return;
118
119 for_each_possible_cpu(cpu) {
120
121 np = of_get_cpu_node(cpu, NULL);
122
123 if (!np)
124 continue;
125
126 if (of_property_read_u32(np, "cpu-release-addr",
127 &release_phys)) {
128 pr_err("CPU %d: missing or invalid cpu-release-addr "
129 "property\n", cpu);
130 continue;
131 }
132
133 /*
134 * holding pen is usually configured in SBC DMEM but can also be
135 * in RAM.
136 */
137
138 if (!memblock_is_memory(release_phys))
139 cpu_strt_ptr =
140 ioremap(release_phys, sizeof(release_phys));
141 else
142 cpu_strt_ptr =
143 (u32 __iomem *)phys_to_virt(release_phys);
144
145 __raw_writel(entry_pa, cpu_strt_ptr);
146
147 /*
148 * wmb so that data is actually written
149 * before cache flush is done
150 */
151 smp_wmb();
152 sync_cache_w(cpu_strt_ptr);
153
154 if (!memblock_is_memory(release_phys))
155 iounmap(cpu_strt_ptr);
156 }
110} 157}
111 158
112struct smp_operations __initdata sti_smp_ops = { 159struct smp_operations __initdata sti_smp_ops = {
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
index 1871b72b1a7e..ae22707d301f 100644
--- a/arch/arm/mach-sti/smp.h
+++ b/arch/arm/mach-sti/smp.h
@@ -14,4 +14,6 @@
14 14
15extern struct smp_operations sti_smp_ops; 15extern struct smp_operations sti_smp_ops;
16 16
17void sti_secondary_startup(void);
18
17#endif 19#endif
diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c
index 5943e1cb7fe1..4b784f721135 100644
--- a/arch/arm/mach-uniphier/platsmp.c
+++ b/arch/arm/mach-uniphier/platsmp.c
@@ -60,12 +60,6 @@ err:
60 sbcm_regmap = NULL; 60 sbcm_regmap = NULL;
61} 61}
62 62
63static void __naked uniphier_secondary_startup(void)
64{
65 asm("bl v7_invalidate_l1\n"
66 "b secondary_startup\n");
67};
68
69static int uniphier_boot_secondary(unsigned int cpu, 63static int uniphier_boot_secondary(unsigned int cpu,
70 struct task_struct *idle) 64 struct task_struct *idle)
71{ 65{
@@ -75,7 +69,7 @@ static int uniphier_boot_secondary(unsigned int cpu,
75 return -ENODEV; 69 return -ENODEV;
76 70
77 ret = regmap_write(sbcm_regmap, 0x1208, 71 ret = regmap_write(sbcm_regmap, 0x1208,
78 virt_to_phys(uniphier_secondary_startup)); 72 virt_to_phys(secondary_startup));
79 if (!ret) 73 if (!ret)
80 asm("sev"); /* wake up secondary CPU */ 74 asm("sev"); /* wake up secondary CPU */
81 75
diff --git a/arch/arm/mach-zx/Kconfig b/arch/arm/mach-zx/Kconfig
index 2a910dc0d15e..7fdc5bf24f9b 100644
--- a/arch/arm/mach-zx/Kconfig
+++ b/arch/arm/mach-zx/Kconfig
@@ -13,6 +13,7 @@ config SOC_ZX296702
13 select ARM_GLOBAL_TIMER 13 select ARM_GLOBAL_TIMER
14 select HAVE_ARM_SCU if SMP 14 select HAVE_ARM_SCU if SMP
15 select HAVE_ARM_TWD if SMP 15 select HAVE_ARM_TWD if SMP
16 select PM_GENERIC_DOMAINS
16 help 17 help
17 Support for ZTE ZX296702 SoC which is a dual core CortexA9MP 18 Support for ZTE ZX296702 SoC which is a dual core CortexA9MP
18endif 19endif
diff --git a/arch/arm/mach-zx/Makefile b/arch/arm/mach-zx/Makefile
index 7c2edf6e5f8b..a4b486433209 100644
--- a/arch/arm/mach-zx/Makefile
+++ b/arch/arm/mach-zx/Makefile
@@ -1,2 +1,2 @@
1obj-$(CONFIG_SOC_ZX296702) += zx296702.o 1obj-$(CONFIG_SOC_ZX296702) += zx296702.o zx296702-pm-domain.o
2obj-$(CONFIG_SMP) += headsmp.o platsmp.o 2obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-zx/zx296702-pm-domain.c b/arch/arm/mach-zx/zx296702-pm-domain.c
new file mode 100644
index 000000000000..e08574d4e2ca
--- /dev/null
+++ b/arch/arm/mach-zx/zx296702-pm-domain.c
@@ -0,0 +1,202 @@
1/*
2 * Copyright (C) 2015 Linaro Ltd.
3 *
4 * Author: Jun Nie <jun.nie@linaro.org>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pm_domain.h>
13#include <linux/slab.h>
14
15#define PCU_DM_CLKEN 0x18
16#define PCU_DM_RSTEN 0x1C
17#define PCU_DM_ISOEN 0x20
18#define PCU_DM_PWRDN 0x24
19#define PCU_DM_ACK_SYNC 0x28
20
21enum {
22 PCU_DM_NEON0 = 0,
23 PCU_DM_NEON1,
24 PCU_DM_GPU,
25 PCU_DM_DECPPU,
26 PCU_DM_VOU,
27 PCU_DM_R2D,
28 PCU_DM_TOP,
29};
30
31static void __iomem *pcubase;
32
33struct zx_pm_domain {
34 struct generic_pm_domain dm;
35 unsigned int bit;
36};
37
38static int normal_power_off(struct generic_pm_domain *domain)
39{
40 struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
41 unsigned long loop = 1000;
42 u32 tmp;
43
44 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
45 tmp &= ~BIT(zpd->bit);
46 writel_relaxed(tmp, pcubase + PCU_DM_CLKEN);
47 udelay(5);
48
49 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
50 tmp &= ~BIT(zpd->bit);
51 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN);
52 udelay(5);
53
54 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
55 tmp &= ~BIT(zpd->bit);
56 writel_relaxed(tmp, pcubase + PCU_DM_RSTEN);
57 udelay(5);
58
59 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
60 tmp &= ~BIT(zpd->bit);
61 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN);
62 do {
63 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
64 } while (--loop && !tmp);
65
66 if (!loop) {
67 pr_err("Error: %s %s fail\n", __func__, domain->name);
68 return -EIO;
69 }
70
71 return 0;
72}
73
74static int normal_power_on(struct generic_pm_domain *domain)
75{
76 struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
77 unsigned long loop = 10000;
78 u32 tmp;
79
80 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
81 tmp &= ~BIT(zpd->bit);
82 writel_relaxed(tmp, pcubase + PCU_DM_PWRDN);
83 do {
84 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
85 } while (--loop && tmp);
86
87 if (!loop) {
88 pr_err("Error: %s %s fail\n", __func__, domain->name);
89 return -EIO;
90 }
91
92 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
93 tmp &= ~BIT(zpd->bit);
94 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN);
95 udelay(5);
96
97 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
98 tmp &= ~BIT(zpd->bit);
99 writel_relaxed(tmp, pcubase + PCU_DM_ISOEN);
100 udelay(5);
101
102 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
103 tmp &= ~BIT(zpd->bit);
104 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN);
105 udelay(5);
106 return 0;
107}
108
109static struct zx_pm_domain gpu_domain = {
110 .dm = {
111 .name = "gpu_domain",
112 .power_off = normal_power_off,
113 .power_on = normal_power_on,
114 },
115 .bit = PCU_DM_GPU,
116};
117
118static struct zx_pm_domain decppu_domain = {
119 .dm = {
120 .name = "decppu_domain",
121 .power_off = normal_power_off,
122 .power_on = normal_power_on,
123 },
124 .bit = PCU_DM_DECPPU,
125};
126
127static struct zx_pm_domain vou_domain = {
128 .dm = {
129 .name = "vou_domain",
130 .power_off = normal_power_off,
131 .power_on = normal_power_on,
132 },
133 .bit = PCU_DM_VOU,
134};
135
136static struct zx_pm_domain r2d_domain = {
137 .dm = {
138 .name = "r2d_domain",
139 .power_off = normal_power_off,
140 .power_on = normal_power_on,
141 },
142 .bit = PCU_DM_R2D,
143};
144
145static struct generic_pm_domain *zx296702_pm_domains[] = {
146 &vou_domain.dm,
147 &gpu_domain.dm,
148 &decppu_domain.dm,
149 &r2d_domain.dm,
150};
151
152static int zx296702_pd_probe(struct platform_device *pdev)
153{
154 struct genpd_onecell_data *genpd_data;
155 struct resource *res;
156 int i;
157
158 genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
159 if (!genpd_data)
160 return -ENOMEM;
161
162 genpd_data->domains = zx296702_pm_domains;
163 genpd_data->num_domains = ARRAY_SIZE(zx296702_pm_domains);
164
165 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
166 if (!res) {
167 dev_err(&pdev->dev, "no memory resource defined\n");
168 return -ENODEV;
169 }
170
171 pcubase = devm_ioremap_resource(&pdev->dev, res);
172 if (!pcubase) {
173 dev_err(&pdev->dev, "ioremap fail.\n");
174 return -EIO;
175 }
176
177 for (i = 0; i < ARRAY_SIZE(zx296702_pm_domains); ++i)
178 pm_genpd_init(zx296702_pm_domains[i], NULL, false);
179
180 of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
181 return 0;
182}
183
184static const struct of_device_id zx296702_pm_domain_matches[] __initconst = {
185 { .compatible = "zte,zx296702-pcu", },
186 { },
187};
188
189static struct platform_driver zx296702_pd_driver __initdata = {
190 .driver = {
191 .name = "zx-powerdomain",
192 .owner = THIS_MODULE,
193 .of_match_table = zx296702_pm_domain_matches,
194 },
195 .probe = zx296702_pd_probe,
196};
197
198static int __init zx296702_pd_init(void)
199{
200 return platform_driver_register(&zx296702_pd_driver);
201}
202subsys_initcall(zx296702_pd_init);
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 616d5840fc2e..6bd4a43e1a78 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -197,8 +197,8 @@ static const char * const zynq_dt_match[] = {
197 197
198DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") 198DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
199 /* 64KB way size, 8-way associativity, parity disabled */ 199 /* 64KB way size, 8-way associativity, parity disabled */
200 .l2c_aux_val = 0x00000000, 200 .l2c_aux_val = 0x00400000,
201 .l2c_aux_mask = 0xffffffff, 201 .l2c_aux_mask = 0xffbfffff,
202 .smp = smp_ops(zynq_smp_ops), 202 .smp = smp_ops(zynq_smp_ops),
203 .map_io = zynq_map_io, 203 .map_io = zynq_map_io,
204 .init_irq = zynq_irq_init, 204 .init_irq = zynq_irq_init,
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index 045c72720a4d..f6d5de073e34 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -18,7 +18,7 @@ ARM_BE8(rev r0, r0)
18.globl zynq_secondary_trampoline_jump 18.globl zynq_secondary_trampoline_jump
19zynq_secondary_trampoline_jump: 19zynq_secondary_trampoline_jump:
20 /* Space for jumping address */ 20 /* Space for jumping address */
21 .word /* cpu 1 */ 21 .word 0 /* cpu 1 */
22.globl zynq_secondary_trampoline_end 22.globl zynq_secondary_trampoline_end
23zynq_secondary_trampoline_end: 23zynq_secondary_trampoline_end:
24ENDPROC(zynq_secondary_trampoline) 24ENDPROC(zynq_secondary_trampoline)
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index d92f07f6ecfb..de2b061889ec 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -289,7 +289,8 @@ int pxa_request_dma (char *name, pxa_dma_prio prio,
289 /* try grabbing a DMA channel with the requested priority */ 289 /* try grabbing a DMA channel with the requested priority */
290 for (i = 0; i < num_dma_channels; i++) { 290 for (i = 0; i < num_dma_channels; i++) {
291 if ((dma_channels[i].prio == prio) && 291 if ((dma_channels[i].prio == prio) &&
292 !dma_channels[i].name) { 292 !dma_channels[i].name &&
293 !pxad_toggle_reserved_channel(i)) {
293 found = 1; 294 found = 1;
294 break; 295 break;
295 } 296 }
@@ -326,13 +327,14 @@ void pxa_free_dma (int dma_ch)
326 local_irq_save(flags); 327 local_irq_save(flags);
327 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; 328 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
328 dma_channels[dma_ch].name = NULL; 329 dma_channels[dma_ch].name = NULL;
330 pxad_toggle_reserved_channel(dma_ch);
329 local_irq_restore(flags); 331 local_irq_restore(flags);
330} 332}
331EXPORT_SYMBOL(pxa_free_dma); 333EXPORT_SYMBOL(pxa_free_dma);
332 334
333static irqreturn_t dma_irq_handler(int irq, void *dev_id) 335static irqreturn_t dma_irq_handler(int irq, void *dev_id)
334{ 336{
335 int i, dint = DINT; 337 int i, dint = DINT, done = 0;
336 struct dma_channel *channel; 338 struct dma_channel *channel;
337 339
338 while (dint) { 340 while (dint) {
@@ -341,16 +343,13 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
341 channel = &dma_channels[i]; 343 channel = &dma_channels[i];
342 if (channel->name && channel->irq_handler) { 344 if (channel->name && channel->irq_handler) {
343 channel->irq_handler(i, channel->data); 345 channel->irq_handler(i, channel->data);
344 } else { 346 done++;
345 /*
346 * IRQ for an unregistered DMA channel:
347 * let's clear the interrupts and disable it.
348 */
349 printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i);
350 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
351 } 347 }
352 } 348 }
353 return IRQ_HANDLED; 349 if (done)
350 return IRQ_HANDLED;
351 else
352 return IRQ_NONE;
354} 353}
355 354
356int __init pxa_init_dma(int irq, int num_ch) 355int __init pxa_init_dma(int irq, int num_ch)
@@ -372,7 +371,8 @@ int __init pxa_init_dma(int irq, int num_ch)
372 spin_lock_init(&dma_channels[i].lock); 371 spin_lock_init(&dma_channels[i].lock);
373 } 372 }
374 373
375 ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL); 374 ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA",
375 dma_channels);
376 if (ret) { 376 if (ret) {
377 printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); 377 printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
378 kfree(dma_channels); 378 kfree(dma_channels);
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h
index a7b91dc06852..28848b344e2d 100644
--- a/arch/arm/plat-pxa/include/plat/dma.h
+++ b/arch/arm/plat-pxa/include/plat/dma.h
@@ -82,4 +82,19 @@ int pxa_request_dma (char *name,
82 82
83void pxa_free_dma (int dma_ch); 83void pxa_free_dma (int dma_ch);
84 84
85/*
86 * Cooperation with pxa_dma + dmaengine while there remains at least one pxa
87 * driver not converted to dmaengine.
88 */
89#if defined(CONFIG_PXA_DMA)
90extern int pxad_toggle_reserved_channel(int legacy_channel);
91#else
92static inline int pxad_toggle_reserved_channel(int legacy_channel)
93{
94 return 0;
95}
96#endif
97
98extern void __init pxa2xx_set_dmac_info(int nb_channels);
99
85#endif /* __PLAT_DMA_H */ 100#endif /* __PLAT_DMA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 14:07:36 -0500