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authorChris Zankel <chris@zankel.net>2016-01-21 00:17:09 -0500
committerChris Zankel <chris@zankel.net>2016-01-21 00:17:09 -0500
commitbb2f3486041aa126cb7ce4929f1e45ede85f0051 (patch)
tree144450f64cc6ad20d72026ed406ccedb524720d9 /arch/xtensa/include
parentd1208404dd477c142680437137c9996b95bfd508 (diff)
parent5bb8def55dc562d81ec582368b4f27c8d432fbd5 (diff)
Merge tag 'xtensa-for-next-20160111' of git://github.com/jcmvbkbc/linux-xtensa
Xtensa improvements for 4.5: - control whether perf IRQ is treated as NMI from Kconfig; - implement ioremap for regions outside KIO segment.
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r--arch/xtensa/include/asm/io.h16
-rw-r--r--arch/xtensa/include/asm/processor.h12
-rw-r--r--arch/xtensa/include/asm/timex.h9
3 files changed, 21 insertions, 16 deletions
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 74fed0b4e2c2..c38e5a732d86 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -25,9 +25,12 @@
25 25
26#ifdef CONFIG_MMU 26#ifdef CONFIG_MMU
27 27
28void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size);
29void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size);
30void xtensa_iounmap(volatile void __iomem *addr);
31
28/* 32/*
29 * Return the virtual address for the specified bus memory. 33 * Return the virtual address for the specified bus memory.
30 * Note that we currently don't support any address outside the KIO segment.
31 */ 34 */
32static inline void __iomem *ioremap_nocache(unsigned long offset, 35static inline void __iomem *ioremap_nocache(unsigned long offset,
33 unsigned long size) 36 unsigned long size)
@@ -36,7 +39,7 @@ static inline void __iomem *ioremap_nocache(unsigned long offset,
36 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) 39 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
37 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); 40 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
38 else 41 else
39 BUG(); 42 return xtensa_ioremap_nocache(offset, size);
40} 43}
41 44
42static inline void __iomem *ioremap_cache(unsigned long offset, 45static inline void __iomem *ioremap_cache(unsigned long offset,
@@ -46,7 +49,7 @@ static inline void __iomem *ioremap_cache(unsigned long offset,
46 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) 49 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
47 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); 50 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
48 else 51 else
49 BUG(); 52 return xtensa_ioremap_cache(offset, size);
50} 53}
51#define ioremap_cache ioremap_cache 54#define ioremap_cache ioremap_cache
52 55
@@ -60,6 +63,13 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
60 63
61static inline void iounmap(volatile void __iomem *addr) 64static inline void iounmap(volatile void __iomem *addr)
62{ 65{
66 unsigned long va = (unsigned long) addr;
67
68 if (!(va >= XCHAL_KIO_CACHED_VADDR &&
69 va - XCHAL_KIO_CACHED_VADDR < XCHAL_KIO_SIZE) &&
70 !(va >= XCHAL_KIO_BYPASS_VADDR &&
71 va - XCHAL_KIO_BYPASS_VADDR < XCHAL_KIO_SIZE))
72 xtensa_iounmap(addr);
63} 73}
64 74
65#define virt_to_bus virt_to_phys 75#define virt_to_bus virt_to_phys
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 83e2e4bc01ba..744ecf0dc3a4 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -78,22 +78,20 @@
78#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) 78#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
79#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) 79#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
80 80
81#define IS_POW2(v) (((v) & ((v) - 1)) == 0) 81#define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l)
82#define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK)
82 83
83#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) 84#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
84 85
85/* LOCKLEVEL defines the interrupt level that masks all 86/* LOCKLEVEL defines the interrupt level that masks all
86 * general-purpose interrupts. 87 * general-purpose interrupts.
87 */ 88 */
88#if defined(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) && \ 89#if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT)
89 defined(XCHAL_PROFILING_INTERRUPT) && \ 90#define LOCKLEVEL (PROFILING_INTLEVEL - 1)
90 PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
91 XCHAL_EXCM_LEVEL > 1 && \
92 IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL))
93#define LOCKLEVEL (XCHAL_EXCM_LEVEL - 1)
94#else 91#else
95#define LOCKLEVEL XCHAL_EXCM_LEVEL 92#define LOCKLEVEL XCHAL_EXCM_LEVEL
96#endif 93#endif
94
97#define TOPLEVEL XCHAL_EXCM_LEVEL 95#define TOPLEVEL XCHAL_EXCM_LEVEL
98#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) 96#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
99 97
diff --git a/arch/xtensa/include/asm/timex.h b/arch/xtensa/include/asm/timex.h
index ca929e6a38b5..f9b389d4e973 100644
--- a/arch/xtensa/include/asm/timex.h
+++ b/arch/xtensa/include/asm/timex.h
@@ -12,19 +12,16 @@
12#include <asm/processor.h> 12#include <asm/processor.h>
13#include <linux/stringify.h> 13#include <linux/stringify.h>
14 14
15#define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
16#define INTLEVEL(x) _INTLEVEL(x)
17
18#if XCHAL_NUM_TIMERS > 0 && \ 15#if XCHAL_NUM_TIMERS > 0 && \
19 INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL 16 XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
20# define LINUX_TIMER 0 17# define LINUX_TIMER 0
21# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT 18# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
22#elif XCHAL_NUM_TIMERS > 1 && \ 19#elif XCHAL_NUM_TIMERS > 1 && \
23 INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL 20 XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
24# define LINUX_TIMER 1 21# define LINUX_TIMER 1
25# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT 22# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
26#elif XCHAL_NUM_TIMERS > 2 && \ 23#elif XCHAL_NUM_TIMERS > 2 && \
27 INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL 24 XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
28# define LINUX_TIMER 2 25# define LINUX_TIMER 2
29# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT 26# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
30#else 27#else