Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 platform updates from Ingo Molnar:
 "The main change is the addition of SGI/UV4 support"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
  x86/platform/UV: Fix incorrect nodes and pnodes for cpuless and memoryless nodes
  x86/platform/UV: Remove Obsolete GRU MMR address translation
  x86/platform/UV: Update physical address conversions for UV4
  x86/platform/UV: Build GAM reference tables
  x86/platform/UV: Support UV4 socket address changes
  x86/platform/UV: Add obtaining GAM Range Table from UV BIOS
  x86/platform/UV: Add UV4 addressing discovery function
  x86/platform/UV: Fold blade info into per node hub info structs
  x86/platform/UV: Allocate common per node hub info structs on local node
  x86/platform/UV: Move blade local processor ID to the per cpu info struct
  x86/platform/UV: Move scir info to the per cpu info struct
  x86/platform/UV: Create per cpu info structs to replace per hub info structs
  x86/platform/UV: Update MMIOH setup function to work for both UV3 and UV4
  x86/platform/UV: Clean up redunduncies after merge of UV4 MMR definitions
  x86/platform/UV: Add UV4 Specific MMR definitions
  x86/platform/UV: Prep for UV4 MMR updates
  x86/platform/UV: Add UV MMR Illegal Access Function
  x86/platform/UV: Add UV4 Specific Defines
  x86/platform/UV: Add UV Architecture Defines
  x86/platform/UV: Add Initial UV4 definitions
  ...

10 files changed, 2865 insertions, 777 deletions

diff --git a/arch/x86/include/asm/bios_ebda.h b/arch/x86/include/asm/bios_ebda.h
index aa6a3170ab5a..2b00c776f223 100644
--- a/arch/x86/include/asm/bios_ebda.h
+++ b/arch/x86/include/asm/bios_ebda.h
@@ -17,27 +17,6 @@ static inline unsigned int get_bios_ebda(void)
         return address; /* 0 means none */
 }
 
-/*
- * Return the sanitized length of the EBDA in bytes, if it exists.
- */
-static inline unsigned int get_bios_ebda_length(void)
-{
-        unsigned int address;
-        unsigned int length;
-
-        address = get_bios_ebda();
-        if (!address)
-                return 0;
-
-        /* EBDA length is byte 0 of the EBDA (stored in KiB) */
-        length = *(unsigned char *)phys_to_virt(address);
-        length <<= 10;
-
-        /* Trim the length if it extends beyond 640KiB */
-        length = min_t(unsigned int, (640 * 1024) - address, length);
-        return length;
-}
-
 void reserve_ebda_region(void);
 
 #ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION
diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h
index 71605c7d5c5c..c852590254d5 100644
--- a/arch/x86/include/asm/uv/bios.h
+++ b/arch/x86/include/asm/uv/bios.h
@@ -51,15 +51,66 @@ enum {
         BIOS_STATUS_UNAVAIL             = -EBUSY
 };
 
+/* Address map parameters */
+struct uv_gam_parameters {
+        u64     mmr_base;
+        u64     gru_base;
+        u8      mmr_shift;      /* Convert PNode to MMR space offset */
+        u8      gru_shift;      /* Convert PNode to GRU space offset */
+        u8      gpa_shift;      /* Size of offset field in GRU phys addr */
+        u8      unused1;
+};
+
+/* UV_TABLE_GAM_RANGE_ENTRY values */
+#define UV_GAM_RANGE_TYPE_UNUSED        0 /* End of table */
+#define UV_GAM_RANGE_TYPE_RAM           1 /* Normal RAM */
+#define UV_GAM_RANGE_TYPE_NVRAM         2 /* Non-volatile memory */
+#define UV_GAM_RANGE_TYPE_NV_WINDOW     3 /* NVMDIMM block window */
+#define UV_GAM_RANGE_TYPE_NV_MAILBOX    4 /* NVMDIMM mailbox */
+#define UV_GAM_RANGE_TYPE_HOLE          5 /* Unused address range */
+#define UV_GAM_RANGE_TYPE_MAX           6
+
+/* The structure stores PA bits 56:26, for 64MB granularity */
+#define UV_GAM_RANGE_SHFT               26              /* 64MB */
+
+struct uv_gam_range_entry {
+        char    type;           /* Entry type: GAM_RANGE_TYPE_UNUSED, etc. */
+        char    unused1;
+        u16     nasid;          /* HNasid */
+        u16     sockid;         /* Socket ID, high bits of APIC ID */
+        u16     pnode;          /* Index to MMR and GRU spaces */
+        u32     pxm;            /* ACPI proximity domain number */
+        u32     limit;          /* PA bits 56:26 (UV_GAM_RANGE_SHFT) */
+};
+
+#define UV_SYSTAB_SIG                   "UVST"
+#define UV_SYSTAB_VERSION_1             1       /* UV1/2/3 BIOS version */
+#define UV_SYSTAB_VERSION_UV4           0x400   /* UV4 BIOS base version */
+#define UV_SYSTAB_VERSION_UV4_1         0x401   /* + gpa_shift */
+#define UV_SYSTAB_VERSION_UV4_2         0x402   /* + TYPE_NVRAM/WINDOW/MBOX */
+#define UV_SYSTAB_VERSION_UV4_LATEST    UV_SYSTAB_VERSION_UV4_2
+
+#define UV_SYSTAB_TYPE_UNUSED           0       /* End of table (offset == 0) */
+#define UV_SYSTAB_TYPE_GAM_PARAMS       1       /* GAM PARAM conversions */
+#define UV_SYSTAB_TYPE_GAM_RNG_TBL      2       /* GAM entry table */
+#define UV_SYSTAB_TYPE_MAX              3
+
 /*
  * The UV system table describes specific firmware
  * capabilities available to the Linux kernel at runtime.
  */
 struct uv_systab {
-        char signature[4];      /* must be "UVST" */
+        char signature[4];      /* must be UV_SYSTAB_SIG */
         u32 revision;           /* distinguish different firmware revs */
         u64 function;           /* BIOS runtime callback function ptr */
+        u32 size;               /* systab size (starting with _VERSION_UV4) */
+        struct {
+                u32 type:8;     /* type of entry */
+                u32 offset:24;  /* byte offset from struct start to entry */
+        } entry[1];             /* additional entries follow */
 };
+extern struct uv_systab *uv_systab;
+/* (... end of definitions from UV BIOS ...) */
 
 enum {
         BIOS_FREQ_BASE_PLATFORM = 0,
@@ -99,7 +150,11 @@ extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect);
 extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *);
 extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus);
 
+#ifdef CONFIG_EFI
 extern void uv_bios_init(void);
+#else
+void uv_bios_init(void) { }
+#endif
 
 extern unsigned long sn_rtc_cycles_per_second;
 extern int uv_type;
@@ -107,7 +162,7 @@ extern long sn_partition_id;
 extern long sn_coherency_id;
 extern long sn_region_size;
 extern long system_serial_number;
-#define partition_coherence_id()        (sn_coherency_id)
+#define uv_partition_coherence_id()     (sn_coherency_id)
 
 extern struct kobject *sgi_uv_kobj;     /* /sys/firmware/sgi_uv */
 
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index fc808b83fccb..cc44d926c17e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -598,7 +598,7 @@ struct bau_control {
         int                     timeout_tries;
         int                     ipi_attempts;
         int                     conseccompletes;
-        short                   nobau;
+        bool                    nobau;
         short                   baudisabled;
         short                   cpu;
         short                   osnode;
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index ea7074784cc4..097b80c989c4 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -16,9 +16,11 @@
 #include <linux/percpu.h>
 #include <linux/timer.h>
 #include <linux/io.h>
+#include <linux/topology.h>
 #include <asm/types.h>
 #include <asm/percpu.h>
 #include <asm/uv/uv_mmrs.h>
+#include <asm/uv/bios.h>
 #include <asm/irq_vectors.h>
 #include <asm/io_apic.h>
 
@@ -103,7 +105,6 @@
  *            processor APICID register.
  */
 
-
 /*
  * Maximum number of bricks in all partitions and in all coherency domains.
  * This is the total number of bricks accessible in the numalink fabric. It
@@ -127,6 +128,7 @@
  */
 #define UV_MAX_NASID_VALUE      (UV_MAX_NUMALINK_BLADES * 2)
 
+/* System Controller Interface Reg info */
 struct uv_scir_s {
         struct timer_list timer;
         unsigned long   offset;
@@ -137,71 +139,173 @@ struct uv_scir_s {
         unsigned char   enabled;
 };
 
+/* GAM (globally addressed memory) range table */
+struct uv_gam_range_s {
+        u32     limit;          /* PA bits 56:26 (GAM_RANGE_SHFT) */
+        u16     nasid;          /* node's global physical address */
+        s8      base;           /* entry index of node's base addr */
+        u8      reserved;
+};
+
 /*
  * The following defines attributes of the HUB chip. These attributes are
- * frequently referenced and are kept in the per-cpu data areas of each cpu.
- * They are kept together in a struct to minimize cache misses.
+ * frequently referenced and are kept in a common per hub struct.
+ * After setup, the struct is read only, so it should be readily
+ * available in the L3 cache on the cpu socket for the node.
  */
 struct uv_hub_info_s {
         unsigned long           global_mmr_base;
+        unsigned long           global_mmr_shift;
         unsigned long           gpa_mask;
-        unsigned int            gnode_extra;
+        unsigned short          *socket_to_node;
+        unsigned short          *socket_to_pnode;
+        unsigned short          *pnode_to_socket;
+        struct uv_gam_range_s   *gr_table;
+        unsigned short          min_socket;
+        unsigned short          min_pnode;
+        unsigned char           m_val;
+        unsigned char           n_val;
+        unsigned char           gr_table_len;
         unsigned char           hub_revision;
         unsigned char           apic_pnode_shift;
+        unsigned char           gpa_shift;
         unsigned char           m_shift;
         unsigned char           n_lshift;
+        unsigned int            gnode_extra;
         unsigned long           gnode_upper;
         unsigned long           lowmem_remap_top;
         unsigned long           lowmem_remap_base;
+        unsigned long           global_gru_base;
+        unsigned long           global_gru_shift;
         unsigned short          pnode;
         unsigned short          pnode_mask;
         unsigned short          coherency_domain_number;
         unsigned short          numa_blade_id;
-        unsigned char           blade_processor_id;
-        unsigned char           m_val;
-        unsigned char           n_val;
+        unsigned short          nr_possible_cpus;
+        unsigned short          nr_online_cpus;
+        short                   memory_nid;
+};
+
+/* CPU specific info with a pointer to the hub common info struct */
+struct uv_cpu_info_s {
+        void                    *p_uv_hub_info;
+        unsigned char           blade_cpu_id;
         struct uv_scir_s        scir;
 };
+DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
+
+#define uv_cpu_info             this_cpu_ptr(&__uv_cpu_info)
+#define uv_cpu_info_per(cpu)    (&per_cpu(__uv_cpu_info, cpu))
+
+#define uv_scir_info            (&uv_cpu_info->scir)
+#define uv_cpu_scir_info(cpu)   (&uv_cpu_info_per(cpu)->scir)
+
+/* Node specific hub common info struct */
+extern void **__uv_hub_info_list;
+static inline struct uv_hub_info_s *uv_hub_info_list(int node)
+{
+        return (struct uv_hub_info_s *)__uv_hub_info_list[node];
+}
+
+static inline struct uv_hub_info_s *_uv_hub_info(void)
+{
+        return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info;
+}
+#define uv_hub_info     _uv_hub_info()
 
-DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
-#define uv_hub_info             this_cpu_ptr(&__uv_hub_info)
-#define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
+static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu)
+{
+        return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
+}
+
+#define UV_HUB_INFO_VERSION     0x7150
+extern int uv_hub_info_version(void);
+static inline int uv_hub_info_check(int version)
+{
+        if (uv_hub_info_version() == version)
+                return 0;
+
+        pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n",
+                uv_hub_info_version(), version);
+
+        BUG();  /* Catastrophic - cannot continue on unknown UV system */
+}
+#define _uv_hub_info_check()    uv_hub_info_check(UV_HUB_INFO_VERSION)
 
 /*
- * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
- * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
+ * HUB revision ranges for each UV HUB architecture.
  * This is a software convention - NOT the hardware revision numbers in
  * the hub chip.
  */
 #define UV1_HUB_REVISION_BASE           1
 #define UV2_HUB_REVISION_BASE           3
 #define UV3_HUB_REVISION_BASE           5
+#define UV4_HUB_REVISION_BASE           7
 
+#ifdef  UV1_HUB_IS_SUPPORTED
 static inline int is_uv1_hub(void)
 {
         return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
 }
+#else
+static inline int is_uv1_hub(void)
+{
+        return 0;
+}
+#endif
 
+#ifdef  UV2_HUB_IS_SUPPORTED
 static inline int is_uv2_hub(void)
 {
         return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
                 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
 }
+#else
+static inline int is_uv2_hub(void)
+{
+        return 0;
+}
+#endif
 
+#ifdef  UV3_HUB_IS_SUPPORTED
+static inline int is_uv3_hub(void)
+{
+        return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) &&
+                (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE));
+}
+#else
 static inline int is_uv3_hub(void)
 {
-        return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE;
+        return 0;
 }
+#endif
 
-static inline int is_uv_hub(void)
+#ifdef  UV4_HUB_IS_SUPPORTED
+static inline int is_uv4_hub(void)
 {
-        return uv_hub_info->hub_revision;
+        return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE;
 }
+#else
+static inline int is_uv4_hub(void)
+{
+        return 0;
+}
+#endif
 
-/* code common to uv2 and uv3 only */
 static inline int is_uvx_hub(void)
 {
-        return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
+        if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE)
+                return uv_hub_info->hub_revision;
+
+        return 0;
+}
+
+static inline int is_uv_hub(void)
+{
+#ifdef  UV1_HUB_IS_SUPPORTED
+        return uv_hub_info->hub_revision;
+#endif
+        return is_uvx_hub();
 }
 
 union uvh_apicid {
@@ -243,24 +347,42 @@ union uvh_apicid {
 #define UV3_LOCAL_MMR_SIZE              (32UL * 1024 * 1024)
 #define UV3_GLOBAL_MMR32_SIZE           (32UL * 1024 * 1024)
 
-#define UV_LOCAL_MMR_BASE               (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
-                                        (is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
-                                                        UV3_LOCAL_MMR_BASE))
-#define UV_GLOBAL_MMR32_BASE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\
-                                        (is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\
-                                                        UV3_GLOBAL_MMR32_BASE))
-#define UV_LOCAL_MMR_SIZE               (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
-                                        (is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
-                                                        UV3_LOCAL_MMR_SIZE))
-#define UV_GLOBAL_MMR32_SIZE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
-                                        (is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\
-                                                        UV3_GLOBAL_MMR32_SIZE))
+#define UV4_LOCAL_MMR_BASE              0xfa000000UL
+#define UV4_GLOBAL_MMR32_BASE           0xfc000000UL
+#define UV4_LOCAL_MMR_SIZE              (32UL * 1024 * 1024)
+#define UV4_GLOBAL_MMR32_SIZE           (16UL * 1024 * 1024)
+
+#define UV_LOCAL_MMR_BASE               (                               \
+                                        is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
+                                        is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
+                                        is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \
+                                        /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)
+
+#define UV_GLOBAL_MMR32_BASE            (                               \
+                                        is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \
+                                        is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \
+                                        is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \
+                                        /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)
+
+#define UV_LOCAL_MMR_SIZE               (                               \
+                                        is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
+                                        is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
+                                        is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \
+                                        /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)
+
+#define UV_GLOBAL_MMR32_SIZE            (                               \
+                                        is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \
+                                        is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \
+                                        is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \
+                                        /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
+
 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
 
 #define UV_GLOBAL_GRU_MMR_BASE          0x4000000
 
 #define UV_GLOBAL_MMR32_PNODE_SHIFT     15
-#define UV_GLOBAL_MMR64_PNODE_SHIFT     26
+#define _UV_GLOBAL_MMR64_PNODE_SHIFT    26
+#define UV_GLOBAL_MMR64_PNODE_SHIFT     (uv_hub_info->global_mmr_shift)
 
 #define UV_GLOBAL_MMR32_PNODE_BITS(p)   ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
 
@@ -307,18 +429,74 @@ union uvh_apicid {
  *            between socket virtual and socket physical addresses.
  */
 
+/* global bits offset - number of local address bits in gpa for this UV arch */
+static inline unsigned int uv_gpa_shift(void)
+{
+        return uv_hub_info->gpa_shift;
+}
+#define _uv_gpa_shift
+
+/* Find node that has the address range that contains global address  */
+static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa)
+{
+        struct uv_gam_range_s *gr = uv_hub_info->gr_table;
+        unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT;
+        int i, num = uv_hub_info->gr_table_len;
+
+        if (gr) {
+                for (i = 0; i < num; i++, gr++) {
+                        if (pal < gr->limit)
+                                return gr;
+                }
+        }
+        pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr);
+        BUG();
+}
+
+/* Return base address of node that contains global address  */
+static inline unsigned long uv_gam_range_base(unsigned long pa)
+{
+        struct uv_gam_range_s *gr = uv_gam_range(pa);
+        int base = gr->base;
+
+        if (base < 0)
+                return 0UL;
+
+        return uv_hub_info->gr_table[base].limit;
+}
+
+/* socket phys RAM --> UV global NASID (UV4+) */
+static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr)
+{
+        return uv_gam_range(paddr)->nasid;
+}
+#define _uv_soc_phys_ram_to_nasid
+
+/* socket virtual --> UV global NASID (UV4+) */
+static inline unsigned long uv_gpa_nasid(void *v)
+{
+        return uv_soc_phys_ram_to_nasid(__pa(v));
+}
+
 /* socket phys RAM --> UV global physical address */
 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
 {
+        unsigned int m_val = uv_hub_info->m_val;
+
         if (paddr < uv_hub_info->lowmem_remap_top)
                 paddr |= uv_hub_info->lowmem_remap_base;
         paddr |= uv_hub_info->gnode_upper;
-        paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
-                ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
+        if (m_val)
+                paddr = ((paddr << uv_hub_info->m_shift)
+                                                >> uv_hub_info->m_shift) |
+                        ((paddr >> uv_hub_info->m_val)
+                                                << uv_hub_info->n_lshift);
+        else
+                paddr |= uv_soc_phys_ram_to_nasid(paddr)
+                                                << uv_hub_info->gpa_shift;
         return paddr;
 }
 
-
 /* socket virtual --> UV global physical address */
 static inline unsigned long uv_gpa(void *v)
 {
@@ -338,54 +516,89 @@ static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
         unsigned long paddr;
         unsigned long remap_base = uv_hub_info->lowmem_remap_base;
         unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
+        unsigned int m_val = uv_hub_info->m_val;
+
+        if (m_val)
+                gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
+                        ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
 
-        gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
-                ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
         paddr = gpa & uv_hub_info->gpa_mask;
         if (paddr >= remap_base && paddr < remap_base + remap_top)
                 paddr -= remap_base;
         return paddr;
 }
 
-
-/* gpa -> pnode */
+/* gpa -> gnode */
 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
 {
-        return gpa >> uv_hub_info->n_lshift;
+        unsigned int n_lshift = uv_hub_info->n_lshift;
+
+        if (n_lshift)
+                return gpa >> n_lshift;
+
+        return uv_gam_range(gpa)->nasid >> 1;
 }
 
 /* gpa -> pnode */
 static inline int uv_gpa_to_pnode(unsigned long gpa)
 {
-        unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
-
-        return uv_gpa_to_gnode(gpa) & n_mask;
+        return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask;
 }
 
-/* gpa -> node offset*/
+/* gpa -> node offset */
 static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
 {
-        return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
+        unsigned int m_shift = uv_hub_info->m_shift;
+
+        if (m_shift)
+                return (gpa << m_shift) >> m_shift;
+
+        return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa);
+}
+
+/* Convert socket to node */
+static inline int _uv_socket_to_node(int socket, unsigned short *s2nid)
+{
+        return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket;
+}
+
+static inline int uv_socket_to_node(int socket)
+{
+        return _uv_socket_to_node(socket, uv_hub_info->socket_to_node);
 }
 
 /* pnode, offset --> socket virtual */
 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
 {
-        return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
-}
+        unsigned int m_val = uv_hub_info->m_val;
+        unsigned long base;
+        unsigned short sockid, node, *p2s;
 
+        if (m_val)
+                return __va(((unsigned long)pnode << m_val) | offset);
 
-/*
- * Extract a PNODE from an APICID (full apicid, not processor subset)
- */
+        p2s = uv_hub_info->pnode_to_socket;
+        sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode;
+        node = uv_socket_to_node(sockid);
+
+        /* limit address of previous socket is our base, except node 0 is 0 */
+        if (!node)
+                return __va((unsigned long)offset);
+
+        base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit);
+        return __va(base << UV_GAM_RANGE_SHFT | offset);
+}
+
+/* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */
 static inline int uv_apicid_to_pnode(int apicid)
 {
-        return (apicid >> uv_hub_info->apic_pnode_shift);
+        int pnode = apicid >> uv_hub_info->apic_pnode_shift;
+        unsigned short *s2pn = uv_hub_info->socket_to_pnode;
+
+        return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;
 }
 
-/*
- * Convert an apicid to the socket number on the blade
- */
+/* Convert an apicid to the socket number on the blade */
 static inline int uv_apicid_to_socket(int apicid)
 {
         if (is_uv1_hub())
@@ -434,16 +647,6 @@ static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset
         return readq(uv_global_mmr64_address(pnode, offset));
 }
 
-/*
- * Global MMR space addresses when referenced by the GRU. (GRU does
- * NOT use socket addressing).
- */
-static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
-{
-        return UV_GLOBAL_GRU_MMR_BASE | offset |
-                ((unsigned long)pnode << uv_hub_info->m_val);
-}
-
 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
 {
         writeb(val, uv_global_mmr64_address(pnode, offset));
@@ -483,27 +686,23 @@ static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
         writeb(val, uv_local_mmr_address(offset));
 }
 
-/*
- * Structures and definitions for converting between cpu, node, pnode, and blade
- * numbers.
- */
-struct uv_blade_info {
-        unsigned short  nr_possible_cpus;
-        unsigned short  nr_online_cpus;
-        unsigned short  pnode;
-        short           memory_nid;
-        spinlock_t      nmi_lock;       /* obsolete, see uv_hub_nmi */
-        unsigned long   nmi_count;      /* obsolete, see uv_hub_nmi */
-};
-extern struct uv_blade_info *uv_blade_info;
-extern short *uv_node_to_blade;
-extern short *uv_cpu_to_blade;
-extern short uv_possible_blades;
-
 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
 static inline int uv_blade_processor_id(void)
 {
-        return uv_hub_info->blade_processor_id;
+        return uv_cpu_info->blade_cpu_id;
+}
+
+/* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */
+static inline int uv_cpu_blade_processor_id(int cpu)
+{
+        return uv_cpu_info_per(cpu)->blade_cpu_id;
+}
+#define _uv_cpu_blade_processor_id 1    /* indicate function available */
+
+/* Blade number to Node number (UV1..UV4 is 1:1) */
+static inline int uv_blade_to_node(int blade)
+{
+        return blade;
 }
 
 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
@@ -512,55 +711,60 @@ static inline int uv_numa_blade_id(void)
         return uv_hub_info->numa_blade_id;
 }
 
-/* Convert a cpu number to the the UV blade number */
-static inline int uv_cpu_to_blade_id(int cpu)
+/*
+ * Convert linux node number to the UV blade number.
+ * .. Currently for UV1 thru UV4 the node and the blade are identical.
+ * .. If this changes then you MUST check references to this function!
+ */
+static inline int uv_node_to_blade_id(int nid)
 {
-        return uv_cpu_to_blade[cpu];
+        return nid;
 }
 
-/* Convert linux node number to the UV blade number */
-static inline int uv_node_to_blade_id(int nid)
+/* Convert a cpu number to the the UV blade number */
+static inline int uv_cpu_to_blade_id(int cpu)
 {
-        return uv_node_to_blade[nid];
+        return uv_node_to_blade_id(cpu_to_node(cpu));
 }
 
 /* Convert a blade id to the PNODE of the blade */
 static inline int uv_blade_to_pnode(int bid)
 {
-        return uv_blade_info[bid].pnode;
+        return uv_hub_info_list(uv_blade_to_node(bid))->pnode;
 }
 
 /* Nid of memory node on blade. -1 if no blade-local memory */
 static inline int uv_blade_to_memory_nid(int bid)
 {
-        return uv_blade_info[bid].memory_nid;
+        return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid;
 }
 
 /* Determine the number of possible cpus on a blade */
 static inline int uv_blade_nr_possible_cpus(int bid)
 {
-        return uv_blade_info[bid].nr_possible_cpus;
+        return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus;
 }
 
 /* Determine the number of online cpus on a blade */
 static inline int uv_blade_nr_online_cpus(int bid)
 {
-        return uv_blade_info[bid].nr_online_cpus;
+        return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus;
 }
 
 /* Convert a cpu id to the PNODE of the blade containing the cpu */
 static inline int uv_cpu_to_pnode(int cpu)
 {
-        return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
+        return uv_cpu_hub_info(cpu)->pnode;
 }
 
 /* Convert a linux node number to the PNODE of the blade */
 static inline int uv_node_to_pnode(int nid)
 {
-        return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
+        return uv_hub_info_list(nid)->pnode;
 }
 
 /* Maximum possible number of blades */
+extern short uv_possible_blades;
 static inline int uv_num_possible_blades(void)
 {
         return uv_possible_blades;
@@ -578,9 +782,7 @@ extern void uv_nmi_setup(void);
 /* Newer SMM NMI handler, not present in all systems */
 #define UVH_NMI_MMRX            UVH_EVENT_OCCURRED0
 #define UVH_NMI_MMRX_CLEAR      UVH_EVENT_OCCURRED0_ALIAS
-#define UVH_NMI_MMRX_SHIFT      (is_uv1_hub() ? \
-                                        UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
-                                        UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
+#define UVH_NMI_MMRX_SHIFT      UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 #define UVH_NMI_MMRX_TYPE       "EXTIO_INT0"
 
 /* Non-zero indicates newer SMM NMI handler present */
@@ -622,9 +824,9 @@ DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
 /* Update SCIR state */
 static inline void uv_set_scir_bits(unsigned char value)
 {
-        if (uv_hub_info->scir.state != value) {
-                uv_hub_info->scir.state = value;
-                uv_write_local_mmr8(uv_hub_info->scir.offset, value);
+        if (uv_scir_info->state != value) {
+                uv_scir_info->state = value;
+                uv_write_local_mmr8(uv_scir_info->offset, value);
         }
 }
 
@@ -635,10 +837,10 @@ static inline unsigned long uv_scir_offset(int apicid)
 
 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
 {
-        if (uv_cpu_hub_info(cpu)->scir.state != value) {
+        if (uv_cpu_scir_info(cpu)->state != value) {
                 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
-                                uv_cpu_hub_info(cpu)->scir.offset, value);
-                uv_cpu_hub_info(cpu)->scir.state = value;
+                                uv_cpu_scir_info(cpu)->offset, value);
+                uv_cpu_scir_info(cpu)->state = value;
         }
 }
 
@@ -666,10 +868,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 
 /*
  * Get the minimum revision number of the hub chips within the partition.
- *     1 - UV1 rev 1.0 initial silicon
- *     2 - UV1 rev 2.0 production silicon
- *     3 - UV2 rev 1.0 initial silicon
- *     5 - UV3 rev 1.0 initial silicon
+ * (See UVx_HUB_REVISION_BASE above for specific values.)
  */
 static inline int uv_get_min_hub_revision_id(void)
 {
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index ddd8db6b6e70..548d684a7960 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -5,7 +5,7 @@
  *
  * SGI UV MMR definitions
  *
- * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_X86_UV_UV_MMRS_H
@@ -18,10 +18,11 @@
  * grouped by architecture types.
  *
  * UVH  - definitions common to all UV hub types.
- * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3).
+ * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4).
  * UV1H - definitions specific to UV type 1 hub.
  * UV2H - definitions specific to UV type 2 hub.
  * UV3H - definitions specific to UV type 3 hub.
+ * UV4H - definitions specific to UV type 4 hub.
  *
  * So in general, MMR addresses and structures are identical on all hubs types.
  * These MMRs are identified as:
@@ -32,19 +33,25 @@
  *              } s;
  *      };
  *
- * If the MMR exists on all hub types but have different addresses:
+ * If the MMR exists on all hub types but have different addresses,
+ * use a conditional operator to define the value at runtime.
  *      #define UV1Hxxx a
  *      #define UV2Hxxx b
  *      #define UV3Hxxx c
+ *      #define UV4Hxxx d
  *      #define UVHxxx  (is_uv1_hub() ? UV1Hxxx :
  *                      (is_uv2_hub() ? UV2Hxxx :
- *                                      UV3Hxxx))
+ *                      (is_uv3_hub() ? UV3Hxxx :
+ *                                      UV4Hxxx))
  *
- * If the MMR exists on all hub types > 1 but have different addresses:
+ * If the MMR exists on all hub types > 1 but have different addresses, the
+ * variation using "UVX" as the prefix exists.
  *      #define UV2Hxxx b
  *      #define UV3Hxxx c
- *      #define UVXHxxx (is_uv2_hub() ? UV2Hxxx :
- *                                      UV3Hxxx))
+ *      #define UV4Hxxx d
+ *      #define UVHxxx  (is_uv2_hub() ? UV2Hxxx :
+ *                      (is_uv3_hub() ? UV3Hxxx :
+ *                                      UV4Hxxx))
  *
  *      union uvh_xxx {
  *              unsigned long       v;
@@ -56,6 +63,8 @@
  *              } s2;
  *              struct uv3h_xxx_s {      # Full UV3 definition (*)
  *              } s3;
+ *              struct uv4h_xxx_s {      # Full UV4 definition (*)
+ *              } s4;
  *      };
  *              (* - if present and different than the common struct)
  *
@@ -73,7 +82,7 @@
  *              } sn;
  *      };
  *
- * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH)
+ * (GEN Flags: mflags_opt= undefs=function UV234=UVXH)
  */
 
 #define UV_MMR_ENABLE           (1UL << 63)
@@ -83,20 +92,36 @@
 #define UV2_HUB_PART_NUMBER_X   0x1111
 #define UV3_HUB_PART_NUMBER     0x9578
 #define UV3_HUB_PART_NUMBER_X   0x4321
+#define UV4_HUB_PART_NUMBER     0x99a1
 
 /* Compat: Indicate which UV Hubs are supported. */
+#define UV1_HUB_IS_SUPPORTED    1
 #define UV2_HUB_IS_SUPPORTED    1
 #define UV3_HUB_IS_SUPPORTED    1
+#define UV4_HUB_IS_SUPPORTED    1
+
+/* Error function to catch undefined references */
+extern unsigned long uv_undefined(char *str);
 
 /* ========================================================================= */
 /*                          UVH_BAU_DATA_BROADCAST                           */
 /* ========================================================================= */
 #define UVH_BAU_DATA_BROADCAST 0x61688UL
-#define UVH_BAU_DATA_BROADCAST_32 0x440
+
+#define UV1H_BAU_DATA_BROADCAST_32 0x440
+#define UV2H_BAU_DATA_BROADCAST_32 0x440
+#define UV3H_BAU_DATA_BROADCAST_32 0x440
+#define UV4H_BAU_DATA_BROADCAST_32 0x360
+#define UVH_BAU_DATA_BROADCAST_32 (                                     \
+        is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 :                     \
+        is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 :                     \
+        is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 :                     \
+        /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32)
 
 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT              0
 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK              0x0000000000000001UL
 
+
 union uvh_bau_data_broadcast_u {
         unsigned long   v;
         struct uvh_bau_data_broadcast_s {
@@ -109,7 +134,16 @@ union uvh_bau_data_broadcast_u {
 /*                           UVH_BAU_DATA_CONFIG                             */
 /* ========================================================================= */
 #define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UVH_BAU_DATA_CONFIG_32 0x438
+
+#define UV1H_BAU_DATA_CONFIG_32 0x438
+#define UV2H_BAU_DATA_CONFIG_32 0x438
+#define UV3H_BAU_DATA_CONFIG_32 0x438
+#define UV4H_BAU_DATA_CONFIG_32 0x358
+#define UVH_BAU_DATA_CONFIG_32 (                                        \
+        is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 :                        \
+        is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 :                        \
+        is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 :                        \
+        /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32)
 
 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT                 0
 #define UVH_BAU_DATA_CONFIG_DM_SHFT                     8
@@ -128,6 +162,7 @@ union uvh_bau_data_broadcast_u {
 #define UVH_BAU_DATA_CONFIG_M_MASK                      0x0000000000010000UL
 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 
+
 union uvh_bau_data_config_u {
         unsigned long   v;
         struct uvh_bau_data_config_s {
@@ -266,7 +301,6 @@ union uvh_bau_data_config_u {
 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK              0x0080000000000000UL
 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK  0x0100000000000000UL
 
-#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT              1
 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT              2
 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
@@ -275,55 +309,11 @@ union uvh_bau_data_config_u {
 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
-#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
-#define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
-#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
-#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
-#define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
-#define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
-#define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
-#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
-#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
-#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
-#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
-#define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
-#define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
-#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
-#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
-#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
-#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
-#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
-#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
-#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
-#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
-#define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT               53
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
-#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
-#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
@@ -332,54 +322,294 @@ union uvh_bau_data_config_u {
 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
-#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
-#define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
-#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
-#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
-#define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
-#define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
-#define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
-#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
-#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
-#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
-#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
-#define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
-#define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
-#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
-#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
-#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
-#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
-#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
-#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
-#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
-#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
-#define UVXH_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
-#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
-#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
+
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
+#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT               53
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
+#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
+
+#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
+#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
+#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
+#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
+#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
+#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
+#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
+#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
+#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
+#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
+#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
+#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
+#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
+#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
+#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
+#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
+#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
+#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
+#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT               53
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
+#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
+#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
+#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
+#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
+#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
+#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
+#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
+#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
+#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
+#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
+#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
+#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
+#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
+#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
+#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
+#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
+#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
+#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
+#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
+#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
+#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
+
+#define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT              1
+#define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT             10
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT           17
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT           18
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT           19
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT           20
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            21
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            22
+#define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT             23
+#define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT             24
+#define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT             25
+#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            26
+#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            27
+#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            28
+#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            29
+#define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT             30
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT           31
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT           32
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT           33
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT           34
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            35
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            36
+#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   37
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          38
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          39
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          40
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          41
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          42
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          43
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          44
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          45
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          46
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          47
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         48
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         49
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         50
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         51
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         52
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         53
+#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            54
+#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            55
+#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            56
+#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            57
+#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        58
+#define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT               59
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            60
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            61
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            62
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            63
+#define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK              0x0000000000000002UL
+#define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK             0x0000000000000400UL
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK           0x0000000000020000UL
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK           0x0000000000040000UL
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK           0x0000000000080000UL
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK           0x0000000000100000UL
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000200000UL
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000400000UL
+#define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000800000UL
+#define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK             0x0000000001000000UL
+#define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000002000000UL
+#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000004000000UL
+#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000008000000UL
+#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000010000000UL
+#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000020000000UL
+#define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000040000000UL
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK           0x0000000080000000UL
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK           0x0000000100000000UL
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK           0x0000000200000000UL
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK           0x0000000400000000UL
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000800000000UL
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000001000000000UL
+#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000002000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000004000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000008000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000010000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000020000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000040000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000080000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000100000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000200000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000400000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000800000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0001000000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0002000000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0004000000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0008000000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0010000000000000UL
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0020000000000000UL
+#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0040000000000000UL
+#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0080000000000000UL
+#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0100000000000000UL
+#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0200000000000000UL
+#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0400000000000000UL
+#define UV4H_EVENT_OCCURRED0_IPI_INT_MASK               0x0800000000000000UL
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x1000000000000000UL
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x2000000000000000UL
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x4000000000000000UL
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x8000000000000000UL
+
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT (                           \
+        is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
+        is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
+        is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :           \
+        /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
 
 union uvh_event_occurred0_u {
         unsigned long   v;
@@ -391,7 +621,7 @@ union uvh_event_occurred0_u {
         } s;
         struct uvxh_event_occurred0_s {
                 unsigned long   lb_hcerr:1;                     /* RW */
-                unsigned long   qp_hcerr:1;                     /* RW */
+                unsigned long   rsvd_1:1;
                 unsigned long   rh_hcerr:1;                     /* RW */
                 unsigned long   lh0_hcerr:1;                    /* RW */
                 unsigned long   lh1_hcerr:1;                    /* RW */
@@ -400,25 +630,51 @@ union uvh_event_occurred0_u {
                 unsigned long   ni0_hcerr:1;                    /* RW */
                 unsigned long   ni1_hcerr:1;                    /* RW */
                 unsigned long   lb_aoerr0:1;                    /* RW */
-                unsigned long   qp_aoerr0:1;                    /* RW */
+                unsigned long   rsvd_10:1;
                 unsigned long   rh_aoerr0:1;                    /* RW */
                 unsigned long   lh0_aoerr0:1;                   /* RW */
                 unsigned long   lh1_aoerr0:1;                   /* RW */
                 unsigned long   gr0_aoerr0:1;                   /* RW */
                 unsigned long   gr1_aoerr0:1;                   /* RW */
                 unsigned long   xb_aoerr0:1;                    /* RW */
-                unsigned long   rt_aoerr0:1;                    /* RW */
+                unsigned long   rsvd_17_63:47;
+        } sx;
+        struct uv4h_event_occurred0_s {
+                unsigned long   lb_hcerr:1;                     /* RW */
+                unsigned long   kt_hcerr:1;                     /* RW */
+                unsigned long   rh_hcerr:1;                     /* RW */
+                unsigned long   lh0_hcerr:1;                    /* RW */
+                unsigned long   lh1_hcerr:1;                    /* RW */
+                unsigned long   gr0_hcerr:1;                    /* RW */
+                unsigned long   gr1_hcerr:1;                    /* RW */
+                unsigned long   ni0_hcerr:1;                    /* RW */
+                unsigned long   ni1_hcerr:1;                    /* RW */
+                unsigned long   lb_aoerr0:1;                    /* RW */
+                unsigned long   kt_aoerr0:1;                    /* RW */
+                unsigned long   rh_aoerr0:1;                    /* RW */
+                unsigned long   lh0_aoerr0:1;                   /* RW */
+                unsigned long   lh1_aoerr0:1;                   /* RW */
+                unsigned long   gr0_aoerr0:1;                   /* RW */
+                unsigned long   gr1_aoerr0:1;                   /* RW */
+                unsigned long   xb_aoerr0:1;                    /* RW */
+                unsigned long   rtq0_aoerr0:1;                  /* RW */
+                unsigned long   rtq1_aoerr0:1;                  /* RW */
+                unsigned long   rtq2_aoerr0:1;                  /* RW */
+                unsigned long   rtq3_aoerr0:1;                  /* RW */
                 unsigned long   ni0_aoerr0:1;                   /* RW */
                 unsigned long   ni1_aoerr0:1;                   /* RW */
                 unsigned long   lb_aoerr1:1;                    /* RW */
-                unsigned long   qp_aoerr1:1;                    /* RW */
+                unsigned long   kt_aoerr1:1;                    /* RW */
                 unsigned long   rh_aoerr1:1;                    /* RW */
                 unsigned long   lh0_aoerr1:1;                   /* RW */
                 unsigned long   lh1_aoerr1:1;                   /* RW */
                 unsigned long   gr0_aoerr1:1;                   /* RW */
                 unsigned long   gr1_aoerr1:1;                   /* RW */
                 unsigned long   xb_aoerr1:1;                    /* RW */
-                unsigned long   rt_aoerr1:1;                    /* RW */
+                unsigned long   rtq0_aoerr1:1;                  /* RW */
+                unsigned long   rtq1_aoerr1:1;                  /* RW */
+                unsigned long   rtq2_aoerr1:1;                  /* RW */
+                unsigned long   rtq3_aoerr1:1;                  /* RW */
                 unsigned long   ni0_aoerr1:1;                   /* RW */
                 unsigned long   ni1_aoerr1:1;                   /* RW */
                 unsigned long   system_shutdown_int:1;          /* RW */
@@ -448,9 +704,7 @@ union uvh_event_occurred0_u {
                 unsigned long   extio_int1:1;                   /* RW */
                 unsigned long   extio_int2:1;                   /* RW */
                 unsigned long   extio_int3:1;                   /* RW */
-                unsigned long   profile_int:1;                  /* RW */
-                unsigned long   rsvd_59_63:5;
-        } sx;
+        } s4;
 };
 
 /* ========================================================================= */
@@ -464,11 +718,21 @@ union uvh_event_occurred0_u {
 /*                         UVH_EXTIO_INT0_BROADCAST                          */
 /* ========================================================================= */
 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL
-#define UVH_EXTIO_INT0_BROADCAST_32 0x3f0
+
+#define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0
+#define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0
+#define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0
+#define UV4H_EXTIO_INT0_BROADCAST_32 0x310
+#define UVH_EXTIO_INT0_BROADCAST_32 (                                   \
+        is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 :                   \
+        is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 :                   \
+        is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 :                   \
+        /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32)
 
 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT            0
 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK            0x0000000000000001UL
 
+
 union uvh_extio_int0_broadcast_u {
         unsigned long   v;
         struct uvh_extio_int0_broadcast_s {
@@ -499,6 +763,7 @@ union uvh_extio_int0_broadcast_u {
 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
+
 union uvh_gr0_tlb_int0_config_u {
         unsigned long   v;
         struct uvh_gr0_tlb_int0_config_s {
@@ -537,6 +802,7 @@ union uvh_gr0_tlb_int0_config_u {
 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
+
 union uvh_gr0_tlb_int1_config_u {
         unsigned long   v;
         struct uvh_gr0_tlb_int1_config_s {
@@ -559,19 +825,18 @@ union uvh_gr0_tlb_int1_config_u {
 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
-#define UVH_GR0_TLB_MMR_CONTROL                                         \
-                (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :              \
-                (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :              \
-                                UV3H_GR0_TLB_MMR_CONTROL))
+#define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL
+#define UVH_GR0_TLB_MMR_CONTROL (                                       \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :                       \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :                       \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL :                       \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL)
 
 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT              0
-#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT           31
-#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
-#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
@@ -601,14 +866,11 @@ union uvh_gr0_tlb_int1_config_u {
 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
 
 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
-#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
-#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
-#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
@@ -651,12 +913,45 @@ union uvh_gr0_tlb_int1_config_u {
 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 
+#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           13
+#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
+#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT         59
+#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000001fffUL
+#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000006000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
+#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK         0xf800000000000000UL
+
+#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK (                            \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK :            \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK)
+#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK (                          \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :          \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK)
+#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT (                          \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :          \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT)
+
 union uvh_gr0_tlb_mmr_control_u {
         unsigned long   v;
         struct uvh_gr0_tlb_mmr_control_s {
-                unsigned long   index:12;                       /* RW */
-                unsigned long   mem_sel:2;                      /* RW */
-                unsigned long   rsvd_14_15:2;
+                unsigned long   rsvd_0_15:16;
                 unsigned long   auto_valid_en:1;                /* RW */
                 unsigned long   rsvd_17_19:3;
                 unsigned long   mmr_hash_index_en:1;            /* RW */
@@ -690,9 +985,7 @@ union uvh_gr0_tlb_mmr_control_u {
                 unsigned long   rsvd_61_63:3;
         } s1;
         struct uvxh_gr0_tlb_mmr_control_s {
-                unsigned long   index:12;                       /* RW */
-                unsigned long   mem_sel:2;                      /* RW */
-                unsigned long   rsvd_14_15:2;
+                unsigned long   rsvd_0_15:16;
                 unsigned long   auto_valid_en:1;                /* RW */
                 unsigned long   rsvd_17_19:3;
                 unsigned long   mmr_hash_index_en:1;            /* RW */
@@ -703,8 +996,7 @@ union uvh_gr0_tlb_mmr_control_u {
                 unsigned long   rsvd_33_47:15;
                 unsigned long   rsvd_48:1;
                 unsigned long   rsvd_49_51:3;
-                unsigned long   rsvd_52:1;
-                unsigned long   rsvd_53_63:11;
+                unsigned long   rsvd_52_63:12;
         } sx;
         struct uv2h_gr0_tlb_mmr_control_s {
                 unsigned long   index:12;                       /* RW */
@@ -741,6 +1033,24 @@ union uvh_gr0_tlb_mmr_control_u {
                 unsigned long   undef_52:1;                     /* Undefined */
                 unsigned long   rsvd_53_63:11;
         } s3;
+        struct uv4h_gr0_tlb_mmr_control_s {
+                unsigned long   index:13;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_15:1;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   ecc_sel:1;                      /* RW */
+                unsigned long   rsvd_22_29:8;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   mmr_op_done:1;                  /* RW */
+                unsigned long   rsvd_33_47:15;
+                unsigned long   undef_48:1;                     /* Undefined */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   rsvd_52_58:7;
+                unsigned long   page_size:5;                    /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -749,19 +1059,14 @@ union uvh_gr0_tlb_mmr_control_u {
 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
-#define UVH_GR0_TLB_MMR_READ_DATA_HI                                    \
-                (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :         \
-                (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :         \
-                                UV3H_GR0_TLB_MMR_READ_DATA_HI))
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL
+#define UVH_GR0_TLB_MMR_READ_DATA_HI (                                  \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :                  \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :                  \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI :                  \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI)
 
 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
 
 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
@@ -773,13 +1078,6 @@ union uvh_gr0_tlb_mmr_control_u {
 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 
 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 
 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
@@ -803,15 +1101,24 @@ union uvh_gr0_tlb_mmr_control_u {
 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
 
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT         34
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          49
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        51
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       52
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       53
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x00000003ffffffffUL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK         0x0001fffc00000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0006000000000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0008000000000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0010000000000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0020000000000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
+
+
 union uvh_gr0_tlb_mmr_read_data_hi_u {
         unsigned long   v;
-        struct uvh_gr0_tlb_mmr_read_data_hi_s {
-                unsigned long   pfn:41;                         /* RO */
-                unsigned long   gaa:2;                          /* RO */
-                unsigned long   dirty:1;                        /* RO */
-                unsigned long   larger:1;                       /* RO */
-                unsigned long   rsvd_45_63:19;
-        } s;
         struct uv1h_gr0_tlb_mmr_read_data_hi_s {
                 unsigned long   pfn:41;                         /* RO */
                 unsigned long   gaa:2;                          /* RO */
@@ -819,13 +1126,6 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
                 unsigned long   larger:1;                       /* RO */
                 unsigned long   rsvd_45_63:19;
         } s1;
-        struct uvxh_gr0_tlb_mmr_read_data_hi_s {
-                unsigned long   pfn:41;                         /* RO */
-                unsigned long   gaa:2;                          /* RO */
-                unsigned long   dirty:1;                        /* RO */
-                unsigned long   larger:1;                       /* RO */
-                unsigned long   rsvd_45_63:19;
-        } sx;
         struct uv2h_gr0_tlb_mmr_read_data_hi_s {
                 unsigned long   pfn:41;                         /* RO */
                 unsigned long   gaa:2;                          /* RO */
@@ -842,6 +1142,16 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
                 unsigned long   undef_46_54:9;                  /* Undefined */
                 unsigned long   way_ecc:9;                      /* RO */
         } s3;
+        struct uv4h_gr0_tlb_mmr_read_data_hi_s {
+                unsigned long   pfn:34;                         /* RO */
+                unsigned long   pnid:15;                        /* RO */
+                unsigned long   gaa:2;                          /* RO */
+                unsigned long   dirty:1;                        /* RO */
+                unsigned long   larger:1;                       /* RO */
+                unsigned long   aa_ext:1;                       /* RO */
+                unsigned long   undef_54:1;                     /* Undefined */
+                unsigned long   way_ecc:9;                      /* RO */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -850,10 +1160,12 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
-#define UVH_GR0_TLB_MMR_READ_DATA_LO                                    \
-                (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :         \
-                (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :         \
-                                UV3H_GR0_TLB_MMR_READ_DATA_LO))
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL
+#define UVH_GR0_TLB_MMR_READ_DATA_LO (                                  \
+        is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :                  \
+        is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :                  \
+        is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO :                  \
+        /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO)
 
 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
@@ -890,6 +1202,14 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
+#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
+
+
 union uvh_gr0_tlb_mmr_read_data_lo_u {
         unsigned long   v;
         struct uvh_gr0_tlb_mmr_read_data_lo_s {
@@ -917,12 +1237,25 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
                 unsigned long   asid:24;                        /* RO */
                 unsigned long   valid:1;                        /* RO */
         } s3;
+        struct uv4h_gr0_tlb_mmr_read_data_lo_s {
+                unsigned long   vpn:39;                         /* RO */
+                unsigned long   asid:24;                        /* RO */
+                unsigned long   valid:1;                        /* RO */
+        } s4;
 };
 
 /* ========================================================================= */
 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
+#define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
+#define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
+#define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
+#define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL
+#define UVH_GR1_TLB_INT0_CONFIG (                                       \
+        is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG :                       \
+        is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG :                       \
+        is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG :                       \
+        /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG)
 
 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT             0
 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT                 8
@@ -941,6 +1274,7 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
+
 union uvh_gr1_tlb_int0_config_u {
         unsigned long   v;
         struct uvh_gr1_tlb_int0_config_s {
@@ -960,7 +1294,15 @@ union uvh_gr1_tlb_int0_config_u {
 /* ========================================================================= */
 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
+#define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
+#define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
+#define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
+#define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL
+#define UVH_GR1_TLB_INT1_CONFIG (                                       \
+        is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG :                       \
+        is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG :                       \
+        is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG :                       \
+        /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG)
 
 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT             0
 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT                 8
@@ -979,6 +1321,7 @@ union uvh_gr1_tlb_int0_config_u {
 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
+
 union uvh_gr1_tlb_int1_config_u {
         unsigned long   v;
         struct uvh_gr1_tlb_int1_config_s {
@@ -1001,19 +1344,18 @@ union uvh_gr1_tlb_int1_config_u {
 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
-#define UVH_GR1_TLB_MMR_CONTROL                                         \
-                (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :              \
-                (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :              \
-                                UV3H_GR1_TLB_MMR_CONTROL))
+#define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL
+#define UVH_GR1_TLB_MMR_CONTROL (                                       \
+        is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :                       \
+        is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :                       \
+        is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL :                       \
+        /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL)
 
 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT              0
-#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT           31
-#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
-#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
@@ -1043,14 +1385,11 @@ union uvh_gr1_tlb_int1_config_u {
 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
 
 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
-#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
-#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
-#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
@@ -1093,12 +1432,30 @@ union uvh_gr1_tlb_int1_config_u {
 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 
+#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           13
+#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
+#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT         59
+#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000001fffUL
+#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000006000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
+#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK         0xf800000000000000UL
+
+
 union uvh_gr1_tlb_mmr_control_u {
         unsigned long   v;
         struct uvh_gr1_tlb_mmr_control_s {
-                unsigned long   index:12;                       /* RW */
-                unsigned long   mem_sel:2;                      /* RW */
-                unsigned long   rsvd_14_15:2;
+                unsigned long   rsvd_0_15:16;
                 unsigned long   auto_valid_en:1;                /* RW */
                 unsigned long   rsvd_17_19:3;
                 unsigned long   mmr_hash_index_en:1;            /* RW */
@@ -1132,9 +1489,7 @@ union uvh_gr1_tlb_mmr_control_u {
                 unsigned long   rsvd_61_63:3;
         } s1;
         struct uvxh_gr1_tlb_mmr_control_s {
-                unsigned long   index:12;                       /* RW */
-                unsigned long   mem_sel:2;                      /* RW */
-                unsigned long   rsvd_14_15:2;
+                unsigned long   rsvd_0_15:16;
                 unsigned long   auto_valid_en:1;                /* RW */
                 unsigned long   rsvd_17_19:3;
                 unsigned long   mmr_hash_index_en:1;            /* RW */
@@ -1145,8 +1500,7 @@ union uvh_gr1_tlb_mmr_control_u {
                 unsigned long   rsvd_33_47:15;
                 unsigned long   rsvd_48:1;
                 unsigned long   rsvd_49_51:3;
-                unsigned long   rsvd_52:1;
-                unsigned long   rsvd_53_63:11;
+                unsigned long   rsvd_52_63:12;
         } sx;
         struct uv2h_gr1_tlb_mmr_control_s {
                 unsigned long   index:12;                       /* RW */
@@ -1183,6 +1537,24 @@ union uvh_gr1_tlb_mmr_control_u {
                 unsigned long   undef_52:1;                     /* Undefined */
                 unsigned long   rsvd_53_63:11;
         } s3;
+        struct uv4h_gr1_tlb_mmr_control_s {
+                unsigned long   index:13;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_15:1;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   ecc_sel:1;                      /* RW */
+                unsigned long   rsvd_22_29:8;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   mmr_op_done:1;                  /* RW */
+                unsigned long   rsvd_33_47:15;
+                unsigned long   undef_48:1;                     /* Undefined */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   rsvd_52_58:7;
+                unsigned long   page_size:5;                    /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -1191,19 +1563,14 @@ union uvh_gr1_tlb_mmr_control_u {
 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
-#define UVH_GR1_TLB_MMR_READ_DATA_HI                                    \
-                (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :         \
-                (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :         \
-                                UV3H_GR1_TLB_MMR_READ_DATA_HI))
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL
+#define UVH_GR1_TLB_MMR_READ_DATA_HI (                                  \
+        is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :                  \
+        is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :                  \
+        is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI :                  \
+        /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI)
 
 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
 
 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
@@ -1215,13 +1582,6 @@ union uvh_gr1_tlb_mmr_control_u {
 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 
 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 
 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
@@ -1245,15 +1605,24 @@ union uvh_gr1_tlb_mmr_control_u {
 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
 
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT         34
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          49
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        51
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       52
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       53
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x00000003ffffffffUL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK         0x0001fffc00000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0006000000000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0008000000000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0010000000000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0020000000000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
+
+
 union uvh_gr1_tlb_mmr_read_data_hi_u {
         unsigned long   v;
-        struct uvh_gr1_tlb_mmr_read_data_hi_s {
-                unsigned long   pfn:41;                         /* RO */
-                unsigned long   gaa:2;                          /* RO */
-                unsigned long   dirty:1;                        /* RO */
-                unsigned long   larger:1;                       /* RO */
-                unsigned long   rsvd_45_63:19;
-        } s;
         struct uv1h_gr1_tlb_mmr_read_data_hi_s {
                 unsigned long   pfn:41;                         /* RO */
                 unsigned long   gaa:2;                          /* RO */
@@ -1261,13 +1630,6 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
                 unsigned long   larger:1;                       /* RO */
                 unsigned long   rsvd_45_63:19;
         } s1;
-        struct uvxh_gr1_tlb_mmr_read_data_hi_s {
-                unsigned long   pfn:41;                         /* RO */
-                unsigned long   gaa:2;                          /* RO */
-                unsigned long   dirty:1;                        /* RO */
-                unsigned long   larger:1;                       /* RO */
-                unsigned long   rsvd_45_63:19;
-        } sx;
         struct uv2h_gr1_tlb_mmr_read_data_hi_s {
                 unsigned long   pfn:41;                         /* RO */
                 unsigned long   gaa:2;                          /* RO */
@@ -1284,6 +1646,16 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
                 unsigned long   undef_46_54:9;                  /* Undefined */
                 unsigned long   way_ecc:9;                      /* RO */
         } s3;
+        struct uv4h_gr1_tlb_mmr_read_data_hi_s {
+                unsigned long   pfn:34;                         /* RO */
+                unsigned long   pnid:15;                        /* RO */
+                unsigned long   gaa:2;                          /* RO */
+                unsigned long   dirty:1;                        /* RO */
+                unsigned long   larger:1;                       /* RO */
+                unsigned long   aa_ext:1;                       /* RO */
+                unsigned long   undef_54:1;                     /* Undefined */
+                unsigned long   way_ecc:9;                      /* RO */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -1292,10 +1664,12 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
-#define UVH_GR1_TLB_MMR_READ_DATA_LO                                    \
-                (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :         \
-                (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :         \
-                                UV3H_GR1_TLB_MMR_READ_DATA_LO))
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL
+#define UVH_GR1_TLB_MMR_READ_DATA_LO (                                  \
+        is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :                  \
+        is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :                  \
+        is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO :                  \
+        /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO)
 
 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
@@ -1332,6 +1706,14 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
+#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
+
+
 union uvh_gr1_tlb_mmr_read_data_lo_u {
         unsigned long   v;
         struct uvh_gr1_tlb_mmr_read_data_lo_s {
@@ -1359,6 +1741,11 @@ union uvh_gr1_tlb_mmr_read_data_lo_u {
                 unsigned long   asid:24;                        /* RO */
                 unsigned long   valid:1;                        /* RO */
         } s3;
+        struct uv4h_gr1_tlb_mmr_read_data_lo_s {
+                unsigned long   vpn:39;                         /* RO */
+                unsigned long   asid:24;                        /* RO */
+                unsigned long   valid:1;                        /* RO */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -1369,6 +1756,7 @@ union uvh_gr1_tlb_mmr_read_data_lo_u {
 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT                0
 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK                0x00ffffffffffffffUL
 
+
 union uvh_int_cmpb_u {
         unsigned long   v;
         struct uvh_int_cmpb_s {
@@ -1382,12 +1770,14 @@ union uvh_int_cmpb_u {
 /* ========================================================================= */
 #define UVH_INT_CMPC 0x22100UL
 
+
 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT               0
 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK               0x00ffffffffffffffUL
 
 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
 
+
 union uvh_int_cmpc_u {
         unsigned long   v;
         struct uvh_int_cmpc_s {
@@ -1401,12 +1791,14 @@ union uvh_int_cmpc_u {
 /* ========================================================================= */
 #define UVH_INT_CMPD 0x22180UL
 
+
 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT               0
 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK               0x00ffffffffffffffUL
 
 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
 
+
 union uvh_int_cmpd_u {
         unsigned long   v;
         struct uvh_int_cmpd_s {
@@ -1419,7 +1811,16 @@ union uvh_int_cmpd_u {
 /*                               UVH_IPI_INT                                 */
 /* ========================================================================= */
 #define UVH_IPI_INT 0x60500UL
-#define UVH_IPI_INT_32 0x348
+
+#define UV1H_IPI_INT_32 0x348
+#define UV2H_IPI_INT_32 0x348
+#define UV3H_IPI_INT_32 0x348
+#define UV4H_IPI_INT_32 0x268
+#define UVH_IPI_INT_32 (                                                \
+        is_uv1_hub() ? UV1H_IPI_INT_32 :                                \
+        is_uv2_hub() ? UV2H_IPI_INT_32 :                                \
+        is_uv3_hub() ? UV3H_IPI_INT_32 :                                \
+        /*is_uv4_hub*/ UV4H_IPI_INT_32)
 
 #define UVH_IPI_INT_VECTOR_SHFT                         0
 #define UVH_IPI_INT_DELIVERY_MODE_SHFT                  8
@@ -1432,6 +1833,7 @@ union uvh_int_cmpd_u {
 #define UVH_IPI_INT_APIC_ID_MASK                        0x0000ffffffff0000UL
 #define UVH_IPI_INT_SEND_MASK                           0x8000000000000000UL
 
+
 union uvh_ipi_int_u {
         unsigned long   v;
         struct uvh_ipi_int_s {
@@ -1448,103 +1850,269 @@ union uvh_ipi_int_u {
 /* ========================================================================= */
 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
+#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST")
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST (                           \
+        is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
+        is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
+        is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :           \
+        /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST)
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
 
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
+
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
+
+
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
+
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
+
 
 union uvh_lb_bau_intd_payload_queue_first_u {
         unsigned long   v;
-        struct uvh_lb_bau_intd_payload_queue_first_s {
+        struct uv1h_lb_bau_intd_payload_queue_first_s {
                 unsigned long   rsvd_0_3:4;
                 unsigned long   address:39;                     /* RW */
                 unsigned long   rsvd_43_48:6;
                 unsigned long   node_id:14;                     /* RW */
                 unsigned long   rsvd_63:1;
-        } s;
+        } s1;
+        struct uv2h_lb_bau_intd_payload_queue_first_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_48:6;
+                unsigned long   node_id:14;                     /* RW */
+                unsigned long   rsvd_63:1;
+        } s2;
+        struct uv3h_lb_bau_intd_payload_queue_first_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_48:6;
+                unsigned long   node_id:14;                     /* RW */
+                unsigned long   rsvd_63:1;
+        } s3;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
+#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST")
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST (                            \
+        is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
+        is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
+        is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :            \
+        /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST)
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
 
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
+
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
+
+
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
+
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
+
 
 union uvh_lb_bau_intd_payload_queue_last_u {
         unsigned long   v;
-        struct uvh_lb_bau_intd_payload_queue_last_s {
+        struct uv1h_lb_bau_intd_payload_queue_last_s {
                 unsigned long   rsvd_0_3:4;
                 unsigned long   address:39;                     /* RW */
                 unsigned long   rsvd_43_63:21;
-        } s;
+        } s1;
+        struct uv2h_lb_bau_intd_payload_queue_last_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s2;
+        struct uv3h_lb_bau_intd_payload_queue_last_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s3;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
+#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL")
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL (                            \
+        is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
+        is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
+        is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :            \
+        /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL)
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
 
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
+
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
+#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
+
+
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
+#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
+
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
+#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
+
 
 union uvh_lb_bau_intd_payload_queue_tail_u {
         unsigned long   v;
-        struct uvh_lb_bau_intd_payload_queue_tail_s {
+        struct uv1h_lb_bau_intd_payload_queue_tail_s {
                 unsigned long   rsvd_0_3:4;
                 unsigned long   address:39;                     /* RW */
                 unsigned long   rsvd_43_63:21;
-        } s;
+        } s1;
+        struct uv2h_lb_bau_intd_payload_queue_tail_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s2;
+        struct uv3h_lb_bau_intd_payload_queue_tail_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s3;
 };
 
 /* ========================================================================= */
 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
+#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE")
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE (                          \
+        is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
+        is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
+        is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :          \
+        /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE)
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
 
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
+
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
+
+
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
+
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
+
 
 union uvh_lb_bau_intd_software_acknowledge_u {
         unsigned long   v;
-        struct uvh_lb_bau_intd_software_acknowledge_s {
+        struct uv1h_lb_bau_intd_software_acknowledge_s {
                 unsigned long   pending_0:1;                    /* RW, W1C */
                 unsigned long   pending_1:1;                    /* RW, W1C */
                 unsigned long   pending_2:1;                    /* RW, W1C */
@@ -1562,27 +2130,84 @@ union uvh_lb_bau_intd_software_acknowledge_u {
                 unsigned long   timeout_6:1;                    /* RW, W1C */
                 unsigned long   timeout_7:1;                    /* RW, W1C */
                 unsigned long   rsvd_16_63:48;
-        } s;
+        } s1;
+        struct uv2h_lb_bau_intd_software_acknowledge_s {
+                unsigned long   pending_0:1;                    /* RW */
+                unsigned long   pending_1:1;                    /* RW */
+                unsigned long   pending_2:1;                    /* RW */
+                unsigned long   pending_3:1;                    /* RW */
+                unsigned long   pending_4:1;                    /* RW */
+                unsigned long   pending_5:1;                    /* RW */
+                unsigned long   pending_6:1;                    /* RW */
+                unsigned long   pending_7:1;                    /* RW */
+                unsigned long   timeout_0:1;                    /* RW */
+                unsigned long   timeout_1:1;                    /* RW */
+                unsigned long   timeout_2:1;                    /* RW */
+                unsigned long   timeout_3:1;                    /* RW */
+                unsigned long   timeout_4:1;                    /* RW */
+                unsigned long   timeout_5:1;                    /* RW */
+                unsigned long   timeout_6:1;                    /* RW */
+                unsigned long   timeout_7:1;                    /* RW */
+                unsigned long   rsvd_16_63:48;
+        } s2;
+        struct uv3h_lb_bau_intd_software_acknowledge_s {
+                unsigned long   pending_0:1;                    /* RW */
+                unsigned long   pending_1:1;                    /* RW */
+                unsigned long   pending_2:1;                    /* RW */
+                unsigned long   pending_3:1;                    /* RW */
+                unsigned long   pending_4:1;                    /* RW */
+                unsigned long   pending_5:1;                    /* RW */
+                unsigned long   pending_6:1;                    /* RW */
+                unsigned long   pending_7:1;                    /* RW */
+                unsigned long   timeout_0:1;                    /* RW */
+                unsigned long   timeout_1:1;                    /* RW */
+                unsigned long   timeout_2:1;                    /* RW */
+                unsigned long   timeout_3:1;                    /* RW */
+                unsigned long   timeout_4:1;                    /* RW */
+                unsigned long   timeout_5:1;                    /* RW */
+                unsigned long   timeout_6:1;                    /* RW */
+                unsigned long   timeout_7:1;                    /* RW */
+                unsigned long   rsvd_16_63:48;
+        } s3;
 };
 
 /* ========================================================================= */
 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
+#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
+#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
+#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
+#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS")
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS (                    \
+        is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
+        is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
+        is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :    \
+        /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS)
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
 
 
 /* ========================================================================= */
 /*                         UVH_LB_BAU_MISC_CONTROL                           */
 /* ========================================================================= */
-#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
-#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
-#define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL
-#define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL
-#define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL
+#define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL
+#define UVH_LB_BAU_MISC_CONTROL (                                       \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL :                       \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL :                       \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL :                       \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL)
+
+#define UV1H_LB_BAU_MISC_CONTROL_32 0xa10
+#define UV2H_LB_BAU_MISC_CONTROL_32 0xa10
+#define UV3H_LB_BAU_MISC_CONTROL_32 0xa10
+#define UV4H_LB_BAU_MISC_CONTROL_32 0xa18
+#define UVH_LB_BAU_MISC_CONTROL_32 (                                    \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 :                    \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 :                    \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 :                    \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32)
 
 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT    0
 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT          8
@@ -1590,8 +2215,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT     10
 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
-#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
@@ -1606,8 +2229,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK     0x0000000000000400UL
 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
-#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
@@ -1656,8 +2277,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
-#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
@@ -1679,8 +2298,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
-#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
@@ -1797,6 +2414,88 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
 
+#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
+#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
+#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
+#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
+#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
+#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
+#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT    15
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
+#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
+#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
+#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
+#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
+#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
+#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
+#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT       37
+#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
+#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46
+#define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
+#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
+#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
+#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
+#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
+#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK    0x00000000000f8000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK       0x0000002000000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL
+#define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
+
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \
+        uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK")
+#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK (        \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK)
+#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \
+        uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT")
+#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT (        \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT)
+#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK      \
+        uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK")
+#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK (     \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK)
+#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT      \
+        uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT")
+#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT (     \
+        is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
+        is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
+        is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
+        /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT)
+
 union uvh_lb_bau_misc_control_u {
         unsigned long   v;
         struct uvh_lb_bau_misc_control_s {
@@ -1806,8 +2505,7 @@ union uvh_lb_bau_misc_control_u {
                 unsigned long   force_lock_nop:1;               /* RW */
                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
                 unsigned long   descriptor_fetch_mode:1;        /* RW */
-                unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
-                unsigned long   intd_soft_ack_timeout_period:4; /* RW */
+                unsigned long   rsvd_15_19:5;
                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
@@ -1844,8 +2542,7 @@ union uvh_lb_bau_misc_control_u {
                 unsigned long   force_lock_nop:1;               /* RW */
                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
                 unsigned long   descriptor_fetch_mode:1;        /* RW */
-                unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
-                unsigned long   intd_soft_ack_timeout_period:4; /* RW */
+                unsigned long   rsvd_15_19:5;
                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
@@ -1918,13 +2615,59 @@ union uvh_lb_bau_misc_control_u {
                 unsigned long   rsvd_46_47:2;
                 unsigned long   fun:16;                         /* RW */
         } s3;
+        struct uv4h_lb_bau_misc_control_s {
+                unsigned long   rejection_delay:8;              /* RW */
+                unsigned long   apic_mode:1;                    /* RW */
+                unsigned long   force_broadcast:1;              /* RW */
+                unsigned long   force_lock_nop:1;               /* RW */
+                unsigned long   qpi_agent_presence_vector:3;    /* RW */
+                unsigned long   descriptor_fetch_mode:1;        /* RW */
+                unsigned long   rsvd_15_19:5;
+                unsigned long   enable_dual_mapping_mode:1;     /* RW */
+                unsigned long   vga_io_port_decode_enable:1;    /* RW */
+                unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
+                unsigned long   suppress_dest_registration:1;   /* RW */
+                unsigned long   programmed_initial_priority:3;  /* RW */
+                unsigned long   use_incoming_priority:1;        /* RW */
+                unsigned long   enable_programmed_initial_priority:1;/* RW */
+                unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
+                unsigned long   apic_mode_status:1;             /* RO */
+                unsigned long   suppress_interrupts_to_self:1;  /* RW */
+                unsigned long   enable_lock_based_system_flush:1;/* RW */
+                unsigned long   enable_extended_sb_status:1;    /* RW */
+                unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
+                unsigned long   use_legacy_descriptor_formats:1;/* RW */
+                unsigned long   suppress_quiesce_msgs_to_qpi:1; /* RW */
+                unsigned long   rsvd_37:1;
+                unsigned long   thread_kill_timebase:8;         /* RW */
+                unsigned long   address_interleave_select:1;    /* RW */
+                unsigned long   rsvd_47:1;
+                unsigned long   fun:16;                         /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
+#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
+#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
+#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
+#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL (                              \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL :              \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL :              \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL :              \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL)
+
+#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
+#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
+#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
+#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 (                           \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 :           \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32)
 
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT     0
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT      62
@@ -1933,6 +2676,7 @@ union uvh_lb_bau_misc_control_u {
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK      0x4000000000000000UL
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK      0x8000000000000000UL
 
+
 union uvh_lb_bau_sb_activation_control_u {
         unsigned long   v;
         struct uvh_lb_bau_sb_activation_control_s {
@@ -1946,12 +2690,30 @@ union uvh_lb_bau_sb_activation_control_u {
 /* ========================================================================= */
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
+#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
+#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 (                             \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 :             \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0)
+
+#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
+#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 (                          \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :          \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32)
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT   0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK   0xffffffffffffffffUL
 
+
 union uvh_lb_bau_sb_activation_status_0_u {
         unsigned long   v;
         struct uvh_lb_bau_sb_activation_status_0_s {
@@ -1962,12 +2724,30 @@ union uvh_lb_bau_sb_activation_status_0_u {
 /* ========================================================================= */
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
+#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
+#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 (                             \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 :             \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1)
+
+#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
+#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 (                          \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :          \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32)
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT   0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK   0xffffffffffffffffUL
 
+
 union uvh_lb_bau_sb_activation_status_1_u {
         unsigned long   v;
         struct uvh_lb_bau_sb_activation_status_1_s {
@@ -1978,23 +2758,55 @@ union uvh_lb_bau_sb_activation_status_1_u {
 /* ========================================================================= */
 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
+#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
+#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
+#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
+#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE (                                 \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE :                 \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE)
+
+#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
+#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
+#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
+#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 (                              \
+        is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 :              \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32)
 
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT      49
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK      0x7ffe000000000000UL
 
+#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
+
+
+#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
+
+#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
+
+#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL
+
+
 union uvh_lb_bau_sb_descriptor_base_u {
         unsigned long   v;
         struct uvh_lb_bau_sb_descriptor_base_s {
                 unsigned long   rsvd_0_11:12;
-                unsigned long   page_address:31;                /* RW */
-                unsigned long   rsvd_43_48:6;
+                unsigned long   rsvd_12_48:37;
                 unsigned long   node_id:14;                     /* RW */
                 unsigned long   rsvd_63:1;
         } s;
+        struct uv4h_lb_bau_sb_descriptor_base_s {
+                unsigned long   rsvd_0_11:12;
+                unsigned long   page_address:34;                /* RW */
+                unsigned long   rsvd_46_48:3;
+                unsigned long   node_id:14;                     /* RW */
+                unsigned long   rsvd_63:1;
+        } s4;
 };
 
 /* ========================================================================= */
@@ -2004,6 +2816,7 @@ union uvh_lb_bau_sb_descriptor_base_u {
 #define UV1H_NODE_ID 0x0UL
 #define UV2H_NODE_ID 0x0UL
 #define UV3H_NODE_ID 0x0UL
+#define UV4H_NODE_ID 0x0UL
 
 #define UVH_NODE_ID_FORCE1_SHFT                         0
 #define UVH_NODE_ID_MANUFACTURER_SHFT                   1
@@ -2080,6 +2893,26 @@ union uvh_lb_bau_sb_descriptor_base_u {
 #define UV3H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
 #define UV3H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
 
+#define UV4H_NODE_ID_FORCE1_SHFT                        0
+#define UV4H_NODE_ID_MANUFACTURER_SHFT                  1
+#define UV4H_NODE_ID_PART_NUMBER_SHFT                   12
+#define UV4H_NODE_ID_REVISION_SHFT                      28
+#define UV4H_NODE_ID_NODE_ID_SHFT                       32
+#define UV4H_NODE_ID_ROUTER_SELECT_SHFT                 48
+#define UV4H_NODE_ID_RESERVED_2_SHFT                    49
+#define UV4H_NODE_ID_NODES_PER_BIT_SHFT                 50
+#define UV4H_NODE_ID_NI_PORT_SHFT                       57
+#define UV4H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
+#define UV4H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
+#define UV4H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
+#define UV4H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
+#define UV4H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
+#define UV4H_NODE_ID_ROUTER_SELECT_MASK                 0x0001000000000000UL
+#define UV4H_NODE_ID_RESERVED_2_MASK                    0x0002000000000000UL
+#define UV4H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
+#define UV4H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
+
+
 union uvh_node_id_u {
         unsigned long   v;
         struct uvh_node_id_s {
@@ -2137,17 +2970,40 @@ union uvh_node_id_u {
                 unsigned long   ni_port:5;                      /* RO */
                 unsigned long   rsvd_62_63:2;
         } s3;
+        struct uv4h_node_id_s {
+                unsigned long   force1:1;                       /* RO */
+                unsigned long   manufacturer:11;                /* RO */
+                unsigned long   part_number:16;                 /* RO */
+                unsigned long   revision:4;                     /* RO */
+                unsigned long   node_id:15;                     /* RW */
+                unsigned long   rsvd_47:1;
+                unsigned long   router_select:1;                /* RO */
+                unsigned long   rsvd_49:1;
+                unsigned long   nodes_per_bit:7;                /* RO */
+                unsigned long   ni_port:5;                      /* RO */
+                unsigned long   rsvd_62_63:2;
+        } s4;
 };
 
 /* ========================================================================= */
 /*                          UVH_NODE_PRESENT_TABLE                           */
 /* ========================================================================= */
 #define UVH_NODE_PRESENT_TABLE 0x1400UL
-#define UVH_NODE_PRESENT_TABLE_DEPTH 16
+
+#define UV1H_NODE_PRESENT_TABLE_DEPTH 16
+#define UV2H_NODE_PRESENT_TABLE_DEPTH 16
+#define UV3H_NODE_PRESENT_TABLE_DEPTH 16
+#define UV4H_NODE_PRESENT_TABLE_DEPTH 4
+#define UVH_NODE_PRESENT_TABLE_DEPTH (                                  \
+        is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH :                  \
+        is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH :                  \
+        is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH :                  \
+        /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH)
 
 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT               0
 #define UVH_NODE_PRESENT_TABLE_NODES_MASK               0xffffffffffffffffUL
 
+
 union uvh_node_present_table_u {
         unsigned long   v;
         struct uvh_node_present_table_s {
@@ -2158,7 +3014,15 @@ union uvh_node_present_table_u {
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR (                      \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :      \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR)
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
@@ -2167,6 +3031,7 @@ union uvh_node_present_table_u {
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
 
+
 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
@@ -2182,7 +3047,15 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR (                      \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :      \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR)
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
@@ -2191,6 +3064,7 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
 
+
 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
@@ -2206,7 +3080,15 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR (                      \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :      \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR)
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
@@ -2215,6 +3097,7 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
 
+
 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
@@ -2230,11 +3113,20 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR (                     \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :     \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR)
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
+
 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
@@ -2247,11 +3139,20 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR (                     \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :     \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR)
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
+
 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
@@ -2264,11 +3165,20 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR (                     \
+        is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
+        is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
+        is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :     \
+        /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR)
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
+
 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
@@ -2281,14 +3191,17 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 /* ========================================================================= */
 /*                          UVH_RH_GAM_CONFIG_MMR                            */
 /* ========================================================================= */
-#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
+#define UV4H_RH_GAM_CONFIG_MMR 0x480000UL
+#define UVH_RH_GAM_CONFIG_MMR (                                         \
+        is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR :                         \
+        is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR :                         \
+        is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR :                         \
+        /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR)
 
-#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT                0
 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT                6
-#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK                0x000000000000003fUL
 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK                0x00000000000003c0UL
 
 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
@@ -2298,9 +3211,7 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK           0x0000000000001000UL
 
-#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
-#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
 
 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
@@ -2313,10 +3224,14 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
 
+#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
+#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
+
+
 union uvh_rh_gam_config_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_config_mmr_s {
-                unsigned long   m_skt:6;                        /* RW */
+                unsigned long   rsvd_0_5:6;
                 unsigned long   n_skt:4;                        /* RW */
                 unsigned long   rsvd_10_63:54;
         } s;
@@ -2328,7 +3243,7 @@ union uvh_rh_gam_config_mmr_u {
                 unsigned long   rsvd_13_63:51;
         } s1;
         struct uvxh_rh_gam_config_mmr_s {
-                unsigned long   m_skt:6;                        /* RW */
+                unsigned long   rsvd_0_5:6;
                 unsigned long   n_skt:4;                        /* RW */
                 unsigned long   rsvd_10_63:54;
         } sx;
@@ -2342,20 +3257,28 @@ union uvh_rh_gam_config_mmr_u {
                 unsigned long   n_skt:4;                        /* RW */
                 unsigned long   rsvd_10_63:54;
         } s3;
+        struct uv4h_rh_gam_config_mmr_s {
+                unsigned long   rsvd_0_5:6;
+                unsigned long   n_skt:4;                        /* RW */
+                unsigned long   rsvd_10_63:54;
+        } s4;
 };
 
 /* ========================================================================= */
 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR (                             \
+        is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
+        is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
+        is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :             \
+        /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR)
 
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT     28
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT    52
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffff0000000UL
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK    0x00f0000000000000UL
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK   0x8000000000000000UL
 
@@ -2368,10 +3291,8 @@ union uvh_rh_gam_config_mmr_u {
 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
@@ -2391,12 +3312,28 @@ union uvh_rh_gam_config_mmr_u {
 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK    0x4000000000000000UL
 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    26
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
+
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK (                   \
+        is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
+        is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
+        is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :   \
+        /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK)
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT (                   \
+        is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
+        is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
+        is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :   \
+        /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT)
+
 union uvh_rh_gam_gru_overlay_config_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_gru_overlay_config_mmr_s {
-                unsigned long   rsvd_0_27:28;
-                unsigned long   base:18;                        /* RW */
-                unsigned long   rsvd_46_51:6;
+                unsigned long   rsvd_0_51:52;
                 unsigned long   n_gru:4;                        /* RW */
                 unsigned long   rsvd_56_62:7;
                 unsigned long   enable:1;                       /* RW */
@@ -2412,8 +3349,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
                 unsigned long   enable:1;                       /* RW */
         } s1;
         struct uvxh_rh_gam_gru_overlay_config_mmr_s {
-                unsigned long   rsvd_0_27:28;
-                unsigned long   base:18;                        /* RW */
+                unsigned long   rsvd_0_45:46;
                 unsigned long   rsvd_46_51:6;
                 unsigned long   n_gru:4;                        /* RW */
                 unsigned long   rsvd_56_62:7;
@@ -2436,6 +3372,15 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
                 unsigned long   mode:1;                         /* RW */
                 unsigned long   enable:1;                       /* RW */
         } s3;
+        struct uv4h_rh_gam_gru_overlay_config_mmr_s {
+                unsigned long   rsvd_0_24:25;
+                unsigned long   undef_25:1;                     /* Undefined */
+                unsigned long   base:20;                        /* RW */
+                unsigned long   rsvd_46_51:6;
+                unsigned long   n_gru:4;                        /* RW */
+                unsigned long   rsvd_56_62:7;
+                unsigned long   enable:1;                       /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -2443,6 +3388,14 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
 /* ========================================================================= */
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR (                           \
+        is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
+        is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
+        is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :           \
+        /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
+
 
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  30
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
@@ -2453,6 +3406,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
+
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  27
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
@@ -2462,6 +3416,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
+
 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
         unsigned long   v;
         struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
@@ -2485,10 +3440,15 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
 /* ========================================================================= */
 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
+#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR (                             \
+        is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
+        is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
+        is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :             \
+        /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR)
 
 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT     26
 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
@@ -2517,6 +3477,12 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
+#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
+#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
+#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
+
+
 union uvh_rh_gam_mmr_overlay_config_mmr_u {
         unsigned long   v;
         struct uvh_rh_gam_mmr_overlay_config_mmr_s {
@@ -2550,16 +3516,31 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u {
                 unsigned long   rsvd_46_62:17;
                 unsigned long   enable:1;                       /* RW */
         } s3;
+        struct uv4h_rh_gam_mmr_overlay_config_mmr_s {
+                unsigned long   rsvd_0_25:26;
+                unsigned long   base:20;                        /* RW */
+                unsigned long   rsvd_46_62:17;
+                unsigned long   enable:1;                       /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
 /*                                 UVH_RTC                                   */
 /* ========================================================================= */
-#define UVH_RTC 0x340000UL
+#define UV1H_RTC 0x340000UL
+#define UV2H_RTC 0x340000UL
+#define UV3H_RTC 0x340000UL
+#define UV4H_RTC 0xe0000UL
+#define UVH_RTC (                                                       \
+        is_uv1_hub() ? UV1H_RTC :                                       \
+        is_uv2_hub() ? UV2H_RTC :                                       \
+        is_uv3_hub() ? UV3H_RTC :                                       \
+        /*is_uv4_hub*/ UV4H_RTC)
 
 #define UVH_RTC_REAL_TIME_CLOCK_SHFT                    0
 #define UVH_RTC_REAL_TIME_CLOCK_MASK                    0x00ffffffffffffffUL
 
+
 union uvh_rtc_u {
         unsigned long   v;
         struct uvh_rtc_s {
@@ -2590,6 +3571,7 @@ union uvh_rtc_u {
 #define UVH_RTC1_INT_CONFIG_M_MASK                      0x0000000000010000UL
 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 
+
 union uvh_rtc1_int_config_u {
         unsigned long   v;
         struct uvh_rtc1_int_config_s {
@@ -2609,12 +3591,30 @@ union uvh_rtc1_int_config_u {
 /* ========================================================================= */
 /*                               UVH_SCRATCH5                                */
 /* ========================================================================= */
-#define UVH_SCRATCH5 0x2d0200UL
-#define UVH_SCRATCH5_32 0x778
+#define UV1H_SCRATCH5 0x2d0200UL
+#define UV2H_SCRATCH5 0x2d0200UL
+#define UV3H_SCRATCH5 0x2d0200UL
+#define UV4H_SCRATCH5 0xb0200UL
+#define UVH_SCRATCH5 (                                                  \
+        is_uv1_hub() ? UV1H_SCRATCH5 :                                  \
+        is_uv2_hub() ? UV2H_SCRATCH5 :                                  \
+        is_uv3_hub() ? UV3H_SCRATCH5 :                                  \
+        /*is_uv4_hub*/ UV4H_SCRATCH5)
+
+#define UV1H_SCRATCH5_32 0x778
+#define UV2H_SCRATCH5_32 0x778
+#define UV3H_SCRATCH5_32 0x778
+#define UV4H_SCRATCH5_32 0x798
+#define UVH_SCRATCH5_32 (                                               \
+        is_uv1_hub() ? UV1H_SCRATCH5_32 :                               \
+        is_uv2_hub() ? UV2H_SCRATCH5_32 :                               \
+        is_uv3_hub() ? UV3H_SCRATCH5_32 :                               \
+        /*is_uv4_hub*/ UV4H_SCRATCH5_32)
 
 #define UVH_SCRATCH5_SCRATCH5_SHFT                      0
 #define UVH_SCRATCH5_SCRATCH5_MASK                      0xffffffffffffffffUL
 
+
 union uvh_scratch5_u {
         unsigned long   v;
         struct uvh_scratch5_s {
@@ -2625,14 +3625,39 @@ union uvh_scratch5_u {
 /* ========================================================================= */
 /*                            UVH_SCRATCH5_ALIAS                             */
 /* ========================================================================= */
-#define UVH_SCRATCH5_ALIAS 0x2d0208UL
-#define UVH_SCRATCH5_ALIAS_32 0x780
+#define UV1H_SCRATCH5_ALIAS 0x2d0208UL
+#define UV2H_SCRATCH5_ALIAS 0x2d0208UL
+#define UV3H_SCRATCH5_ALIAS 0x2d0208UL
+#define UV4H_SCRATCH5_ALIAS 0xb0208UL
+#define UVH_SCRATCH5_ALIAS (                                            \
+        is_uv1_hub() ? UV1H_SCRATCH5_ALIAS :                            \
+        is_uv2_hub() ? UV2H_SCRATCH5_ALIAS :                            \
+        is_uv3_hub() ? UV3H_SCRATCH5_ALIAS :                            \
+        /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS)
+
+#define UV1H_SCRATCH5_ALIAS_32 0x780
+#define UV2H_SCRATCH5_ALIAS_32 0x780
+#define UV3H_SCRATCH5_ALIAS_32 0x780
+#define UV4H_SCRATCH5_ALIAS_32 0x7a0
+#define UVH_SCRATCH5_ALIAS_32 (                                         \
+        is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 :                         \
+        is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 :                         \
+        is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 :                         \
+        /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32)
 
 
 /* ========================================================================= */
 /*                           UVH_SCRATCH5_ALIAS_2                            */
 /* ========================================================================= */
-#define UVH_SCRATCH5_ALIAS_2 0x2d0210UL
+#define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL
+#define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
+#define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
+#define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
+#define UVH_SCRATCH5_ALIAS_2 (                                          \
+        is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 :                          \
+        is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 :                          \
+        is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 :                          \
+        /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2)
 #define UVH_SCRATCH5_ALIAS_2_32 0x788
 
 
@@ -2640,76 +3665,255 @@ union uvh_scratch5_u {
 /*                          UVXH_EVENT_OCCURRED2                             */
 /* ========================================================================= */
 #define UVXH_EVENT_OCCURRED2 0x70100UL
-#define UVXH_EVENT_OCCURRED2_32 0xb68
-
-#define UVXH_EVENT_OCCURRED2_RTC_0_SHFT                 0
-#define UVXH_EVENT_OCCURRED2_RTC_1_SHFT                 1
-#define UVXH_EVENT_OCCURRED2_RTC_2_SHFT                 2
-#define UVXH_EVENT_OCCURRED2_RTC_3_SHFT                 3
-#define UVXH_EVENT_OCCURRED2_RTC_4_SHFT                 4
-#define UVXH_EVENT_OCCURRED2_RTC_5_SHFT                 5
-#define UVXH_EVENT_OCCURRED2_RTC_6_SHFT                 6
-#define UVXH_EVENT_OCCURRED2_RTC_7_SHFT                 7
-#define UVXH_EVENT_OCCURRED2_RTC_8_SHFT                 8
-#define UVXH_EVENT_OCCURRED2_RTC_9_SHFT                 9
-#define UVXH_EVENT_OCCURRED2_RTC_10_SHFT                10
-#define UVXH_EVENT_OCCURRED2_RTC_11_SHFT                11
-#define UVXH_EVENT_OCCURRED2_RTC_12_SHFT                12
-#define UVXH_EVENT_OCCURRED2_RTC_13_SHFT                13
-#define UVXH_EVENT_OCCURRED2_RTC_14_SHFT                14
-#define UVXH_EVENT_OCCURRED2_RTC_15_SHFT                15
-#define UVXH_EVENT_OCCURRED2_RTC_16_SHFT                16
-#define UVXH_EVENT_OCCURRED2_RTC_17_SHFT                17
-#define UVXH_EVENT_OCCURRED2_RTC_18_SHFT                18
-#define UVXH_EVENT_OCCURRED2_RTC_19_SHFT                19
-#define UVXH_EVENT_OCCURRED2_RTC_20_SHFT                20
-#define UVXH_EVENT_OCCURRED2_RTC_21_SHFT                21
-#define UVXH_EVENT_OCCURRED2_RTC_22_SHFT                22
-#define UVXH_EVENT_OCCURRED2_RTC_23_SHFT                23
-#define UVXH_EVENT_OCCURRED2_RTC_24_SHFT                24
-#define UVXH_EVENT_OCCURRED2_RTC_25_SHFT                25
-#define UVXH_EVENT_OCCURRED2_RTC_26_SHFT                26
-#define UVXH_EVENT_OCCURRED2_RTC_27_SHFT                27
-#define UVXH_EVENT_OCCURRED2_RTC_28_SHFT                28
-#define UVXH_EVENT_OCCURRED2_RTC_29_SHFT                29
-#define UVXH_EVENT_OCCURRED2_RTC_30_SHFT                30
-#define UVXH_EVENT_OCCURRED2_RTC_31_SHFT                31
-#define UVXH_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
-#define UVXH_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
-#define UVXH_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
-#define UVXH_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
-#define UVXH_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
-#define UVXH_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
-#define UVXH_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
-#define UVXH_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
-#define UVXH_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
-#define UVXH_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
-#define UVXH_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
-#define UVXH_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
-#define UVXH_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
-#define UVXH_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
-#define UVXH_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
-#define UVXH_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
-#define UVXH_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
-#define UVXH_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
-#define UVXH_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
-#define UVXH_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
-#define UVXH_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
-#define UVXH_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
-#define UVXH_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
-#define UVXH_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
-#define UVXH_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
-#define UVXH_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
-
-union uvxh_event_occurred2_u {
+
+#define UV2H_EVENT_OCCURRED2_32 0xb68
+#define UV3H_EVENT_OCCURRED2_32 0xb68
+#define UV4H_EVENT_OCCURRED2_32 0x608
+#define UVH_EVENT_OCCURRED2_32 (                                        \
+        is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 :                        \
+        is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 :                        \
+        /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32)
+
+
+#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT                 0
+#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT                 1
+#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT                 2
+#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT                 3
+#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT                 4
+#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT                 5
+#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT                 6
+#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT                 7
+#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT                 8
+#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT                 9
+#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT                10
+#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT                11
+#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT                12
+#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT                13
+#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT                14
+#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT                15
+#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT                16
+#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT                17
+#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT                18
+#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT                19
+#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT                20
+#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT                21
+#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT                22
+#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT                23
+#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT                24
+#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT                25
+#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT                26
+#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT                27
+#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT                28
+#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT                29
+#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT                30
+#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT                31
+#define UV2H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
+#define UV2H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
+#define UV2H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
+#define UV2H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
+#define UV2H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
+#define UV2H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
+#define UV2H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
+#define UV2H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
+#define UV2H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
+#define UV2H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
+#define UV2H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
+#define UV2H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
+#define UV2H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
+#define UV2H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
+#define UV2H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
+#define UV2H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
+
+#define UV3H_EVENT_OCCURRED2_RTC_0_SHFT                 0
+#define UV3H_EVENT_OCCURRED2_RTC_1_SHFT                 1
+#define UV3H_EVENT_OCCURRED2_RTC_2_SHFT                 2
+#define UV3H_EVENT_OCCURRED2_RTC_3_SHFT                 3
+#define UV3H_EVENT_OCCURRED2_RTC_4_SHFT                 4
+#define UV3H_EVENT_OCCURRED2_RTC_5_SHFT                 5
+#define UV3H_EVENT_OCCURRED2_RTC_6_SHFT                 6
+#define UV3H_EVENT_OCCURRED2_RTC_7_SHFT                 7
+#define UV3H_EVENT_OCCURRED2_RTC_8_SHFT                 8
+#define UV3H_EVENT_OCCURRED2_RTC_9_SHFT                 9
+#define UV3H_EVENT_OCCURRED2_RTC_10_SHFT                10
+#define UV3H_EVENT_OCCURRED2_RTC_11_SHFT                11
+#define UV3H_EVENT_OCCURRED2_RTC_12_SHFT                12
+#define UV3H_EVENT_OCCURRED2_RTC_13_SHFT                13
+#define UV3H_EVENT_OCCURRED2_RTC_14_SHFT                14
+#define UV3H_EVENT_OCCURRED2_RTC_15_SHFT                15
+#define UV3H_EVENT_OCCURRED2_RTC_16_SHFT                16
+#define UV3H_EVENT_OCCURRED2_RTC_17_SHFT                17
+#define UV3H_EVENT_OCCURRED2_RTC_18_SHFT                18
+#define UV3H_EVENT_OCCURRED2_RTC_19_SHFT                19
+#define UV3H_EVENT_OCCURRED2_RTC_20_SHFT                20
+#define UV3H_EVENT_OCCURRED2_RTC_21_SHFT                21
+#define UV3H_EVENT_OCCURRED2_RTC_22_SHFT                22
+#define UV3H_EVENT_OCCURRED2_RTC_23_SHFT                23
+#define UV3H_EVENT_OCCURRED2_RTC_24_SHFT                24
+#define UV3H_EVENT_OCCURRED2_RTC_25_SHFT                25
+#define UV3H_EVENT_OCCURRED2_RTC_26_SHFT                26
+#define UV3H_EVENT_OCCURRED2_RTC_27_SHFT                27
+#define UV3H_EVENT_OCCURRED2_RTC_28_SHFT                28
+#define UV3H_EVENT_OCCURRED2_RTC_29_SHFT                29
+#define UV3H_EVENT_OCCURRED2_RTC_30_SHFT                30
+#define UV3H_EVENT_OCCURRED2_RTC_31_SHFT                31
+#define UV3H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
+#define UV3H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
+#define UV3H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
+#define UV3H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
+#define UV3H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
+#define UV3H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
+#define UV3H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
+#define UV3H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
+#define UV3H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
+#define UV3H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
+#define UV3H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
+#define UV3H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
+#define UV3H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
+#define UV3H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
+#define UV3H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
+#define UV3H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
+#define UV3H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
+#define UV3H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
+#define UV3H_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
+#define UV3H_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
+#define UV3H_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
+#define UV3H_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
+#define UV3H_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
+#define UV3H_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
+#define UV3H_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
+#define UV3H_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
+
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
+#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT      16
+#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT     17
+#define UV4H_EVENT_OCCURRED2_RTC_0_SHFT                 18
+#define UV4H_EVENT_OCCURRED2_RTC_1_SHFT                 19
+#define UV4H_EVENT_OCCURRED2_RTC_2_SHFT                 20
+#define UV4H_EVENT_OCCURRED2_RTC_3_SHFT                 21
+#define UV4H_EVENT_OCCURRED2_RTC_4_SHFT                 22
+#define UV4H_EVENT_OCCURRED2_RTC_5_SHFT                 23
+#define UV4H_EVENT_OCCURRED2_RTC_6_SHFT                 24
+#define UV4H_EVENT_OCCURRED2_RTC_7_SHFT                 25
+#define UV4H_EVENT_OCCURRED2_RTC_8_SHFT                 26
+#define UV4H_EVENT_OCCURRED2_RTC_9_SHFT                 27
+#define UV4H_EVENT_OCCURRED2_RTC_10_SHFT                28
+#define UV4H_EVENT_OCCURRED2_RTC_11_SHFT                29
+#define UV4H_EVENT_OCCURRED2_RTC_12_SHFT                30
+#define UV4H_EVENT_OCCURRED2_RTC_13_SHFT                31
+#define UV4H_EVENT_OCCURRED2_RTC_14_SHFT                32
+#define UV4H_EVENT_OCCURRED2_RTC_15_SHFT                33
+#define UV4H_EVENT_OCCURRED2_RTC_16_SHFT                34
+#define UV4H_EVENT_OCCURRED2_RTC_17_SHFT                35
+#define UV4H_EVENT_OCCURRED2_RTC_18_SHFT                36
+#define UV4H_EVENT_OCCURRED2_RTC_19_SHFT                37
+#define UV4H_EVENT_OCCURRED2_RTC_20_SHFT                38
+#define UV4H_EVENT_OCCURRED2_RTC_21_SHFT                39
+#define UV4H_EVENT_OCCURRED2_RTC_22_SHFT                40
+#define UV4H_EVENT_OCCURRED2_RTC_23_SHFT                41
+#define UV4H_EVENT_OCCURRED2_RTC_24_SHFT                42
+#define UV4H_EVENT_OCCURRED2_RTC_25_SHFT                43
+#define UV4H_EVENT_OCCURRED2_RTC_26_SHFT                44
+#define UV4H_EVENT_OCCURRED2_RTC_27_SHFT                45
+#define UV4H_EVENT_OCCURRED2_RTC_28_SHFT                46
+#define UV4H_EVENT_OCCURRED2_RTC_29_SHFT                47
+#define UV4H_EVENT_OCCURRED2_RTC_30_SHFT                48
+#define UV4H_EVENT_OCCURRED2_RTC_31_SHFT                49
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
+#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK      0x0000000000010000UL
+#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK     0x0000000000020000UL
+#define UV4H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000040000UL
+#define UV4H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000080000UL
+#define UV4H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000100000UL
+#define UV4H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000200000UL
+#define UV4H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000400000UL
+#define UV4H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000800000UL
+#define UV4H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000001000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000002000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000004000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000008000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000010000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000020000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000040000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000080000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000100000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000200000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000400000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000800000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_18_MASK                0x0000001000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_19_MASK                0x0000002000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_20_MASK                0x0000004000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_21_MASK                0x0000008000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_22_MASK                0x0000010000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_23_MASK                0x0000020000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_24_MASK                0x0000040000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_25_MASK                0x0000080000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_26_MASK                0x0000100000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_27_MASK                0x0000200000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_28_MASK                0x0000400000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_29_MASK                0x0000800000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_30_MASK                0x0001000000000000UL
+#define UV4H_EVENT_OCCURRED2_RTC_31_MASK                0x0002000000000000UL
+
+#define UVXH_EVENT_OCCURRED2_RTC_1_MASK (                               \
+        is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK :                \
+        is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK :                \
+        /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK)
+
+union uvh_event_occurred2_u {
         unsigned long   v;
-        struct uvxh_event_occurred2_s {
+        struct uv2h_event_occurred2_s {
                 unsigned long   rtc_0:1;                        /* RW */
                 unsigned long   rtc_1:1;                        /* RW */
                 unsigned long   rtc_2:1;                        /* RW */
@@ -2743,25 +3947,129 @@ union uvxh_event_occurred2_u {
                 unsigned long   rtc_30:1;                       /* RW */
                 unsigned long   rtc_31:1;                       /* RW */
                 unsigned long   rsvd_32_63:32;
-        } sx;
+        } s2;
+        struct uv3h_event_occurred2_s {
+                unsigned long   rtc_0:1;                        /* RW */
+                unsigned long   rtc_1:1;                        /* RW */
+                unsigned long   rtc_2:1;                        /* RW */
+                unsigned long   rtc_3:1;                        /* RW */
+                unsigned long   rtc_4:1;                        /* RW */
+                unsigned long   rtc_5:1;                        /* RW */
+                unsigned long   rtc_6:1;                        /* RW */
+                unsigned long   rtc_7:1;                        /* RW */
+                unsigned long   rtc_8:1;                        /* RW */
+                unsigned long   rtc_9:1;                        /* RW */
+                unsigned long   rtc_10:1;                       /* RW */
+                unsigned long   rtc_11:1;                       /* RW */
+                unsigned long   rtc_12:1;                       /* RW */
+                unsigned long   rtc_13:1;                       /* RW */
+                unsigned long   rtc_14:1;                       /* RW */
+                unsigned long   rtc_15:1;                       /* RW */
+                unsigned long   rtc_16:1;                       /* RW */
+                unsigned long   rtc_17:1;                       /* RW */
+                unsigned long   rtc_18:1;                       /* RW */
+                unsigned long   rtc_19:1;                       /* RW */
+                unsigned long   rtc_20:1;                       /* RW */
+                unsigned long   rtc_21:1;                       /* RW */
+                unsigned long   rtc_22:1;                       /* RW */
+                unsigned long   rtc_23:1;                       /* RW */
+                unsigned long   rtc_24:1;                       /* RW */
+                unsigned long   rtc_25:1;                       /* RW */
+                unsigned long   rtc_26:1;                       /* RW */
+                unsigned long   rtc_27:1;                       /* RW */
+                unsigned long   rtc_28:1;                       /* RW */
+                unsigned long   rtc_29:1;                       /* RW */
+                unsigned long   rtc_30:1;                       /* RW */
+                unsigned long   rtc_31:1;                       /* RW */
+                unsigned long   rsvd_32_63:32;
+        } s3;
+        struct uv4h_event_occurred2_s {
+                unsigned long   message_accelerator_int0:1;     /* RW */
+                unsigned long   message_accelerator_int1:1;     /* RW */
+                unsigned long   message_accelerator_int2:1;     /* RW */
+                unsigned long   message_accelerator_int3:1;     /* RW */
+                unsigned long   message_accelerator_int4:1;     /* RW */
+                unsigned long   message_accelerator_int5:1;     /* RW */
+                unsigned long   message_accelerator_int6:1;     /* RW */
+                unsigned long   message_accelerator_int7:1;     /* RW */
+                unsigned long   message_accelerator_int8:1;     /* RW */
+                unsigned long   message_accelerator_int9:1;     /* RW */
+                unsigned long   message_accelerator_int10:1;    /* RW */
+                unsigned long   message_accelerator_int11:1;    /* RW */
+                unsigned long   message_accelerator_int12:1;    /* RW */
+                unsigned long   message_accelerator_int13:1;    /* RW */
+                unsigned long   message_accelerator_int14:1;    /* RW */
+                unsigned long   message_accelerator_int15:1;    /* RW */
+                unsigned long   rtc_interval_int:1;             /* RW */
+                unsigned long   bau_dashboard_int:1;            /* RW */
+                unsigned long   rtc_0:1;                        /* RW */
+                unsigned long   rtc_1:1;                        /* RW */
+                unsigned long   rtc_2:1;                        /* RW */
+                unsigned long   rtc_3:1;                        /* RW */
+                unsigned long   rtc_4:1;                        /* RW */
+                unsigned long   rtc_5:1;                        /* RW */
+                unsigned long   rtc_6:1;                        /* RW */
+                unsigned long   rtc_7:1;                        /* RW */
+                unsigned long   rtc_8:1;                        /* RW */
+                unsigned long   rtc_9:1;                        /* RW */
+                unsigned long   rtc_10:1;                       /* RW */
+                unsigned long   rtc_11:1;                       /* RW */
+                unsigned long   rtc_12:1;                       /* RW */
+                unsigned long   rtc_13:1;                       /* RW */
+                unsigned long   rtc_14:1;                       /* RW */
+                unsigned long   rtc_15:1;                       /* RW */
+                unsigned long   rtc_16:1;                       /* RW */
+                unsigned long   rtc_17:1;                       /* RW */
+                unsigned long   rtc_18:1;                       /* RW */
+                unsigned long   rtc_19:1;                       /* RW */
+                unsigned long   rtc_20:1;                       /* RW */
+                unsigned long   rtc_21:1;                       /* RW */
+                unsigned long   rtc_22:1;                       /* RW */
+                unsigned long   rtc_23:1;                       /* RW */
+                unsigned long   rtc_24:1;                       /* RW */
+                unsigned long   rtc_25:1;                       /* RW */
+                unsigned long   rtc_26:1;                       /* RW */
+                unsigned long   rtc_27:1;                       /* RW */
+                unsigned long   rtc_28:1;                       /* RW */
+                unsigned long   rtc_29:1;                       /* RW */
+                unsigned long   rtc_30:1;                       /* RW */
+                unsigned long   rtc_31:1;                       /* RW */
+                unsigned long   rsvd_50_63:14;
+        } s4;
 };
 
 /* ========================================================================= */
 /*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
 /* ========================================================================= */
 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
-#define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70
+
+#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
+#define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70
+#define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610
+#define UVH_EVENT_OCCURRED2_ALIAS_32 (                                  \
+        is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 :                  \
+        is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 :                  \
+        /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32)
 
 
 /* ========================================================================= */
 /*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
 /* ========================================================================= */
-#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
-#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 (                             \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 :             \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 :             \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2)
+
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
+#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 (                          \
+        is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :          \
+        is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :          \
+        /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32)
 
 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
@@ -2772,6 +4080,10 @@ union uvxh_event_occurred2_u {
 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
 
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
+#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
+
+
 union uvxh_lb_bau_sb_activation_status_2_u {
         unsigned long   v;
         struct uvxh_lb_bau_sb_activation_status_2_s {
@@ -2783,6 +4095,9 @@ union uvxh_lb_bau_sb_activation_status_2_u {
         struct uv3h_lb_bau_sb_activation_status_2_s {
                 unsigned long   aux_error:64;                   /* RW */
         } s3;
+        struct uv4h_lb_bau_sb_activation_status_2_s {
+                unsigned long   aux_error:64;                   /* RW */
+        } s4;
 };
 
 /* ========================================================================= */
@@ -2823,26 +4138,6 @@ union uv3h_gr0_gam_gr_config_u {
 };
 
 /* ========================================================================= */
-/*                          UV3H_GR1_GAM_GR_CONFIG                           */
-/* ========================================================================= */
-#define UV3H_GR1_GAM_GR_CONFIG                          0x1000028UL
-
-#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT               0
-#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT            10
-#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK               0x000000000000003fUL
-#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK            0x0000000000000400UL
-
-union uv3h_gr1_gam_gr_config_u {
-        unsigned long   v;
-        struct uv3h_gr1_gam_gr_config_s {
-                unsigned long   m_skt:6;                        /* RW */
-                unsigned long   undef_6_9:4;                    /* Undefined */
-                unsigned long   subspace:1;                     /* RW */
-                unsigned long   reserved:53;
-        } s3;
-};
-
-/* ========================================================================= */
 /*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                   */
 /* ========================================================================= */
 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR           0x1603000UL
@@ -2924,5 +4219,67 @@ union uv3h_rh_gam_mmioh_redirect_config1_mmr_u {
         } s3;
 };
 
+/* ========================================================================= */
+/*                       UV4H_LB_PROC_INTD_QUEUE_FIRST                       */
+/* ========================================================================= */
+#define UV4H_LB_PROC_INTD_QUEUE_FIRST                   0xa4100UL
+
+#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6
+#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL
+
+union uv4h_lb_proc_intd_queue_first_u {
+        unsigned long   v;
+        struct uv4h_lb_proc_intd_queue_first_s {
+                unsigned long   undef_0_5:6;                    /* Undefined */
+                unsigned long   first_payload_address:40;       /* RW */
+        } s4;
+};
+
+/* ========================================================================= */
+/*                       UV4H_LB_PROC_INTD_QUEUE_LAST                        */
+/* ========================================================================= */
+#define UV4H_LB_PROC_INTD_QUEUE_LAST                    0xa4108UL
+
+#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5
+#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL
+
+union uv4h_lb_proc_intd_queue_last_u {
+        unsigned long   v;
+        struct uv4h_lb_proc_intd_queue_last_s {
+                unsigned long   undef_0_4:5;                    /* Undefined */
+                unsigned long   last_payload_address:41;        /* RW */
+        } s4;
+};
+
+/* ========================================================================= */
+/*                     UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                      */
+/* ========================================================================= */
+#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                0xa4118UL
+
+#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0
+#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL
+
+union uv4h_lb_proc_intd_soft_ack_clear_u {
+        unsigned long   v;
+        struct uv4h_lb_proc_intd_soft_ack_clear_s {
+                unsigned long   soft_ack_pending_flags:8;       /* WP */
+        } s4;
+};
+
+/* ========================================================================= */
+/*                    UV4H_LB_PROC_INTD_SOFT_ACK_PENDING                     */
+/* ========================================================================= */
+#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING              0xa4110UL
+
+#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0
+#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL
+
+union uv4h_lb_proc_intd_soft_ack_pending_u {
+        unsigned long   v;
+        struct uv4h_lb_proc_intd_soft_ack_pending_s {
+                unsigned long   soft_ack_flags:8;               /* RW */
+        } s4;
+};
+
 
 #endif /* _ASM_X86_UV_UV_MMRS_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index d7ce96a7daca..29003154fafd 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -48,12 +48,35 @@ static u64 gru_start_paddr, gru_end_paddr;
 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
 static u64 gru_dist_lmask, gru_dist_umask;
 static union uvh_apicid uvh_apicid;
+
+/* info derived from CPUID */
+static struct {
+        unsigned int apicid_shift;
+        unsigned int apicid_mask;
+        unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
+        unsigned int pnode_mask;
+        unsigned int gpa_shift;
+} uv_cpuid;
+
 int uv_min_hub_revision_id;
 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
 unsigned int uv_apicid_hibits;
 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
 
 static struct apic apic_x2apic_uv_x;
+static struct uv_hub_info_s uv_hub_info_node0;
+
+/* Set this to use hardware error handler instead of kernel panic */
+static int disable_uv_undefined_panic = 1;
+unsigned long uv_undefined(char *str)
+{
+        if (likely(!disable_uv_undefined_panic))
+                panic("UV: error: undefined MMR: %s\n", str);
+        else
+                pr_crit("UV: error: undefined MMR: %s\n", str);
+        return ~0ul;    /* cause a machine fault  */
+}
+EXPORT_SYMBOL(uv_undefined);
 
 static unsigned long __init uv_early_read_mmr(unsigned long addr)
 {
@@ -108,21 +131,71 @@ static int __init early_get_pnodeid(void)
         case UV3_HUB_PART_NUMBER_X:
                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
                 break;
+        case UV4_HUB_PART_NUMBER:
+                uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
+                break;
         }
 
         uv_hub_info->hub_revision = uv_min_hub_revision_id;
-        pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
+        uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
+        pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
+        uv_cpuid.gpa_shift = 46;        /* default unless changed */
+
+        pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
+                node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
+                m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
         return pnode;
 }
 
-static void __init early_get_apic_pnode_shift(void)
+/* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
+#define SMT_LEVEL       0       /* leaf 0xb SMT level */
+#define INVALID_TYPE    0       /* leaf 0xb sub-leaf types */
+#define SMT_TYPE        1
+#define CORE_TYPE       2
+#define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
+#define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
+
+static void set_x2apic_bits(void)
+{
+        unsigned int eax, ebx, ecx, edx, sub_index;
+        unsigned int sid_shift;
+
+        cpuid(0, &eax, &ebx, &ecx, &edx);
+        if (eax < 0xb) {
+                pr_info("UV: CPU does not have CPUID.11\n");
+                return;
+        }
+        cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
+        if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
+                pr_info("UV: CPUID.11 not implemented\n");
+                return;
+        }
+        sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
+        sub_index = 1;
+        do {
+                cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
+                if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
+                        sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
+                        break;
+                }
+                sub_index++;
+        } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
+        uv_cpuid.apicid_shift = 0;
+        uv_cpuid.apicid_mask = (~(-1 << sid_shift));
+        uv_cpuid.socketid_shift = sid_shift;
+}
+
+static void __init early_get_apic_socketid_shift(void)
 {
-        uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
-        if (!uvh_apicid.v)
-                /*
-                 * Old bios, use default value
-                 */
-                uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
+        if (is_uv2_hub() || is_uv3_hub())
+                uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
+
+        set_x2apic_bits();
+
+        pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
+                uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
+        pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
+                uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 }
 
 /*
@@ -150,13 +223,18 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         if (strncmp(oem_id, "SGI", 3) != 0)
                 return 0;
 
+        /* Setup early hub type field in uv_hub_info for Node 0 */
+        uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
+
         /*
          * Determine UV arch type.
          *   SGI: UV100/1000
          *   SGI2: UV2000/3000
          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
+         *   SGI4: UV400 (truncated to 4 chars because of different varieties)
          */
         uv_hub_info->hub_revision =
+                !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
@@ -165,7 +243,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
                 goto badbios;
 
         pnodeid = early_get_pnodeid();
-        early_get_apic_pnode_shift();
+        early_get_apic_socketid_shift();
         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
         x86_platform.nmi_init = uv_nmi_init;
 
@@ -211,17 +289,11 @@ int is_uv_system(void)
 }
 EXPORT_SYMBOL_GPL(is_uv_system);
 
-DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
-EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
-
-struct uv_blade_info *uv_blade_info;
-EXPORT_SYMBOL_GPL(uv_blade_info);
-
-short *uv_node_to_blade;
-EXPORT_SYMBOL_GPL(uv_node_to_blade);
+void **__uv_hub_info_list;
+EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 
-short *uv_cpu_to_blade;
-EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
+DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
+EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 
 short uv_possible_blades;
 EXPORT_SYMBOL_GPL(uv_possible_blades);
@@ -229,6 +301,115 @@ EXPORT_SYMBOL_GPL(uv_possible_blades);
 unsigned long sn_rtc_cycles_per_second;
 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 
+/* the following values are used for the per node hub info struct */
+static __initdata unsigned short *_node_to_pnode;
+static __initdata unsigned short _min_socket, _max_socket;
+static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
+static __initdata struct uv_gam_range_entry *uv_gre_table;
+static __initdata struct uv_gam_parameters *uv_gp_table;
+static __initdata unsigned short *_socket_to_node;
+static __initdata unsigned short *_socket_to_pnode;
+static __initdata unsigned short *_pnode_to_socket;
+static __initdata struct uv_gam_range_s *_gr_table;
+#define SOCK_EMPTY      ((unsigned short)~0)
+
+extern int uv_hub_info_version(void)
+{
+        return UV_HUB_INFO_VERSION;
+}
+EXPORT_SYMBOL(uv_hub_info_version);
+
+/* Build GAM range lookup table */
+static __init void build_uv_gr_table(void)
+{
+        struct uv_gam_range_entry *gre = uv_gre_table;
+        struct uv_gam_range_s *grt;
+        unsigned long last_limit = 0, ram_limit = 0;
+        int bytes, i, sid, lsid = -1;
+
+        if (!gre)
+                return;
+
+        bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
+        grt = kzalloc(bytes, GFP_KERNEL);
+        BUG_ON(!grt);
+        _gr_table = grt;
+
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
+                        if (!ram_limit) {   /* mark hole between ram/non-ram */
+                                ram_limit = last_limit;
+                                last_limit = gre->limit;
+                                lsid++;
+                                continue;
+                        }
+                        last_limit = gre->limit;
+                        pr_info("UV: extra hole in GAM RE table @%d\n",
+                                (int)(gre - uv_gre_table));
+                        continue;
+                }
+                if (_max_socket < gre->sockid) {
+                        pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
+                                gre->sockid, _max_socket,
+                                (int)(gre - uv_gre_table));
+                        continue;
+                }
+                sid = gre->sockid - _min_socket;
+                if (lsid < sid) {               /* new range */
+                        grt = &_gr_table[sid];
+                        grt->base = lsid;
+                        grt->nasid = gre->nasid;
+                        grt->limit = last_limit = gre->limit;
+                        lsid = sid;
+                        continue;
+                }
+                if (lsid == sid && !ram_limit) {        /* update range */
+                        if (grt->limit == last_limit) { /* .. if contiguous */
+                                grt->limit = last_limit = gre->limit;
+                                continue;
+                        }
+                }
+                if (!ram_limit) {               /* non-contiguous ram range */
+                        grt++;
+                        grt->base = sid - 1;
+                        grt->nasid = gre->nasid;
+                        grt->limit = last_limit = gre->limit;
+                        continue;
+                }
+                grt++;                          /* non-contiguous/non-ram */
+                grt->base = grt - _gr_table;    /* base is this entry */
+                grt->nasid = gre->nasid;
+                grt->limit = last_limit = gre->limit;
+                lsid++;
+        }
+
+        /* shorten table if possible */
+        grt++;
+        i = grt - _gr_table;
+        if (i < _gr_table_len) {
+                void *ret;
+
+                bytes = i * sizeof(struct uv_gam_range_s);
+                ret = krealloc(_gr_table, bytes, GFP_KERNEL);
+                if (ret) {
+                        _gr_table = ret;
+                        _gr_table_len = i;
+                }
+        }
+
+        /* display resultant gam range table */
+        for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
+                int gb = grt->base;
+                unsigned long start = gb < 0 ?  0 :
+                        (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
+                unsigned long end =
+                        (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
+
+                pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
+                        i, grt->nasid, start, end, gb);
+        }
+}
+
 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 {
         unsigned long val;
@@ -355,7 +536,6 @@ static unsigned long set_apic_id(unsigned int id)
 
 static unsigned int uv_read_apic_id(void)
 {
-
         return x2apic_get_apic_id(apic_read(APIC_ID));
 }
 
@@ -430,58 +610,38 @@ static void set_x2apic_extra_bits(int pnode)
         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 }
 
-/*
- * Called on boot cpu.
- */
-static __init int boot_pnode_to_blade(int pnode)
-{
-        int blade;
-
-        for (blade = 0; blade < uv_num_possible_blades(); blade++)
-                if (pnode == uv_blade_info[blade].pnode)
-                        return blade;
-        BUG();
-}
-
-struct redir_addr {
-        unsigned long redirect;
-        unsigned long alias;
-};
-
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
-static __initdata struct redir_addr redir_addrs[] = {
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
-};
-
-static unsigned char get_n_lshift(int m_val)
-{
-        union uv3h_gr0_gam_gr_config_u m_gr_config;
-
-        if (is_uv1_hub())
-                return m_val;
-
-        if (is_uv2_hub())
-                return m_val == 40 ? 40 : 39;
-
-        m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
-        return m_gr_config.s3.m_skt;
-}
-
 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 {
         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
+        unsigned long m_redirect;
+        unsigned long m_overlay;
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
-                alias.v = uv_read_local_mmr(redir_addrs[i].alias);
+        for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
+                switch (i) {
+                case 0:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
+                        break;
+                case 1:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
+                        break;
+                case 2:
+                        m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
+                        m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
+                        break;
+                }
+                alias.v = uv_read_local_mmr(m_overlay);
                 if (alias.s.enable && alias.s.base == 0) {
                         *size = (1UL << alias.s.m_alias);
-                        redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
-                        *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
+                        redirect.v = uv_read_local_mmr(m_redirect);
+                        *base = (unsigned long)redirect.s.dest_base
+                                                        << DEST_SHIFT;
                         return;
                 }
         }
@@ -544,6 +704,8 @@ static __init void map_gru_high(int max_pnode)
 {
         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
+        unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
+        unsigned long base;
 
         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
         if (!gru.s.enable) {
@@ -555,8 +717,9 @@ static __init void map_gru_high(int max_pnode)
                 map_gru_distributed(gru.v);
                 return;
         }
-        map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
-        gru_start_paddr = ((u64)gru.s.base << shift);
+        base = (gru.v & mask) >> shift;
+        map_high("GRU", base, shift, shift, max_pnode, map_wb);
+        gru_start_paddr = ((u64)base << shift);
         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 }
 
@@ -595,6 +758,7 @@ static __initdata struct mmioh_config mmiohs[] = {
         },
 };
 
+/* UV3 & UV4 have identical MMIOH overlay configs */
 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 {
         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
@@ -674,7 +838,7 @@ static __init void map_mmioh_high(int min_pnode, int max_pnode)
         unsigned long mmr, base;
         int shift, enable, m_io, n_io;
 
-        if (is_uv3_hub()) {
+        if (is_uv3_hub() || is_uv4_hub()) {
                 /* Map both MMIOH Regions */
                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
@@ -739,8 +903,8 @@ static __init void uv_rtc_init(void)
  */
 static void uv_heartbeat(unsigned long ignored)
 {
-        struct timer_list *timer = &uv_hub_info->scir.timer;
-        unsigned char bits = uv_hub_info->scir.state;
+        struct timer_list *timer = &uv_scir_info->timer;
+        unsigned char bits = uv_scir_info->state;
 
         /* flip heartbeat bit */
         bits ^= SCIR_CPU_HEARTBEAT;
@@ -760,14 +924,14 @@ static void uv_heartbeat(unsigned long ignored)
 
 static void uv_heartbeat_enable(int cpu)
 {
-        while (!uv_cpu_hub_info(cpu)->scir.enabled) {
-                struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
+        while (!uv_cpu_scir_info(cpu)->enabled) {
+                struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 
                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
                 setup_timer(timer, uv_heartbeat, cpu);
                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
                 add_timer_on(timer, cpu);
-                uv_cpu_hub_info(cpu)->scir.enabled = 1;
+                uv_cpu_scir_info(cpu)->enabled = 1;
 
                 /* also ensure that boot cpu is enabled */
                 cpu = 0;
@@ -777,9 +941,9 @@ static void uv_heartbeat_enable(int cpu)
 #ifdef CONFIG_HOTPLUG_CPU
 static void uv_heartbeat_disable(int cpu)
 {
-        if (uv_cpu_hub_info(cpu)->scir.enabled) {
-                uv_cpu_hub_info(cpu)->scir.enabled = 0;
-                del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
+        if (uv_cpu_scir_info(cpu)->enabled) {
+                uv_cpu_scir_info(cpu)->enabled = 0;
+                del_timer(&uv_cpu_scir_info(cpu)->timer);
         }
         uv_set_cpu_scir_bits(cpu, 0xff);
 }
@@ -862,155 +1026,475 @@ int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 void uv_cpu_init(void)
 {
         /* CPU 0 initialization will be done via uv_system_init. */
-        if (!uv_blade_info)
+        if (smp_processor_id() == 0)
                 return;
 
-        uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
+        uv_hub_info->nr_online_cpus++;
 
         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
                 set_x2apic_extra_bits(uv_hub_info->pnode);
 }
 
-void __init uv_system_init(void)
+struct mn {
+        unsigned char   m_val;
+        unsigned char   n_val;
+        unsigned char   m_shift;
+        unsigned char   n_lshift;
+};
+
+static void get_mn(struct mn *mnp)
 {
-        union uvh_rh_gam_config_mmr_u  m_n_config;
-        union uvh_node_id_u node_id;
-        unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
-        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
-        int gnode_extra, min_pnode = 999999, max_pnode = -1;
-        unsigned long mmr_base, present, paddr;
-        unsigned short pnode_mask;
-        unsigned char n_lshift;
-        char *hub = (is_uv1_hub() ? "UV100/1000" :
-                    (is_uv2_hub() ? "UV2000/3000" :
-                    (is_uv3_hub() ? "UV300" : NULL)));
+        union uvh_rh_gam_config_mmr_u m_n_config;
+        union uv3h_gr0_gam_gr_config_u m_gr_config;
 
-        if (!hub) {
-                pr_err("UV: Unknown/unsupported UV hub\n");
-                return;
+        m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
+        mnp->n_val = m_n_config.s.n_skt;
+        if (is_uv4_hub()) {
+                mnp->m_val = 0;
+                mnp->n_lshift = 0;
+        } else if (is_uv3_hub()) {
+                mnp->m_val = m_n_config.s3.m_skt;
+                m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
+                mnp->n_lshift = m_gr_config.s3.m_skt;
+        } else if (is_uv2_hub()) {
+                mnp->m_val = m_n_config.s2.m_skt;
+                mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
+        } else if (is_uv1_hub()) {
+                mnp->m_val = m_n_config.s1.m_skt;
+                mnp->n_lshift = mnp->m_val;
         }
-        pr_info("UV: Found %s hub\n", hub);
+        mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
+}
 
-        map_low_mmrs();
+void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
+{
+        struct mn mn = {0};     /* avoid unitialized warnings */
+        union uvh_node_id_u node_id;
 
-        m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
-        m_val = m_n_config.s.m_skt;
-        n_val = m_n_config.s.n_skt;
-        pnode_mask = (1 << n_val) - 1;
-        n_lshift = get_n_lshift(m_val);
-        mmr_base =
-            uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
-            ~UV_MMR_ENABLE;
+        get_mn(&mn);
+        hub_info->m_val = mn.m_val;
+        hub_info->n_val = mn.n_val;
+        hub_info->m_shift = mn.m_shift;
+        hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
+
+        hub_info->hub_revision = uv_hub_info->hub_revision;
+        hub_info->pnode_mask = uv_cpuid.pnode_mask;
+        hub_info->min_pnode = _min_pnode;
+        hub_info->min_socket = _min_socket;
+        hub_info->pnode_to_socket = _pnode_to_socket;
+        hub_info->socket_to_node = _socket_to_node;
+        hub_info->socket_to_pnode = _socket_to_pnode;
+        hub_info->gr_table_len = _gr_table_len;
+        hub_info->gr_table = _gr_table;
+        hub_info->gpa_mask = mn.m_val ?
+                (1UL << (mn.m_val + mn.n_val)) - 1 :
+                (1UL << uv_cpuid.gpa_shift) - 1;
 
         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
-        gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
-        gnode_upper = ((unsigned long)gnode_extra  << m_val);
-        pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
-                        n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
-                        n_lshift);
+        hub_info->gnode_extra =
+                (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
+
+        hub_info->gnode_upper =
+                ((unsigned long)hub_info->gnode_extra << mn.m_val);
+
+        if (uv_gp_table) {
+                hub_info->global_mmr_base = uv_gp_table->mmr_base;
+                hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
+                hub_info->global_gru_base = uv_gp_table->gru_base;
+                hub_info->global_gru_shift = uv_gp_table->gru_shift;
+                hub_info->gpa_shift = uv_gp_table->gpa_shift;
+                hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
+        } else {
+                hub_info->global_mmr_base =
+                        uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
+                                        ~UV_MMR_ENABLE;
+                hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
+        }
 
-        pr_info("UV: global MMR base 0x%lx\n", mmr_base);
+        get_lowmem_redirect(
+                &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
 
-        for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
-                uv_possible_blades +=
-                  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
+        hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
 
-        /* uv_num_possible_blades() is really the hub count */
-        pr_info("UV: Found %d blades, %d hubs\n",
-                        is_uv1_hub() ? uv_num_possible_blades() :
-                        (uv_num_possible_blades() + 1) / 2,
-                        uv_num_possible_blades());
+        /* show system specific info */
+        pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
+                hub_info->n_val, hub_info->m_val,
+                hub_info->m_shift, hub_info->n_lshift);
 
-        bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
-        uv_blade_info = kzalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_blade_info);
+        pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
+                hub_info->gpa_mask, hub_info->gpa_shift,
+                hub_info->pnode_mask, hub_info->apic_pnode_shift);
 
-        for (blade = 0; blade < uv_num_possible_blades(); blade++)
-                uv_blade_info[blade].memory_nid = -1;
+        pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
+                hub_info->global_mmr_base, hub_info->global_mmr_shift,
+                hub_info->global_gru_base, hub_info->global_gru_shift);
 
-        get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+        pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
+                hub_info->gnode_upper, hub_info->gnode_extra);
+}
+
+static void __init decode_gam_params(unsigned long ptr)
+{
+        uv_gp_table = (struct uv_gam_parameters *)ptr;
+
+        pr_info("UV: GAM Params...\n");
+        pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
+                uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
+                uv_gp_table->gru_base, uv_gp_table->gru_shift,
+                uv_gp_table->gpa_shift);
+}
+
+static void __init decode_gam_rng_tbl(unsigned long ptr)
+{
+        struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
+        unsigned long lgre = 0;
+        int index = 0;
+        int sock_min = 999999, pnode_min = 99999;
+        int sock_max = -1, pnode_max = -1;
+
+        uv_gre_table = gre;
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (!index) {
+                        pr_info("UV: GAM Range Table...\n");
+                        pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s %3s\n",
+                                "Range", "", "Size", "Type", "NASID",
+                                "SID", "PN", "PXM");
+                }
+                pr_info(
+                "UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x %3d\n",
+                        index++,
+                        (unsigned long)lgre << UV_GAM_RANGE_SHFT,
+                        (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
+                        ((unsigned long)(gre->limit - lgre)) >>
+                                (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
+                        gre->type, gre->nasid, gre->sockid,
+                        gre->pnode, gre->pxm);
+
+                lgre = gre->limit;
+                if (sock_min > gre->sockid)
+                        sock_min = gre->sockid;
+                if (sock_max < gre->sockid)
+                        sock_max = gre->sockid;
+                if (pnode_min > gre->pnode)
+                        pnode_min = gre->pnode;
+                if (pnode_max < gre->pnode)
+                        pnode_max = gre->pnode;
+        }
+        _min_socket = sock_min;
+        _max_socket = sock_max;
+        _min_pnode = pnode_min;
+        _max_pnode = pnode_max;
+        _gr_table_len = index;
+        pr_info(
+        "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
+                index, _min_socket, _max_socket, _min_pnode, _max_pnode);
+}
+
+static void __init decode_uv_systab(void)
+{
+        struct uv_systab *st;
+        int i;
+
+        st = uv_systab;
+        if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
+                return;
+        if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
+                pr_crit(
+                "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
+                        st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
+                BUG();
+        }
+
+        for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
+                unsigned long ptr = st->entry[i].offset;
 
-        bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
-        uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_node_to_blade);
-        memset(uv_node_to_blade, 255, bytes);
+                if (!ptr)
+                        continue;
+
+                ptr = ptr + (unsigned long)st;
+
+                switch (st->entry[i].type) {
+                case UV_SYSTAB_TYPE_GAM_PARAMS:
+                        decode_gam_params(ptr);
+                        break;
+
+                case UV_SYSTAB_TYPE_GAM_RNG_TBL:
+                        decode_gam_rng_tbl(ptr);
+                        break;
+                }
+        }
+}
 
-        bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
-        uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
-        BUG_ON(!uv_cpu_to_blade);
-        memset(uv_cpu_to_blade, 255, bytes);
+/*
+ * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
+ * .. NB: UVH_NODE_PRESENT_TABLE is going away,
+ * .. being replaced by GAM Range Table
+ */
+static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
+{
+        int i, uv_pb = 0;
 
-        blade = 0;
+        pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
-                present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
-                for (j = 0; j < 64; j++) {
-                        if (!test_bit(j, &present))
-                                continue;
-                        pnode = (i * 64 + j) & pnode_mask;
-                        uv_blade_info[blade].pnode = pnode;
-                        uv_blade_info[blade].nr_possible_cpus = 0;
-                        uv_blade_info[blade].nr_online_cpus = 0;
-                        spin_lock_init(&uv_blade_info[blade].nmi_lock);
-                        min_pnode = min(pnode, min_pnode);
-                        max_pnode = max(pnode, max_pnode);
-                        blade++;
+                unsigned long np;
+
+                np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
+                if (np)
+                        pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
+
+                uv_pb += hweight64(np);
+        }
+        if (uv_possible_blades != uv_pb)
+                uv_possible_blades = uv_pb;
+}
+
+static void __init build_socket_tables(void)
+{
+        struct uv_gam_range_entry *gre = uv_gre_table;
+        int num, nump;
+        int cpu, i, lnid;
+        int minsock = _min_socket;
+        int maxsock = _max_socket;
+        int minpnode = _min_pnode;
+        int maxpnode = _max_pnode;
+        size_t bytes;
+
+        if (!gre) {
+                if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
+                        pr_info("UV: No UVsystab socket table, ignoring\n");
+                        return;         /* not required */
                 }
+                pr_crit(
+                "UV: Error: UVsystab address translations not available!\n");
+                BUG();
+        }
+
+        /* build socket id -> node id, pnode */
+        num = maxsock - minsock + 1;
+        bytes = num * sizeof(_socket_to_node[0]);
+        _socket_to_node = kmalloc(bytes, GFP_KERNEL);
+        _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
+
+        nump = maxpnode - minpnode + 1;
+        bytes = nump * sizeof(_pnode_to_socket[0]);
+        _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
+
+        for (i = 0; i < num; i++)
+                _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
+
+        for (i = 0; i < nump; i++)
+                _pnode_to_socket[i] = SOCK_EMPTY;
+
+        /* fill in pnode/node/addr conversion list values */
+        pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n");
+        for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
+                        continue;
+                i = gre->sockid - minsock;
+                if (_socket_to_pnode[i] != SOCK_EMPTY)
+                        continue;       /* duplicate */
+                _socket_to_pnode[i] = gre->pnode;
+                _socket_to_node[i] = gre->pxm;
+
+                i = gre->pnode - minpnode;
+                _pnode_to_socket[i] = gre->sockid;
+
+                pr_info(
+                "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n",
+                        gre->sockid, gre->type, gre->nasid,
+                        _socket_to_pnode[gre->sockid - minsock],
+                        _socket_to_node[gre->sockid - minsock],
+                        _pnode_to_socket[gre->pnode - minpnode]);
         }
 
-        uv_bios_init();
+        /* check socket -> node values */
+        lnid = -1;
+        for_each_present_cpu(cpu) {
+                int nid = cpu_to_node(cpu);
+                int apicid, sockid;
+
+                if (lnid == nid)
+                        continue;
+                lnid = nid;
+                apicid = per_cpu(x86_cpu_to_apicid, cpu);
+                sockid = apicid >> uv_cpuid.socketid_shift;
+                i = sockid - minsock;
+
+                if (nid != _socket_to_node[i]) {
+                        pr_warn(
+                        "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n",
+                                i, sockid, gre->type, _socket_to_node[i], nid);
+                        _socket_to_node[i] = nid;
+                }
+        }
+
+        /* Setup physical blade to pnode translation from GAM Range Table */
+        bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
+        _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
+        BUG_ON(!_node_to_pnode);
+
+        for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
+                unsigned short sockid;
+
+                for (sockid = minsock; sockid <= maxsock; sockid++) {
+                        if (lnid == _socket_to_node[sockid - minsock]) {
+                                _node_to_pnode[lnid] =
+                                        _socket_to_pnode[sockid - minsock];
+                                break;
+                        }
+                }
+                if (sockid > maxsock) {
+                        pr_err("UV: socket for node %d not found!\n", lnid);
+                        BUG();
+                }
+        }
+
+        /*
+         * If socket id == pnode or socket id == node for all nodes,
+         *   system runs faster by removing corresponding conversion table.
+         */
+        pr_info("UV: Checking socket->node/pnode for identity maps\n");
+        if (minsock == 0) {
+                for (i = 0; i < num; i++)
+                        if (_socket_to_node[i] == SOCK_EMPTY ||
+                                i != _socket_to_node[i])
+                                break;
+                if (i >= num) {
+                        kfree(_socket_to_node);
+                        _socket_to_node = NULL;
+                        pr_info("UV: 1:1 socket_to_node table removed\n");
+                }
+        }
+        if (minsock == minpnode) {
+                for (i = 0; i < num; i++)
+                        if (_socket_to_pnode[i] != SOCK_EMPTY &&
+                                _socket_to_pnode[i] != i + minpnode)
+                                break;
+                if (i >= num) {
+                        kfree(_socket_to_pnode);
+                        _socket_to_pnode = NULL;
+                        pr_info("UV: 1:1 socket_to_pnode table removed\n");
+                }
+        }
+}
+
+void __init uv_system_init(void)
+{
+        struct uv_hub_info_s hub_info = {0};
+        int bytes, cpu, nodeid;
+        unsigned short min_pnode = 9999, max_pnode = 0;
+        char *hub = is_uv4_hub() ? "UV400" :
+                    is_uv3_hub() ? "UV300" :
+                    is_uv2_hub() ? "UV2000/3000" :
+                    is_uv1_hub() ? "UV100/1000" : NULL;
+
+        if (!hub) {
+                pr_err("UV: Unknown/unsupported UV hub\n");
+                return;
+        }
+        pr_info("UV: Found %s hub\n", hub);
+
+        map_low_mmrs();
+
+        uv_bios_init();                 /* get uv_systab for decoding */
+        decode_uv_systab();
+        build_socket_tables();
+        build_uv_gr_table();
+        uv_init_hub_info(&hub_info);
+        uv_possible_blades = num_possible_nodes();
+        if (!_node_to_pnode)
+                boot_init_possible_blades(&hub_info);
+
+        /* uv_num_possible_blades() is really the hub count */
+        pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
+                        uv_num_possible_blades(),
+                        num_possible_nodes(),
+                        num_possible_cpus());
+
         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
                             &sn_region_size, &system_serial_number);
+        hub_info.coherency_domain_number = sn_coherency_id;
         uv_rtc_init();
 
-        for_each_present_cpu(cpu) {
-                int apicid = per_cpu(x86_cpu_to_apicid, cpu);
+        bytes = sizeof(void *) * uv_num_possible_blades();
+        __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
+        BUG_ON(!__uv_hub_info_list);
 
-                nid = cpu_to_node(cpu);
-                /*
-                 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
-                 */
-                uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
-                uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
-                uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
+        bytes = sizeof(struct uv_hub_info_s);
+        for_each_node(nodeid) {
+                struct uv_hub_info_s *new_hub;
 
-                uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
-                uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
+                if (__uv_hub_info_list[nodeid]) {
+                        pr_err("UV: Node %d UV HUB already initialized!?\n",
+                                nodeid);
+                        BUG();
+                }
+
+                /* Allocate new per hub info list */
+                new_hub = (nodeid == 0) ?
+                        &uv_hub_info_node0 :
+                        kzalloc_node(bytes, GFP_KERNEL, nodeid);
+                BUG_ON(!new_hub);
+                __uv_hub_info_list[nodeid] = new_hub;
+                new_hub = uv_hub_info_list(nodeid);
+                BUG_ON(!new_hub);
+                *new_hub = hub_info;
+
+                /* Use information from GAM table if available */
+                if (_node_to_pnode)
+                        new_hub->pnode = _node_to_pnode[nodeid];
+                else    /* Fill in during cpu loop */
+                        new_hub->pnode = 0xffff;
+                new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
+                new_hub->memory_nid = -1;
+                new_hub->nr_possible_cpus = 0;
+                new_hub->nr_online_cpus = 0;
+        }
 
+        /* Initialize per cpu info */
+        for_each_possible_cpu(cpu) {
+                int apicid = per_cpu(x86_cpu_to_apicid, cpu);
+                int numa_node_id;
+                unsigned short pnode;
+
+                nodeid = cpu_to_node(cpu);
+                numa_node_id = numa_cpu_node(cpu);
                 pnode = uv_apicid_to_pnode(apicid);
-                blade = boot_pnode_to_blade(pnode);
-                lcpu = uv_blade_info[blade].nr_possible_cpus;
-                uv_blade_info[blade].nr_possible_cpus++;
-
-                /* Any node on the blade, else will contain -1. */
-                uv_blade_info[blade].memory_nid = nid;
-
-                uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
-                uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
-                uv_cpu_hub_info(cpu)->m_val = m_val;
-                uv_cpu_hub_info(cpu)->n_val = n_val;
-                uv_cpu_hub_info(cpu)->numa_blade_id = blade;
-                uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
-                uv_cpu_hub_info(cpu)->pnode = pnode;
-                uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
-                uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
-                uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
-                uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
-                uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
-                uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
-                uv_node_to_blade[nid] = blade;
-                uv_cpu_to_blade[cpu] = blade;
+
+                uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
+                uv_cpu_info_per(cpu)->blade_cpu_id =
+                        uv_cpu_hub_info(cpu)->nr_possible_cpus++;
+                if (uv_cpu_hub_info(cpu)->memory_nid == -1)
+                        uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
+                if (nodeid != numa_node_id &&   /* init memoryless node */
+                    uv_hub_info_list(numa_node_id)->pnode == 0xffff)
+                        uv_hub_info_list(numa_node_id)->pnode = pnode;
+                else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
+                        uv_cpu_hub_info(cpu)->pnode = pnode;
+                uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
         }
 
-        /* Add blade/pnode info for nodes without cpus */
-        for_each_online_node(nid) {
-                if (uv_node_to_blade[nid] >= 0)
-                        continue;
-                paddr = node_start_pfn(nid) << PAGE_SHIFT;
-                pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
-                blade = boot_pnode_to_blade(pnode);
-                uv_node_to_blade[nid] = blade;
+        for_each_node(nodeid) {
+                unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
+
+                /* Add pnode info for pre-GAM list nodes without cpus */
+                if (pnode == 0xffff) {
+                        unsigned long paddr;
+
+                        paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
+                        pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
+                        uv_hub_info_list(nodeid)->pnode = pnode;
+                }
+                min_pnode = min(pnode, min_pnode);
+                max_pnode = max(pnode, max_pnode);
+                pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
+                        nodeid,
+                        uv_hub_info_list(nodeid)->pnode,
+                        uv_hub_info_list(nodeid)->nr_possible_cpus);
         }
 
+        pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
         map_gru_high(max_pnode);
         map_mmr_high(max_pnode);
         map_mmioh_high(min_pnode, max_pnode);
diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c
index 1584cbed0dce..815fec6e05e2 100644
--- a/arch/x86/platform/uv/bios_uv.c
+++ b/arch/x86/platform/uv/bios_uv.c
@@ -21,19 +21,20 @@
 
 #include <linux/efi.h>
 #include <linux/export.h>
+#include <linux/slab.h>
 #include <asm/efi.h>
 #include <linux/io.h>
 #include <asm/uv/bios.h>
 #include <asm/uv/uv_hub.h>
 
-static struct uv_systab uv_systab;
+struct uv_systab *uv_systab;
 
 s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
 {
-        struct uv_systab *tab = &uv_systab;
+        struct uv_systab *tab = uv_systab;
         s64 ret;
 
-        if (!tab->function)
+        if (!tab || !tab->function)
                 /*
                  * BIOS does not support UV systab
                  */
@@ -183,34 +184,31 @@ int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus)
 }
 EXPORT_SYMBOL_GPL(uv_bios_set_legacy_vga_target);
 
-
 #ifdef CONFIG_EFI
 void uv_bios_init(void)
 {
-        struct uv_systab *tab;
-
-        if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) ||
-            (efi.uv_systab == (unsigned long)NULL)) {
-                printk(KERN_CRIT "No EFI UV System Table.\n");
-                uv_systab.function = (unsigned long)NULL;
+        uv_systab = NULL;
+        if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) || !efi.uv_systab) {
+                pr_crit("UV: UVsystab: missing\n");
                 return;
         }
 
-        tab = (struct uv_systab *)ioremap(efi.uv_systab,
-                                        sizeof(struct uv_systab));
-        if (strncmp(tab->signature, "UVST", 4) != 0)
-                printk(KERN_ERR "bad signature in UV system table!");
-
-        /*
-         * Copy table to permanent spot for later use.
-         */
-        memcpy(&uv_systab, tab, sizeof(struct uv_systab));
-        iounmap(tab);
+        uv_systab = ioremap(efi.uv_systab, sizeof(struct uv_systab));
+        if (!uv_systab || strncmp(uv_systab->signature, UV_SYSTAB_SIG, 4)) {
+                pr_err("UV: UVsystab: bad signature!\n");
+                iounmap(uv_systab);
+                return;
+        }
 
-        printk(KERN_INFO "EFI UV System Table Revision %d\n",
-                                        uv_systab.revision);
+        if (uv_systab->revision >= UV_SYSTAB_VERSION_UV4) {
+                iounmap(uv_systab);
+                uv_systab = ioremap(efi.uv_systab, uv_systab->size);
+                if (!uv_systab) {
+                        pr_err("UV: UVsystab: ioremap(%d) failed!\n",
+                                uv_systab->size);
+                        return;
+                }
+        }
+        pr_info("UV: UVsystab: Revision:%x\n", uv_systab->revision);
 }
-#else   /* !CONFIG_EFI */
-
-void uv_bios_init(void) { }
 #endif
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 3b6ec42718e4..fdb4d42b4ce5 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -37,7 +37,7 @@ static int timeout_base_ns[] = {
 };
 
 static int timeout_us;
-static int nobau;
+static bool nobau = true;
 static int nobau_perm;
 static cycles_t congested_cycles;
 
@@ -106,13 +106,28 @@ static char *stat_description[] = {
         "enable:   number times use of the BAU was re-enabled"
 };
 
-static int __init
-setup_nobau(char *arg)
+static int __init setup_bau(char *arg)
 {
-        nobau = 1;
+        int result;
+
+        if (!arg)
+                return -EINVAL;
+
+        result = strtobool(arg, &nobau);
+        if (result)
+                return result;
+
+        /* we need to flip the logic here, so that bau=y sets nobau to false */
+        nobau = !nobau;
+
+        if (!nobau)
+                pr_info("UV BAU Enabled\n");
+        else
+                pr_info("UV BAU Disabled\n");
+
         return 0;
 }
-early_param("nobau", setup_nobau);
+early_param("bau", setup_bau);
 
 /* base pnode in this partition */
 static int uv_base_pnode __read_mostly;
@@ -131,10 +146,10 @@ set_bau_on(void)
                 pr_info("BAU not initialized; cannot be turned on\n");
                 return;
         }
-        nobau = 0;
+        nobau = false;
         for_each_present_cpu(cpu) {
                 bcp = &per_cpu(bau_control, cpu);
-                bcp->nobau = 0;
+                bcp->nobau = false;
         }
         pr_info("BAU turned on\n");
         return;
@@ -146,10 +161,10 @@ set_bau_off(void)
         int cpu;
         struct bau_control *bcp;
 
-        nobau = 1;
+        nobau = true;
         for_each_present_cpu(cpu) {
                 bcp = &per_cpu(bau_control, cpu);
-                bcp->nobau = 1;
+                bcp->nobau = true;
         }
         pr_info("BAU turned off\n");
         return;
@@ -1886,7 +1901,7 @@ static void __init init_per_cpu_tunables(void)
                 bcp = &per_cpu(bau_control, cpu);
                 bcp->baudisabled                = 0;
                 if (nobau)
-                        bcp->nobau              = 1;
+                        bcp->nobau              = true;
                 bcp->statp                      = &per_cpu(ptcstats, cpu);
                 /* time interval to catch a hardware stay-busy bug */
                 bcp->timeout_interval           = usec_2_cycles(2*timeout_us);
@@ -2025,7 +2040,8 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
                         return 1;
                 }
                 bcp->uvhub_master = *hmasterp;
-                bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
+                bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu);
+
                 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
                         printk(KERN_EMERG "%d cpus per uvhub invalid\n",
                                 bcp->uvhub_cpu);
diff --git a/arch/x86/platform/uv/uv_sysfs.c b/arch/x86/platform/uv/uv_sysfs.c
index 5d4ba301e776..e9da9ebd924a 100644
--- a/arch/x86/platform/uv/uv_sysfs.c
+++ b/arch/x86/platform/uv/uv_sysfs.c
@@ -34,7 +34,7 @@ static ssize_t partition_id_show(struct kobject *kobj,
 static ssize_t coherence_id_show(struct kobject *kobj,
                         struct kobj_attribute *attr, char *buf)
 {
-        return snprintf(buf, PAGE_SIZE, "%ld\n", partition_coherence_id());
+        return snprintf(buf, PAGE_SIZE, "%ld\n", uv_partition_coherence_id());
 }
 
 static struct kobj_attribute partition_id_attr =
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 2b158a9fa1d7..b333fc45f9ec 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -165,7 +165,7 @@ static __init int uv_rtc_allocate_timers(void)
         for_each_present_cpu(cpu) {
                 int nid = cpu_to_node(cpu);
                 int bid = uv_cpu_to_blade_id(cpu);
-                int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
+                int bcpu = uv_cpu_blade_processor_id(cpu);
                 struct uv_rtc_timer_head *head = blade_info[bid];
 
                 if (!head) {
@@ -226,7 +226,7 @@ static int uv_rtc_set_timer(int cpu, u64 expires)
         int pnode = uv_cpu_to_pnode(cpu);
         int bid = uv_cpu_to_blade_id(cpu);
         struct uv_rtc_timer_head *head = blade_info[bid];
-        int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
+        int bcpu = uv_cpu_blade_processor_id(cpu);
         u64 *t = &head->cpu[bcpu].expires;
         unsigned long flags;
         int next_cpu;
@@ -262,7 +262,7 @@ static int uv_rtc_unset_timer(int cpu, int force)
         int pnode = uv_cpu_to_pnode(cpu);
         int bid = uv_cpu_to_blade_id(cpu);
         struct uv_rtc_timer_head *head = blade_info[bid];
-        int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
+        int bcpu = uv_cpu_blade_processor_id(cpu);
         u64 *t = &head->cpu[bcpu].expires;
         unsigned long flags;
         int rc = 0;