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authorDan Williams <dan.j.williams@intel.com>2017-05-30 01:40:44 -0400
committerDan Williams <dan.j.williams@intel.com>2017-06-15 17:35:24 -0400
commit4e4f00a9b51a1c52ebdd728a1caeb3b9fe48c39d (patch)
tree949f4063c4ec29fa77660d12390942976dce8d0f /arch/x86
parent81f558701ae8d5677635118751b1b4043094c7e9 (diff)
x86, dax, libnvdimm: remove wb_cache_pmem() indirection
With all handling of the CONFIG_ARCH_HAS_PMEM_API case being moved to libnvdimm and the pmem driver directly we do not need to provide global wrappers and fallbacks in the CONFIG_ARCH_HAS_PMEM_API=n case. The pmem driver will simply not link to arch_wb_cache_pmem() in that case. Same as before, pmem flushing is only defined for x86_64, via clean_cache_range(), but it is straightforward to add other archs in the future. arch_wb_cache_pmem() is an exported function since the pmem module needs to find it, but it is privately declared in drivers/nvdimm/pmem.h because there are no consumers outside of the pmem driver. Cc: <x86@kernel.org> Cc: Jan Kara <jack@suse.cz> Cc: Jeff Moyer <jmoyer@redhat.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Oliver O'Halloran <oohall@gmail.com> Cc: Matthew Wilcox <mawilcox@microsoft.com> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/include/asm/pmem.h21
-rw-r--r--arch/x86/lib/usercopy_64.c6
2 files changed, 6 insertions, 21 deletions
diff --git a/arch/x86/include/asm/pmem.h b/arch/x86/include/asm/pmem.h
index f4c119d253f3..4759a179aa52 100644
--- a/arch/x86/include/asm/pmem.h
+++ b/arch/x86/include/asm/pmem.h
@@ -44,27 +44,6 @@ static inline void arch_memcpy_to_pmem(void *dst, const void *src, size_t n)
44 BUG(); 44 BUG();
45} 45}
46 46
47/**
48 * arch_wb_cache_pmem - write back a cache range with CLWB
49 * @vaddr: virtual start address
50 * @size: number of bytes to write back
51 *
52 * Write back a cache range using the CLWB (cache line write back)
53 * instruction. Note that @size is internally rounded up to be cache
54 * line size aligned.
55 */
56static inline void arch_wb_cache_pmem(void *addr, size_t size)
57{
58 u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
59 unsigned long clflush_mask = x86_clflush_size - 1;
60 void *vend = addr + size;
61 void *p;
62
63 for (p = (void *)((unsigned long)addr & ~clflush_mask);
64 p < vend; p += x86_clflush_size)
65 clwb(p);
66}
67
68static inline void arch_invalidate_pmem(void *addr, size_t size) 47static inline void arch_invalidate_pmem(void *addr, size_t size)
69{ 48{
70 clflush_cache_range(addr, size); 49 clflush_cache_range(addr, size);
diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c
index f42d2fd86ca3..75d3776123cc 100644
--- a/arch/x86/lib/usercopy_64.c
+++ b/arch/x86/lib/usercopy_64.c
@@ -97,6 +97,12 @@ static void clean_cache_range(void *addr, size_t size)
97 clwb(p); 97 clwb(p);
98} 98}
99 99
100void arch_wb_cache_pmem(void *addr, size_t size)
101{
102 clean_cache_range(addr, size);
103}
104EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
105
100long __copy_user_flushcache(void *dst, const void __user *src, unsigned size) 106long __copy_user_flushcache(void *dst, const void __user *src, unsigned size)
101{ 107{
102 unsigned long flushed, dest = (unsigned long) dst; 108 unsigned long flushed, dest = (unsigned long) dst;