Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 mm updates from Ingo Molnar:

 - Extend the memmap= boot parameter syntax to allow the redeclaration
   and dropping of existing ranges, and to support all e820 range types
   (Jan H. Schönherr)

 - Improve the W+X boot time security checks to remove false positive
   warnings on Xen (Jan Beulich)

 - Support booting as Xen PVH guest (Juergen Gross)

 - Improved 5-level paging (LA57) support, in particular it's possible
   now to have a single kernel image for both 4-level and 5-level
   hardware (Kirill A. Shutemov)

 - AMD hardware RAM encryption support (SME/SEV) fixes (Tom Lendacky)

 - Preparatory commits for hardware-encrypted RAM support on Intel CPUs.
   (Kirill A. Shutemov)

 - Improved Intel-MID support (Andy Shevchenko)

 - Show EFI page tables in page_tables debug files (Andy Lutomirski)

 - ... plus misc fixes and smaller cleanups

* 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (56 commits)
  x86/cpu/tme: Fix spelling: "configuation" -> "configuration"
  x86/boot: Fix SEV boot failure from change to __PHYSICAL_MASK_SHIFT
  x86/mm: Update comment in detect_tme() regarding x86_phys_bits
  x86/mm/32: Remove unused node_memmap_size_bytes() & CONFIG_NEED_NODE_MEMMAP_SIZE logic
  x86/mm: Remove pointless checks in vmalloc_fault
  x86/platform/intel-mid: Add special handling for ACPI HW reduced platforms
  ACPI, x86/boot: Introduce the ->reduced_hw_early_init() ACPI callback
  ACPI, x86/boot: Split out acpi_generic_reduce_hw_init() and export
  x86/pconfig: Provide defines and helper to run MKTME_KEY_PROG leaf
  x86/pconfig: Detect PCONFIG targets
  x86/tme: Detect if TME and MKTME is activated by BIOS
  x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G
  x86/boot/compressed/64: Use page table in trampoline memory
  x86/boot/compressed/64: Use stack from trampoline memory
  x86/boot/compressed/64: Make sure we have a 32-bit code segment
  x86/mm: Do not use paravirtualized calls in native_set_p4d()
  kdump, vmcoreinfo: Export pgtable_l5_enabled value
  x86/boot/compressed/64: Prepare new top-level page table for trampoline
  x86/boot/compressed/64: Set up trampoline memory
  x86/boot/compressed/64: Save and restore trampoline memory
  ...

1 files changed, 19 insertions, 41 deletions

diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index f75ea0748b9f..73bd8c95ac71 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -417,11 +417,11 @@ void vmalloc_sync_all(void)
  */
 static noinline int vmalloc_fault(unsigned long address)
 {
-        pgd_t *pgd, *pgd_ref;
-        p4d_t *p4d, *p4d_ref;
-        pud_t *pud, *pud_ref;
-        pmd_t *pmd, *pmd_ref;
-        pte_t *pte, *pte_ref;
+        pgd_t *pgd, *pgd_k;
+        p4d_t *p4d, *p4d_k;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *pte;
 
         /* Make sure we are in vmalloc area: */
         if (!(address >= VMALLOC_START && address < VMALLOC_END))
@@ -435,73 +435,51 @@ static noinline int vmalloc_fault(unsigned long address)
          * case just flush:
          */
         pgd = (pgd_t *)__va(read_cr3_pa()) + pgd_index(address);
-        pgd_ref = pgd_offset_k(address);
-        if (pgd_none(*pgd_ref))
+        pgd_k = pgd_offset_k(address);
+        if (pgd_none(*pgd_k))
                 return -1;
 
-        if (CONFIG_PGTABLE_LEVELS > 4) {
+        if (pgtable_l5_enabled) {
                 if (pgd_none(*pgd)) {
-                        set_pgd(pgd, *pgd_ref);
+                        set_pgd(pgd, *pgd_k);
                         arch_flush_lazy_mmu_mode();
                 } else {
-                        BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
+                        BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_k));
                 }
         }
 
         /* With 4-level paging, copying happens on the p4d level. */
         p4d = p4d_offset(pgd, address);
-        p4d_ref = p4d_offset(pgd_ref, address);
-        if (p4d_none(*p4d_ref))
+        p4d_k = p4d_offset(pgd_k, address);
+        if (p4d_none(*p4d_k))
                 return -1;
 
-        if (p4d_none(*p4d) && CONFIG_PGTABLE_LEVELS == 4) {
-                set_p4d(p4d, *p4d_ref);
+        if (p4d_none(*p4d) && !pgtable_l5_enabled) {
+                set_p4d(p4d, *p4d_k);
                 arch_flush_lazy_mmu_mode();
         } else {
-                BUG_ON(p4d_pfn(*p4d) != p4d_pfn(*p4d_ref));
+                BUG_ON(p4d_pfn(*p4d) != p4d_pfn(*p4d_k));
         }
 
-        /*
-         * Below here mismatches are bugs because these lower tables
-         * are shared:
-         */
         BUILD_BUG_ON(CONFIG_PGTABLE_LEVELS < 4);
 
         pud = pud_offset(p4d, address);
-        pud_ref = pud_offset(p4d_ref, address);
-        if (pud_none(*pud_ref))
+        if (pud_none(*pud))
                 return -1;
 
-        if (pud_none(*pud) || pud_pfn(*pud) != pud_pfn(*pud_ref))
-                BUG();
-
         if (pud_large(*pud))
                 return 0;
 
         pmd = pmd_offset(pud, address);
-        pmd_ref = pmd_offset(pud_ref, address);
-        if (pmd_none(*pmd_ref))
+        if (pmd_none(*pmd))
                 return -1;
 
-        if (pmd_none(*pmd) || pmd_pfn(*pmd) != pmd_pfn(*pmd_ref))
-                BUG();
-
         if (pmd_large(*pmd))
                 return 0;
 
-        pte_ref = pte_offset_kernel(pmd_ref, address);
-        if (!pte_present(*pte_ref))
-                return -1;
-
         pte = pte_offset_kernel(pmd, address);
-
-        /*
-         * Don't use pte_page here, because the mappings can point
-         * outside mem_map, and the NUMA hash lookup cannot handle
-         * that:
-         */
-        if (!pte_present(*pte) || pte_pfn(*pte) != pte_pfn(*pte_ref))
-                BUG();
+        if (!pte_present(*pte))
+                return -1;
 
         return 0;
 }