Merge tag 'asoc-v3.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes for v3.18

As well as the usual driver fixes there's a few other things here:

One is a fix for a race in DPCM which is unfortuantely a rather large
diffstat, this is the result of growing usage of the mainline code and
hence more detailed testing so I'm relatively happy.

The other is a fix for non-DT machine driver matching following some of
the componentization work which is much more focused.

Both have had a while to cook in -next.

16 files changed, 72 insertions, 228 deletions

diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index b436fc735aa4..a142e77693e1 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -397,7 +397,7 @@ static int mp_register_gsi(struct device *dev, u32 gsi, int trigger,
 
         /* Don't set up the ACPI SCI because it's already set up */
         if (acpi_gbl_FADT.sci_interrupt == gsi)
-                return gsi;
+                return mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC);
 
         trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1;
         polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1;
@@ -604,14 +604,18 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
 
 int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
 {
-        int irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK);
+        int irq;
 
-        if (irq >= 0) {
+        if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
+                *irqp = gsi;
+        } else {
+                irq = mp_map_gsi_to_irq(gsi,
+                                        IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK);
+                if (irq < 0)
+                        return -1;
                 *irqp = irq;
-                return 0;
         }
-
-        return -1;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
 
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 5972b108f15a..b708738d016e 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -185,8 +185,6 @@ static void apbt_setup_irq(struct apbt_dev *adev)
 
         irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
         irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
-        /* APB timer irqs are set up as mp_irqs, timer is edge type */
-        __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
 }
 
 /* Should be called with per cpu */
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 00853b254ab0..ba6cc041edb1 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1297,7 +1297,7 @@ void setup_local_APIC(void)
         unsigned int value, queued;
         int i, j, acked = 0;
         unsigned long long tsc = 0, ntsc;
-        long long max_loops = cpu_khz;
+        long long max_loops = cpu_khz ? cpu_khz : 1000000;
 
         if (cpu_has_tsc)
                 rdtscll(tsc);
@@ -1383,7 +1383,7 @@ void setup_local_APIC(void)
                         break;
                 }
                 if (queued) {
-                        if (cpu_has_tsc) {
+                        if (cpu_has_tsc && cpu_khz) {
                                 rdtscll(ntsc);
                                 max_loops = (cpu_khz << 10) - (ntsc - tsc);
                         } else
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 01d5453b5502..e27b49d7c922 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -39,9 +39,12 @@ obj-$(CONFIG_CPU_SUP_AMD)		+= perf_event_amd_iommu.o
 endif
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_knc.o perf_event_p4.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
-obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore.o perf_event_intel_uncore_snb.o
-obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore_snbep.o perf_event_intel_uncore_nhmex.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_rapl.o
+
+obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE)  += perf_event_intel_uncore.o \
+                                           perf_event_intel_uncore_snb.o \
+                                           perf_event_intel_uncore_snbep.o \
+                                           perf_event_intel_uncore_nhmex.o
 endif
 
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1ef456273172..9cc6b6f25f42 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -213,12 +213,13 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_X86_F00F_BUG
         /*
-         * All current models of Pentium and Pentium with MMX technology CPUs
+         * All models of Pentium and Pentium with MMX technology CPUs
          * have the F0 0F bug, which lets nonprivileged users lock up the
          * system. Announce that the fault handler will be checking for it.
+         * The Quark is also family 5, but does not have the same bug.
          */
         clear_cpu_bug(c, X86_BUG_F00F);
-        if (!paravirt_enabled() && c->x86 == 5) {
+        if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) {
                 static int f00f_workaround_enabled;
 
                 set_cpu_bug(c, X86_BUG_F00F);
diff --git a/arch/x86/kernel/cpu/microcode/amd_early.c b/arch/x86/kernel/cpu/microcode/amd_early.c
index 7aa1acc79789..06674473b0e6 100644
--- a/arch/x86/kernel/cpu/microcode/amd_early.c
+++ b/arch/x86/kernel/cpu/microcode/amd_early.c
@@ -108,12 +108,13 @@ static size_t compute_container_size(u8 *data, u32 total_size)
  * load_microcode_amd() to save equivalent cpu table and microcode patches in
  * kernel heap memory.
  */
-static void apply_ucode_in_initrd(void *ucode, size_t size)
+static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
 {
         struct equiv_cpu_entry *eq;
         size_t *cont_sz;
         u32 *header;
         u8  *data, **cont;
+        u8 (*patch)[PATCH_MAX_SIZE];
         u16 eq_id = 0;
         int offset, left;
         u32 rev, eax, ebx, ecx, edx;
@@ -123,10 +124,12 @@ static void apply_ucode_in_initrd(void *ucode, size_t size)
         new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
         cont_sz = (size_t *)__pa_nodebug(&container_size);
         cont    = (u8 **)__pa_nodebug(&container);
+        patch   = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
 #else
         new_rev = &ucode_new_rev;
         cont_sz = &container_size;
         cont    = &container;
+        patch   = &amd_ucode_patch;
 #endif
 
         data   = ucode;
@@ -213,9 +216,9 @@ static void apply_ucode_in_initrd(void *ucode, size_t size)
                                 rev = mc->hdr.patch_id;
                                 *new_rev = rev;
 
-                                /* save ucode patch */
-                                memcpy(amd_ucode_patch, mc,
-                                       min_t(u32, header[1], PATCH_MAX_SIZE));
+                                if (save_patch)
+                                        memcpy(patch, mc,
+                                               min_t(u32, header[1], PATCH_MAX_SIZE));
                         }
                 }
 
@@ -246,7 +249,7 @@ void __init load_ucode_amd_bsp(void)
         *data = cp.data;
         *size = cp.size;
 
-        apply_ucode_in_initrd(cp.data, cp.size);
+        apply_ucode_in_initrd(cp.data, cp.size, true);
 }
 
 #ifdef CONFIG_X86_32
@@ -263,7 +266,7 @@ void load_ucode_amd_ap(void)
         size_t *usize;
         void **ucode;
 
-        mc = (struct microcode_amd *)__pa(amd_ucode_patch);
+        mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
         if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
                 __apply_microcode_amd(mc);
                 return;
@@ -275,7 +278,7 @@ void load_ucode_amd_ap(void)
         if (!*ucode || !*usize)
                 return;
 
-        apply_ucode_in_initrd(*ucode, *usize);
+        apply_ucode_in_initrd(*ucode, *usize, false);
 }
 
 static void __init collect_cpu_sig_on_bsp(void *arg)
@@ -339,7 +342,7 @@ void load_ucode_amd_ap(void)
                  * AP has a different equivalence ID than BSP, looks like
                  * mixed-steppings silicon so go through the ucode blob anew.
                  */
-                apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size);
+                apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
         }
 }
 #endif
@@ -347,7 +350,9 @@ void load_ucode_amd_ap(void)
 int __init save_microcode_in_initrd_amd(void)
 {
         unsigned long cont;
+        int retval = 0;
         enum ucode_state ret;
+        u8 *cont_va;
         u32 eax;
 
         if (!container)
@@ -355,13 +360,15 @@ int __init save_microcode_in_initrd_amd(void)
 
 #ifdef CONFIG_X86_32
         get_bsp_sig();
-        cont = (unsigned long)container;
+        cont    = (unsigned long)container;
+        cont_va = __va(container);
 #else
         /*
          * We need the physical address of the container for both bitness since
          * boot_params.hdr.ramdisk_image is a physical address.
          */
-        cont = __pa(container);
+        cont    = __pa(container);
+        cont_va = container;
 #endif
 
         /*
@@ -372,6 +379,8 @@ int __init save_microcode_in_initrd_amd(void)
         if (relocated_ramdisk)
                 container = (u8 *)(__va(relocated_ramdisk) +
                              (cont - boot_params.hdr.ramdisk_image));
+        else
+                container = cont_va;
 
         if (ucode_new_rev)
                 pr_info("microcode: updated early to new patch_level=0x%08x\n",
@@ -382,7 +391,7 @@ int __init save_microcode_in_initrd_amd(void)
 
         ret = load_microcode_amd(eax, container, container_size);
         if (ret != UCODE_OK)
-                return -EINVAL;
+                retval = -EINVAL;
 
         /*
          * This will be freed any msec now, stash patches for the current
@@ -391,5 +400,5 @@ int __init save_microcode_in_initrd_amd(void)
         container = NULL;
         container_size = 0;
 
-        return 0;
+        return retval;
 }
diff --git a/arch/x86/kernel/cpu/microcode/core_early.c b/arch/x86/kernel/cpu/microcode/core_early.c
index 5f28a64e71ea..2c017f242a78 100644
--- a/arch/x86/kernel/cpu/microcode/core_early.c
+++ b/arch/x86/kernel/cpu/microcode/core_early.c
@@ -124,7 +124,7 @@ void __init load_ucode_bsp(void)
 static bool check_loader_disabled_ap(void)
 {
 #ifdef CONFIG_X86_32
-        return __pa_nodebug(dis_ucode_ldr);
+        return *((bool *)__pa_nodebug(&dis_ucode_ldr));
 #else
         return dis_ucode_ldr;
 #endif
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 1b8299dd3d91..143e5f5dc855 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -243,8 +243,9 @@ static bool check_hw_exists(void)
 
 msr_fail:
         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
-        printk(boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR
-               "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
+        printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
+                boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
+                reg, val_new);
 
         return false;
 }
@@ -444,12 +445,6 @@ int x86_pmu_hw_config(struct perf_event *event)
         if (event->attr.type == PERF_TYPE_RAW)
                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 
-        if (event->attr.sample_period && x86_pmu.limit_period) {
-                if (x86_pmu.limit_period(event, event->attr.sample_period) >
-                                event->attr.sample_period)
-                        return -EINVAL;
-        }
-
         return x86_setup_perfctr(event);
 }
 
@@ -987,9 +982,6 @@ int x86_perf_event_set_period(struct perf_event *event)
         if (left > x86_pmu.max_period)
                 left = x86_pmu.max_period;
 
-        if (x86_pmu.limit_period)
-                left = x86_pmu.limit_period(event, left);
-
         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 
         /*
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index d98a34d435d7..fc5eb390b368 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -445,7 +445,6 @@ struct x86_pmu {
         struct x86_pmu_quirk *quirks;
         int             perfctr_second_write;
         bool            late_ack;
-        unsigned        (*limit_period)(struct perf_event *event, unsigned l);
 
         /*
          * sysfs attrs
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index a73947c53b65..944bf019b74f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -220,15 +220,6 @@ static struct event_constraint intel_hsw_event_constraints[] = {
         EVENT_CONSTRAINT_END
 };
 
-static struct event_constraint intel_bdw_event_constraints[] = {
-        FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
-        FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
-        INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
-        INTEL_EVENT_CONSTRAINT(0xa3, 0x4),      /* CYCLE_ACTIVITY.* */
-        EVENT_CONSTRAINT_END
-};
-
 static u64 intel_pmu_event_map(int hw_event)
 {
         return intel_perfmon_event_map[hw_event];
@@ -424,126 +415,6 @@ static __initconst const u64 snb_hw_cache_event_ids
 
 };
 
-static __initconst const u64 hsw_hw_cache_event_ids
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(L1D ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
-                [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(L1I ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
-                [ C(RESULT_ACCESS) ] = 0x1b7,
-                /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
-                   L3_MISS|ANY_SNOOP */
-                [ C(RESULT_MISS)   ] = 0x1b7,
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE:ALL_RFO */
-                /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
-                [ C(RESULT_MISS)   ] = 0x1b7,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(DTLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
-                [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
-                [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(ITLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
-                [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
- [ C(BPU ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
-                [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
-};
-
-static __initconst const u64 hsw_hw_cache_extra_regs
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
-                [ C(RESULT_ACCESS) ] = 0x2d5,
-                /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
-                   L3_MISS|ANY_SNOOP */
-                [ C(RESULT_MISS)   ] = 0x3fbc0202d5ull,
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x122,   /* OFFCORE_RESPONSE:ALL_RFO */
-                /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
-                [ C(RESULT_MISS)   ] = 0x3fbc020122ull,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
-};
-
 static __initconst const u64 westmere_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -2034,24 +1905,6 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
         return c;
 }
 
-/*
- * Broadwell:
- * The INST_RETIRED.ALL period always needs to have lowest
- * 6bits cleared (BDM57). It shall not use a period smaller
- * than 100 (BDM11). We combine the two to enforce
- * a min-period of 128.
- */
-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
-{
-        if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
-                        X86_CONFIG(.event=0xc0, .umask=0x01)) {
-                if (left < 128)
-                        left = 128;
-                left &= ~0x3fu;
-        }
-        return left;
-}
-
 PMU_FORMAT_ATTR(event,  "config:0-7"    );
 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
 PMU_FORMAT_ATTR(edge,   "config:18"     );
@@ -2692,8 +2545,8 @@ __init int intel_pmu_init(void)
         case 69: /* 22nm Haswell ULT */
         case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
                 x86_pmu.late_ack = true;
-                memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
-                memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+                memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
+                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
 
                 intel_pmu_lbr_init_snb();
 
@@ -2712,28 +2565,6 @@ __init int intel_pmu_init(void)
                 pr_cont("Haswell events, ");
                 break;
 
-        case 61: /* 14nm Broadwell Core-M */
-                x86_pmu.late_ack = true;
-                memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
-                memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
-
-                intel_pmu_lbr_init_snb();
-
-                x86_pmu.event_constraints = intel_bdw_event_constraints;
-                x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
-                x86_pmu.extra_regs = intel_snbep_extra_regs;
-                x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
-                /* all extra regs are per-cpu when HT is on */
-                x86_pmu.er_flags |= ERF_HAS_RSP_1;
-                x86_pmu.er_flags |= ERF_NO_HT_SHARING;
-
-                x86_pmu.hw_config = hsw_hw_config;
-                x86_pmu.get_event_constraints = hsw_get_event_constraints;
-                x86_pmu.cpu_events = hsw_events_attrs;
-                x86_pmu.limit_period = bdw_limit_period;
-                pr_cont("Broadwell events, ");
-                break;
-
         default:
                 switch (x86_pmu.version) {
                 case 1:
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index b553ed89e5f5..344b63f18d14 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -447,15 +447,14 @@ sysenter_exit:
 sysenter_audit:
         testl $(_TIF_WORK_SYSCALL_ENTRY & ~_TIF_SYSCALL_AUDIT),TI_flags(%ebp)
         jnz syscall_trace_entry
-        addl $4,%esp
-        CFI_ADJUST_CFA_OFFSET -4
-        movl %esi,4(%esp)               /* 5th arg: 4th syscall arg */
-        movl %edx,(%esp)                /* 4th arg: 3rd syscall arg */
-        /* %ecx already in %ecx            3rd arg: 2nd syscall arg */
-        movl %ebx,%edx                  /* 2nd arg: 1st syscall arg */
-        /* %eax already in %eax            1st arg: syscall number */
+        /* movl PT_EAX(%esp), %eax      already set, syscall number: 1st arg to audit */
+        movl PT_EBX(%esp), %edx         /* ebx/a0: 2nd arg to audit */
+        /* movl PT_ECX(%esp), %ecx      already set, a1: 3nd arg to audit */
+        pushl_cfi PT_ESI(%esp)          /* a3: 5th arg */
+        pushl_cfi PT_EDX+4(%esp)        /* a2: 4th arg */
         call __audit_syscall_entry
-        pushl_cfi %ebx
+        popl_cfi %ecx /* get that remapped edx off the stack */
+        popl_cfi %ecx /* get that remapped esi off the stack */
         movl PT_EAX(%esp),%eax          /* reload syscall number */
         jmp sysenter_do_call
 
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 8af817105e29..e7cc5370cd2f 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -111,8 +111,7 @@ static void make_8259A_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
         io_apic_irqs &= ~(1<<irq);
-        irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
-                                      i8259A_chip.name);
+        irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
         enable_irq(irq);
 }
 
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 44f1ed42fdf2..4de73ee78361 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -70,7 +70,6 @@ int vector_used_by_percpu_irq(unsigned int vector)
 void __init init_ISA_irqs(void)
 {
         struct irq_chip *chip = legacy_pic->chip;
-        const char *name = chip->name;
         int i;
 
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
@@ -79,7 +78,7 @@ void __init init_ISA_irqs(void)
         legacy_pic->init(0);
 
         for (i = 0; i < nr_legacy_irqs(); i++)
-                irq_set_chip_and_handler_name(i, chip, handle_level_irq, name);
+                irq_set_chip_and_handler(i, chip, handle_level_irq);
 }
 
 void __init init_IRQ(void)
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 235cfd39e0d7..ab08aa2276fb 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1128,7 +1128,6 @@ void __init setup_arch(char **cmdline_p)
         setup_real_mode();
 
         memblock_set_current_limit(get_max_mapped());
-        dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
 
         /*
          * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
@@ -1159,6 +1158,7 @@ void __init setup_arch(char **cmdline_p)
         early_acpi_boot_init();
 
         initmem_init();
+        dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
 
         /*
          * Reserve memory for crash kernel after SRAT is parsed so that it
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 2d5200e56357..668d8f2a8781 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -102,8 +102,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 EXPORT_PER_CPU_SYMBOL(cpu_info);
 
-static DEFINE_PER_CPU(struct completion, die_complete);
-
 atomic_t init_deasserted;
 
 /*
@@ -1305,10 +1303,14 @@ static void __ref remove_cpu_from_maps(int cpu)
         numa_remove_cpu(cpu);
 }
 
+static DEFINE_PER_CPU(struct completion, die_complete);
+
 void cpu_disable_common(void)
 {
         int cpu = smp_processor_id();
 
+        init_completion(&per_cpu(die_complete, smp_processor_id()));
+
         remove_siblinginfo(cpu);
 
         /* It's now safe to remove this processor from the online map */
@@ -1327,16 +1329,21 @@ int native_cpu_disable(void)
                 return ret;
 
         clear_local_APIC();
-        init_completion(&per_cpu(die_complete, smp_processor_id()));
         cpu_disable_common();
 
         return 0;
 }
 
+void cpu_die_common(unsigned int cpu)
+{
+        wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ);
+}
+
 void native_cpu_die(unsigned int cpu)
 {
         /* We don't do anything here: idle task is faking death itself. */
-        wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ);
+
+        cpu_die_common(cpu);
 
         /* They ack this in play_dead() by setting CPU_DEAD */
         if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index b6025f9e36c6..b7e50bba3bbb 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1166,14 +1166,17 @@ void __init tsc_init(void)
 
         x86_init.timers.tsc_pre_init();
 
-        if (!cpu_has_tsc)
+        if (!cpu_has_tsc) {
+                setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
                 return;
+        }
 
         tsc_khz = x86_platform.calibrate_tsc();
         cpu_khz = tsc_khz;
 
         if (!tsc_khz) {
                 mark_tsc_unstable("could not calculate TSC khz");
+                setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
                 return;
         }