Merge branch 'next' into for-linus

1 files changed, 5 insertions, 9 deletions

diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606d3e92..3ca42d0e43a2 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
                 csig->pf = 1 << ((val[1] >> 18) & 7);
         }
 
-        wrmsr(MSR_IA32_UCODE_REV, 0, 0);
-        /* see notes above for revision 1.07.  Apparent chip bug */
-        sync_core();
-        /* get the current revision from MSR 0x8B */
-        rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+        csig->rev = c->microcode;
         pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
                 cpu_num, csig->sig, csig->pf, csig->rev);
 
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
         struct microcode_intel *mc_intel;
         struct ucode_cpu_info *uci;
         unsigned int val[2];
-        int cpu_num;
+        int cpu_num = raw_smp_processor_id();
+        struct cpuinfo_x86 *c = &cpu_data(cpu_num);
 
-        cpu_num = raw_smp_processor_id();
         uci = ucode_cpu_info + cpu;
         mc_intel = uci->mc;
 
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
               (unsigned long) mc_intel->bits >> 16 >> 16);
         wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 
-        /* see notes above for revision 1.07.  Apparent chip bug */
+        /* As documented in the SDM: Do a CPUID 1 here */
         sync_core();
 
         /* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
                 (mc_intel->hdr.date >> 16) & 0xff);
 
         uci->cpu_sig.rev = val[1];
+        c->microcode = val[1];
 
         return 0;
 }