perf/x86/intel: Add Haswell PEBS support

Add simple PEBS support for Haswell.

The constraints are similar to SandyBridge with a few new
events.

Reviewed-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <ak@linux.jf.intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/1371515812-9646-4-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 4e995af0d384..4a4c4ba0c1d7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -889,7 +889,8 @@ static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
                 return true;
 
         /* implicit branch sampling to correct PEBS skid */
-        if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
+        if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
+            x86_pmu.intel_cap.pebs_format < 2)
                 return true;
 
         return false;
@@ -2265,8 +2266,9 @@ __init int intel_pmu_init(void)
                 intel_pmu_lbr_init_snb();
 
                 x86_pmu.event_constraints = intel_hsw_event_constraints;
-
+                x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
                 x86_pmu.extra_regs = intel_snb_extra_regs;
+                x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
                 /* all extra regs are per-cpu when HT is on */
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;