diff options
| author | Borislav Petkov <bp@suse.de> | 2016-02-03 06:33:37 -0500 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2016-02-09 05:41:17 -0500 |
| commit | de778275c295825e6638f3f74103f40642d45caa (patch) | |
| tree | 48f3187ff7b88203284f72b0dc143bd8b51d8d3f /arch/x86/kernel/cpu/microcode | |
| parent | 4fe9349fc3b042b481692b577bda97cde4d6f517 (diff) | |
x86/microcode/intel: Rename mc_intel variable to mc
Well, it is apparent what it points to - microcode. And since it is the
intel loader, no need for the "_intel" suffix. Use "!" for the 0/NULL
checks, while at it.
No functionality change.
Tested-by: Thomas Voegtle <tv@lio96.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1454499225-21544-10-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/microcode')
| -rw-r--r-- | arch/x86/kernel/cpu/microcode/intel.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 9f5fe72419ba..d1b2f583f543 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c | |||
| @@ -601,19 +601,19 @@ void show_ucode_info_early(void) | |||
| 601 | */ | 601 | */ |
| 602 | static void print_ucode(struct ucode_cpu_info *uci) | 602 | static void print_ucode(struct ucode_cpu_info *uci) |
| 603 | { | 603 | { |
| 604 | struct microcode_intel *mc_intel; | 604 | struct microcode_intel *mc; |
| 605 | int *delay_ucode_info_p; | 605 | int *delay_ucode_info_p; |
| 606 | int *current_mc_date_p; | 606 | int *current_mc_date_p; |
| 607 | 607 | ||
| 608 | mc_intel = uci->mc; | 608 | mc = uci->mc; |
| 609 | if (mc_intel == NULL) | 609 | if (!mc) |
| 610 | return; | 610 | return; |
| 611 | 611 | ||
| 612 | delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); | 612 | delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); |
| 613 | current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); | 613 | current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); |
| 614 | 614 | ||
| 615 | *delay_ucode_info_p = 1; | 615 | *delay_ucode_info_p = 1; |
| 616 | *current_mc_date_p = mc_intel->hdr.date; | 616 | *current_mc_date_p = mc->hdr.date; |
| 617 | } | 617 | } |
| 618 | #else | 618 | #else |
| 619 | 619 | ||
| @@ -628,29 +628,29 @@ static inline void flush_tlb_early(void) | |||
| 628 | 628 | ||
| 629 | static inline void print_ucode(struct ucode_cpu_info *uci) | 629 | static inline void print_ucode(struct ucode_cpu_info *uci) |
| 630 | { | 630 | { |
| 631 | struct microcode_intel *mc_intel; | 631 | struct microcode_intel *mc; |
| 632 | 632 | ||
| 633 | mc_intel = uci->mc; | 633 | mc = uci->mc; |
| 634 | if (mc_intel == NULL) | 634 | if (!mc) |
| 635 | return; | 635 | return; |
| 636 | 636 | ||
| 637 | print_ucode_info(uci, mc_intel->hdr.date); | 637 | print_ucode_info(uci, mc->hdr.date); |
| 638 | } | 638 | } |
| 639 | #endif | 639 | #endif |
| 640 | 640 | ||
| 641 | static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | 641 | static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) |
| 642 | { | 642 | { |
| 643 | struct microcode_intel *mc_intel; | 643 | struct microcode_intel *mc; |
| 644 | unsigned int val[2]; | 644 | unsigned int val[2]; |
| 645 | 645 | ||
| 646 | mc_intel = uci->mc; | 646 | mc = uci->mc; |
| 647 | if (mc_intel == NULL) | 647 | if (!mc) |
| 648 | return 0; | 648 | return 0; |
| 649 | 649 | ||
| 650 | /* write microcode via MSR 0x79 */ | 650 | /* write microcode via MSR 0x79 */ |
| 651 | native_wrmsr(MSR_IA32_UCODE_WRITE, | 651 | native_wrmsr(MSR_IA32_UCODE_WRITE, |
| 652 | (unsigned long) mc_intel->bits, | 652 | (unsigned long)mc->bits, |
| 653 | (unsigned long) mc_intel->bits >> 16 >> 16); | 653 | (unsigned long)mc->bits >> 16 >> 16); |
| 654 | native_wrmsr(MSR_IA32_UCODE_REV, 0, 0); | 654 | native_wrmsr(MSR_IA32_UCODE_REV, 0, 0); |
| 655 | 655 | ||
| 656 | /* As documented in the SDM: Do a CPUID 1 here */ | 656 | /* As documented in the SDM: Do a CPUID 1 here */ |
| @@ -658,7 +658,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |||
| 658 | 658 | ||
| 659 | /* get the current revision from MSR 0x8B */ | 659 | /* get the current revision from MSR 0x8B */ |
| 660 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | 660 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); |
| 661 | if (val[1] != mc_intel->hdr.rev) | 661 | if (val[1] != mc->hdr.rev) |
| 662 | return -1; | 662 | return -1; |
| 663 | 663 | ||
| 664 | #ifdef CONFIG_X86_64 | 664 | #ifdef CONFIG_X86_64 |
| @@ -670,7 +670,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |||
| 670 | if (early) | 670 | if (early) |
| 671 | print_ucode(uci); | 671 | print_ucode(uci); |
| 672 | else | 672 | else |
| 673 | print_ucode_info(uci, mc_intel->hdr.date); | 673 | print_ucode_info(uci, mc->hdr.date); |
| 674 | 674 | ||
| 675 | return 0; | 675 | return 0; |
| 676 | } | 676 | } |
| @@ -821,7 +821,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) | |||
| 821 | * return 0 - no update found | 821 | * return 0 - no update found |
| 822 | * return 1 - found update | 822 | * return 1 - found update |
| 823 | */ | 823 | */ |
| 824 | static int get_matching_mc(struct microcode_intel *mc_intel, int cpu) | 824 | static int get_matching_mc(struct microcode_intel *mc, int cpu) |
| 825 | { | 825 | { |
| 826 | struct cpu_signature cpu_sig; | 826 | struct cpu_signature cpu_sig; |
| 827 | unsigned int csig, cpf, crev; | 827 | unsigned int csig, cpf, crev; |
| @@ -832,38 +832,38 @@ static int get_matching_mc(struct microcode_intel *mc_intel, int cpu) | |||
| 832 | cpf = cpu_sig.pf; | 832 | cpf = cpu_sig.pf; |
| 833 | crev = cpu_sig.rev; | 833 | crev = cpu_sig.rev; |
| 834 | 834 | ||
| 835 | return has_newer_microcode(mc_intel, csig, cpf, crev); | 835 | return has_newer_microcode(mc, csig, cpf, crev); |
| 836 | } | 836 | } |
| 837 | 837 | ||
| 838 | static int apply_microcode_intel(int cpu) | 838 | static int apply_microcode_intel(int cpu) |
| 839 | { | 839 | { |
| 840 | struct microcode_intel *mc_intel; | 840 | struct microcode_intel *mc; |
| 841 | struct ucode_cpu_info *uci; | 841 | struct ucode_cpu_info *uci; |
| 842 | unsigned int val[2]; | 842 | unsigned int val[2]; |
| 843 | int cpu_num = raw_smp_processor_id(); | 843 | int cpu_num = raw_smp_processor_id(); |
| 844 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); | 844 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); |
| 845 | 845 | ||
| 846 | uci = ucode_cpu_info + cpu; | 846 | uci = ucode_cpu_info + cpu; |
| 847 | mc_intel = uci->mc; | 847 | mc = uci->mc; |
| 848 | 848 | ||
| 849 | /* We should bind the task to the CPU */ | 849 | /* We should bind the task to the CPU */ |
| 850 | BUG_ON(cpu_num != cpu); | 850 | BUG_ON(cpu_num != cpu); |
| 851 | 851 | ||
| 852 | if (mc_intel == NULL) | 852 | if (!mc) |
| 853 | return 0; | 853 | return 0; |
| 854 | 854 | ||
| 855 | /* | 855 | /* |
| 856 | * Microcode on this CPU could be updated earlier. Only apply the | 856 | * Microcode on this CPU could be updated earlier. Only apply the |
| 857 | * microcode patch in mc_intel when it is newer than the one on this | 857 | * microcode patch in mc when it is newer than the one on this |
| 858 | * CPU. | 858 | * CPU. |
| 859 | */ | 859 | */ |
| 860 | if (get_matching_mc(mc_intel, cpu) == 0) | 860 | if (!get_matching_mc(mc, cpu)) |
| 861 | return 0; | 861 | return 0; |
| 862 | 862 | ||
| 863 | /* write microcode via MSR 0x79 */ | 863 | /* write microcode via MSR 0x79 */ |
| 864 | wrmsr(MSR_IA32_UCODE_WRITE, | 864 | wrmsr(MSR_IA32_UCODE_WRITE, |
| 865 | (unsigned long) mc_intel->bits, | 865 | (unsigned long) mc->bits, |
| 866 | (unsigned long) mc_intel->bits >> 16 >> 16); | 866 | (unsigned long) mc->bits >> 16 >> 16); |
| 867 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); | 867 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); |
| 868 | 868 | ||
| 869 | /* As documented in the SDM: Do a CPUID 1 here */ | 869 | /* As documented in the SDM: Do a CPUID 1 here */ |
| @@ -872,16 +872,16 @@ static int apply_microcode_intel(int cpu) | |||
| 872 | /* get the current revision from MSR 0x8B */ | 872 | /* get the current revision from MSR 0x8B */ |
| 873 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | 873 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); |
| 874 | 874 | ||
| 875 | if (val[1] != mc_intel->hdr.rev) { | 875 | if (val[1] != mc->hdr.rev) { |
| 876 | pr_err("CPU%d update to revision 0x%x failed\n", | 876 | pr_err("CPU%d update to revision 0x%x failed\n", |
| 877 | cpu_num, mc_intel->hdr.rev); | 877 | cpu_num, mc->hdr.rev); |
| 878 | return -1; | 878 | return -1; |
| 879 | } | 879 | } |
| 880 | pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n", | 880 | pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n", |
| 881 | cpu_num, val[1], | 881 | cpu_num, val[1], |
| 882 | mc_intel->hdr.date & 0xffff, | 882 | mc->hdr.date & 0xffff, |
| 883 | mc_intel->hdr.date >> 24, | 883 | mc->hdr.date >> 24, |
| 884 | (mc_intel->hdr.date >> 16) & 0xff); | 884 | (mc->hdr.date >> 16) & 0xff); |
| 885 | 885 | ||
| 886 | uci->cpu_sig.rev = val[1]; | 886 | uci->cpu_sig.rev = val[1]; |
| 887 | c->microcode = val[1]; | 887 | c->microcode = val[1]; |
