diff options
author | Peter Zijlstra <peterz@infradead.org> | 2017-12-05 07:34:51 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2017-12-22 14:13:03 -0500 |
commit | 23cb7d46f371844c004784ad9552a57446f73e5a (patch) | |
tree | dd20a872135a37d11436300ef93e099ec62b7d54 /arch/x86/kernel/cpu/microcode/intel.c | |
parent | 3e46e0f5ee3643a1239be9046c7ba6c66ca2b329 (diff) |
x86/microcode: Dont abuse the TLB-flush interface
Commit:
ec400ddeff20 ("x86/microcode_intel_early.c: Early update ucode on Intel's CPU")
... grubbed into tlbflush internals without coherent explanation.
Since it says its a precaution and the SDM doesn't mention anything like
this, take it out back.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Laight <David.Laight@aculab.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eduardo Valentin <eduval@amazon.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: aliguori@amazon.com
Cc: daniel.gruss@iaik.tugraz.at
Cc: fenghua.yu@intel.com
Cc: hughd@google.com
Cc: keescook@google.com
Cc: linux-mm@kvack.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/microcode/intel.c')
-rw-r--r-- | arch/x86/kernel/cpu/microcode/intel.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 7dbcb7adf797..8ccdca6d3f9e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c | |||
@@ -565,15 +565,6 @@ static void print_ucode(struct ucode_cpu_info *uci) | |||
565 | } | 565 | } |
566 | #else | 566 | #else |
567 | 567 | ||
568 | /* | ||
569 | * Flush global tlb. We only do this in x86_64 where paging has been enabled | ||
570 | * already and PGE should be enabled as well. | ||
571 | */ | ||
572 | static inline void flush_tlb_early(void) | ||
573 | { | ||
574 | __native_flush_tlb_global_irq_disabled(); | ||
575 | } | ||
576 | |||
577 | static inline void print_ucode(struct ucode_cpu_info *uci) | 568 | static inline void print_ucode(struct ucode_cpu_info *uci) |
578 | { | 569 | { |
579 | struct microcode_intel *mc; | 570 | struct microcode_intel *mc; |
@@ -602,10 +593,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |||
602 | if (rev != mc->hdr.rev) | 593 | if (rev != mc->hdr.rev) |
603 | return -1; | 594 | return -1; |
604 | 595 | ||
605 | #ifdef CONFIG_X86_64 | ||
606 | /* Flush global tlb. This is precaution. */ | ||
607 | flush_tlb_early(); | ||
608 | #endif | ||
609 | uci->cpu_sig.rev = rev; | 596 | uci->cpu_sig.rev = rev; |
610 | 597 | ||
611 | if (early) | 598 | if (early) |