x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify)

- A few ESCR have escaped fixing at previous attempt.
- p4_escr_map is read only, make it const.

Nothing serious.

Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Lin Ming <ming.m.lin@intel.com>
LKML-Reference: <20100318211256.GH5062@lenovo>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 871249cf4d2b..2a1a57f71539 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -401,13 +401,13 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
 #define P4_RETIRED_MISPRED_BRANCH_TYPE  P4_EVENT_PACK(0x05, 0x02)
         /*
          * MSR_P4_TBPU_ESCR0:   4, 5
-         * MSR_P4_TBPU_ESCR0:   6, 7
+         * MSR_P4_TBPU_ESCR1:   6, 7
          */
 
 #define P4_RETIRED_BRANCH_TYPE          P4_EVENT_PACK(0x04, 0x02)
         /*
          * MSR_P4_TBPU_ESCR0:   4, 5
-         * MSR_P4_TBPU_ESCR0:   6, 7
+         * MSR_P4_TBPU_ESCR1:   6, 7
          */
 
 #define P4_RESOURCE_STALL               P4_EVENT_PACK(0x01, 0x01)