Merge tag 'v4.6-rc4' into sched/core, to refresh the tree

Signed-off-by: Ingo Molnar <mingo@kernel.org>
author: Ingo Molnar <mingo@kernel.org> 2016-04-23 08:16:36 -0400
committer: Ingo Molnar <mingo@kernel.org> 2016-04-23 08:16:36 -0400
commit: 84eaae155a16d7864f0f814934e5062885cb0709 (patch)
tree: afdbb8a4375a2d755f6e4d63767396bfc4124c50 /arch/x86/events
parent: f454bfddf6ba557381d8bf5df50eff778602ff23 (diff)
parent: c3b46c73264b03000d1e18b22f5caf63332547c9 (diff)
3 files changed, 71 insertions, 13 deletions
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 049ada8d4e9c..86a9bec18dab 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -369,7 +369,7 @@ static int amd_pmu_cpu_prepare(int cpu)
        WARN_ON_ONCE(cpuc->amd_nb);
-        if (boot_cpu_data.x86_max_cores < 2)
+        if (!x86_pmu.amd_nb_constraints)
                return NOTIFY_OK;
        cpuc->amd_nb = amd_alloc_nb(cpu);
@@ -388,7 +388,7 @@ static void amd_pmu_cpu_starting(int cpu)
        cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
-        if (boot_cpu_data.x86_max_cores < 2)
+        if (!x86_pmu.amd_nb_constraints)
                return;
        nb_id = amd_get_nb_id(cpu);
@@ -414,7 +414,7 @@ static void amd_pmu_cpu_dead(int cpu)
 {
        struct cpu_hw_events *cpuhw;
-        if (boot_cpu_data.x86_max_cores < 2)
+        if (!x86_pmu.amd_nb_constraints)
                return;
        cpuhw = &per_cpu(cpu_hw_events, cpu);
@@ -648,6 +648,8 @@ static __initconst const struct x86_pmu amd_pmu = {
        .cpu_prepare            = amd_pmu_cpu_prepare,
        .cpu_starting           = amd_pmu_cpu_starting,
        .cpu_dead               = amd_pmu_cpu_dead,
+        .amd_nb_constraints     = 1,
 };
 static int __init amd_core_pmu_init(void)
@@ -674,6 +676,11 @@ static int __init amd_core_pmu_init(void)
        x86_pmu.eventsel        = MSR_F15H_PERF_CTL;
        x86_pmu.perfctr         = MSR_F15H_PERF_CTR;
        x86_pmu.num_counters    = AMD64_NUM_COUNTERS_CORE;
+        /*
+         * AMD Core perfctr has separate MSRs for the NB events, see
+         * the amd/uncore.c driver.
+         */
+        x86_pmu.amd_nb_constraints = 0;
        pr_cont("core perfctr, ");
        return 0;
@@ -693,6 +700,14 @@ __init int amd_pmu_init(void)
        if (ret)
                return ret;
+        if (num_possible_cpus() == 1) {
+                /*
+                 * No point in allocating data structures to serialize
+                 * against other CPUs, when there is only the one CPU.
+                 */
+                x86_pmu.amd_nb_constraints = 0;
+        }
        /* Events are common for all AMDs */
        memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
               sizeof(hw_cache_event_ids));
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 3ea25c3917c0..feb90f6730e8 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -28,10 +28,46 @@ static u32 ibs_caps;
 #define IBS_FETCH_CONFIG_MASK   (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
 #define IBS_OP_CONFIG_MASK      IBS_OP_MAX_CNT
+/*
+ * IBS states:
+ *
+ * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
+ * and any further add()s must fail.
+ *
+ * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
+ * complicated by the fact that the IBS hardware can send late NMIs (ie. after
+ * we've cleared the EN bit).
+ *
+ * In order to consume these late NMIs we have the STOPPED state, any NMI that
+ * happens after we've cleared the EN state will clear this bit and report the
+ * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
+ * someone else can consume our BIT and our NMI will go unhandled).
+ *
+ * And since we cannot set/clear this separate bit together with the EN bit,
+ * there are races; if we cleared STARTED early, an NMI could land in
+ * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
+ * could happen if the period is small enough), and consume our STOPPED bit
+ * and trigger streams of unhandled NMIs.
+ *
+ * If, however, we clear STARTED late, an NMI can hit between clearing the
+ * EN bit and clearing STARTED, still see STARTED set and process the event.
+ * If this event will have the VALID bit clear, we bail properly, but this
+ * is not a given. With VALID set we can end up calling pmu::stop() again
+ * (the throttle logic) and trigger the WARNs in there.
+ *
+ * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
+ * nesting, and clear STARTED late, so that we have a well defined state over
+ * the clearing of the EN bit.
+ *
+ * XXX: we could probably be using !atomic bitops for all this.
+ */
 enum ibs_states {
        IBS_ENABLED     = 0,
        IBS_STARTED     = 1,
        IBS_STOPPING    = 2,
+        IBS_STOPPED     = 3,
        IBS_MAX_STATES,
 };
@@ -377,11 +413,10 @@ static void perf_ibs_start(struct perf_event *event, int flags)
        perf_ibs_set_period(perf_ibs, hwc, &period);
        /*
-         * Set STARTED before enabling the hardware, such that
+         * Set STARTED before enabling the hardware, such that a subsequent NMI
-         * a subsequent NMI must observe it. Then clear STOPPING
+         * must observe it.
-         * such that we don't consume NMIs by accident.
         */
-        set_bit(IBS_STARTED, pcpu->state);
+        set_bit(IBS_STARTED,    pcpu->state);
        clear_bit(IBS_STOPPING, pcpu->state);
        perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
@@ -396,6 +431,9 @@ static void perf_ibs_stop(struct perf_event *event, int flags)
        u64 config;
        int stopping;
+        if (test_and_set_bit(IBS_STOPPING, pcpu->state))
+                return;
        stopping = test_bit(IBS_STARTED, pcpu->state);
        if (!stopping && (hwc->state & PERF_HES_UPTODATE))
@@ -405,12 +443,12 @@ static void perf_ibs_stop(struct perf_event *event, int flags)
        if (stopping) {
                /*
-                 * Set STOPPING before disabling the hardware, such that it
+                 * Set STOPPED before disabling the hardware, such that it
                 * must be visible to NMIs the moment we clear the EN bit,
                 * at which point we can generate an !VALID sample which
                 * we need to consume.
                 */
-                set_bit(IBS_STOPPING, pcpu->state);
+                set_bit(IBS_STOPPED, pcpu->state);
                perf_ibs_disable_event(perf_ibs, hwc, config);
                /*
                 * Clear STARTED after disabling the hardware; if it were
@@ -556,7 +594,7 @@ fail:
                 * with samples that even have the valid bit cleared.
                 * Mark all this NMIs as handled.
                 */
-                if (test_and_clear_bit(IBS_STOPPING, pcpu->state))
+                if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
                        return 1;
                return 0;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index ba6ef18528c9..ad4dc7ffffb5 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -608,6 +608,11 @@ struct x86_pmu {
        atomic_t        lbr_exclusive[x86_lbr_exclusive_max];
        /*
+         * AMD bits
+         */
+        unsigned int    amd_nb_constraints : 1;
+        /*
         * Extra registers for events
         */
        struct extra_reg *extra_regs;
@@ -795,6 +800,9 @@ ssize_t intel_event_sysfs_show(char *page, u64 config);
 struct attribute **merge_attr(struct attribute **a, struct attribute **b);
+ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
+                          char *page);
 #ifdef CONFIG_CPU_SUP_AMD
 int amd_pmu_init(void);
@@ -925,9 +933,6 @@ int p6_pmu_init(void);
 int knc_pmu_init(void);
-ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
-                          char *page);
 static inline int is_ht_workaround_enabled(void)
 {
        return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
author	Ingo Molnar <mingo@kernel.org>	2016-04-23 08:16:36 -0400
committer	Ingo Molnar <mingo@kernel.org>	2016-04-23 08:16:36 -0400
commit	84eaae155a16d7864f0f814934e5062885cb0709 (patch)
tree	afdbb8a4375a2d755f6e4d63767396bfc4124c50 /arch/x86/events
parent	f454bfddf6ba557381d8bf5df50eff778602ff23 (diff)
parent	c3b46c73264b03000d1e18b22f5caf63332547c9 (diff)