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authorKan Liang <kan.liang@intel.com>2016-03-20 14:58:21 -0400
committerIngo Molnar <mingo@kernel.org>2016-03-21 06:16:19 -0400
commitcb2252522aaff572f28dc6613307e1e0e62496cd (patch)
tree69d6bb9c78fe6935b0c220a61fad654b41e46f30 /arch/x86/events/intel
parentc7ab62bfbe0e27ef452d19d88b083f01e99f13a7 (diff)
perf/x86/intel/uncore: Remove ev_sel_ext bit support for PCU
The ev_sel_ext in PCU_MSR_PMON_CTL is locked on some CPU models, so despite it being documented in the SDM, if we write 1 to that bit then we can get a #GP fault. Which #GP the perf fuzzer happily triggered in Peter Zijlstra's testing. Also, there are no public events which use that bit, so remove ev_sel_ext bit support for PCU. Reported-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@intel.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1458500301-3594-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/events/intel')
-rw-r--r--arch/x86/events/intel/uncore_snbep.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 93f6bd9bf761..ab2bcaaebe38 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -46,7 +46,6 @@
46 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 46 (SNBEP_PMON_CTL_EV_SEL_MASK | \
47 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 47 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
48 SNBEP_PMON_CTL_EDGE_DET | \ 48 SNBEP_PMON_CTL_EDGE_DET | \
49 SNBEP_PMON_CTL_EV_SEL_EXT | \
50 SNBEP_PMON_CTL_INVERT | \ 49 SNBEP_PMON_CTL_INVERT | \
51 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 50 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
52 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 51 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -148,7 +147,6 @@
148/* IVBEP PCU */ 147/* IVBEP PCU */
149#define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 148#define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
150 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 149 (SNBEP_PMON_CTL_EV_SEL_MASK | \
151 SNBEP_PMON_CTL_EV_SEL_EXT | \
152 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 150 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
153 SNBEP_PMON_CTL_EDGE_DET | \ 151 SNBEP_PMON_CTL_EDGE_DET | \
154 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 152 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
@@ -258,7 +256,6 @@
258 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 256 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
259 SNBEP_PMON_CTL_EDGE_DET | \ 257 SNBEP_PMON_CTL_EDGE_DET | \
260 SNBEP_CBO_PMON_CTL_TID_EN | \ 258 SNBEP_CBO_PMON_CTL_TID_EN | \
261 SNBEP_PMON_CTL_EV_SEL_EXT | \
262 SNBEP_PMON_CTL_INVERT | \ 259 SNBEP_PMON_CTL_INVERT | \
263 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ 260 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \
264 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 261 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
@@ -472,7 +469,7 @@ static struct attribute *snbep_uncore_cbox_formats_attr[] = {
472}; 469};
473 470
474static struct attribute *snbep_uncore_pcu_formats_attr[] = { 471static struct attribute *snbep_uncore_pcu_formats_attr[] = {
475 &format_attr_event_ext.attr, 472 &format_attr_event.attr,
476 &format_attr_occ_sel.attr, 473 &format_attr_occ_sel.attr,
477 &format_attr_edge.attr, 474 &format_attr_edge.attr,
478 &format_attr_inv.attr, 475 &format_attr_inv.attr,
@@ -1313,7 +1310,7 @@ static struct attribute *ivbep_uncore_cbox_formats_attr[] = {
1313}; 1310};
1314 1311
1315static struct attribute *ivbep_uncore_pcu_formats_attr[] = { 1312static struct attribute *ivbep_uncore_pcu_formats_attr[] = {
1316 &format_attr_event_ext.attr, 1313 &format_attr_event.attr,
1317 &format_attr_occ_sel.attr, 1314 &format_attr_occ_sel.attr,
1318 &format_attr_edge.attr, 1315 &format_attr_edge.attr,
1319 &format_attr_thresh5.attr, 1316 &format_attr_thresh5.attr,