diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-05 13:32:52 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-06 12:55:56 -0400 |
| commit | 8d9e53b93de7383d5bb4b3507f146bfcd83c6e5d (patch) | |
| tree | 7a54bc1d199b384f0b58263e71489a0d9aed5dea /arch/tile/kernel/pci_gx.c | |
| parent | eafa5c8a10f52e5d05870a40e2ffb49537d4471f (diff) | |
tile PCI RC: use proper accessor function
Using the low-level hv_dev_pread() API makes assumptions about the
layout of datastructures in the Tilera hypervisor API; it's better to
use the gxio_XXX accessor and the pcie_trio_ports_property struct.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/pci_gx.c')
| -rw-r--r-- | arch/tile/kernel/pci_gx.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 8352d85ab818..de5008b72fa3 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c | |||
| @@ -91,7 +91,7 @@ static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | |||
| 91 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 | 91 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 |
| 92 | 92 | ||
| 93 | /* Array of the PCIe ports configuration info obtained from the BIB. */ | 93 | /* Array of the PCIe ports configuration info obtained from the BIB. */ |
| 94 | struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | 94 | struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO]; |
| 95 | 95 | ||
| 96 | /* Number of configured TRIO instances. */ | 96 | /* Number of configured TRIO instances. */ |
| 97 | int num_trio_shims; | 97 | int num_trio_shims; |
| @@ -195,10 +195,7 @@ static int tile_pcie_open(int trio_index) | |||
| 195 | #endif | 195 | #endif |
| 196 | 196 | ||
| 197 | /* Get the properties of the PCIe ports on this TRIO instance. */ | 197 | /* Get the properties of the PCIe ports on this TRIO instance. */ |
| 198 | ret = hv_dev_pread(context->fd, 0, | 198 | ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]); |
| 199 | (HV_VirtAddr)&pcie_ports[trio_index][0], | ||
| 200 | sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES, | ||
| 201 | GXIO_TRIO_OP_GET_PORT_PROPERTY); | ||
| 202 | if (ret < 0) { | 199 | if (ret < 0) { |
| 203 | pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d," | 200 | pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d," |
| 204 | " on TRIO %d\n", ret, trio_index); | 201 | " on TRIO %d\n", ret, trio_index); |
| @@ -221,8 +218,8 @@ static int tile_pcie_open(int trio_index) | |||
| 221 | unsigned int reg_offset; | 218 | unsigned int reg_offset; |
| 222 | 219 | ||
| 223 | /* Ignore ports that are not specified in the BIB. */ | 220 | /* Ignore ports that are not specified in the BIB. */ |
| 224 | if (!pcie_ports[trio_index][mac].allow_rc && | 221 | if (!pcie_ports[trio_index].ports[mac].allow_rc && |
| 225 | !pcie_ports[trio_index][mac].allow_ep) | 222 | !pcie_ports[trio_index].ports[mac].allow_ep) |
| 226 | continue; | 223 | continue; |
| 227 | 224 | ||
| 228 | reg_offset = | 225 | reg_offset = |
| @@ -243,7 +240,7 @@ static int tile_pcie_open(int trio_index) | |||
| 243 | */ | 240 | */ |
| 244 | if (port_config.strap_state == AUTO_CONFIG_EP || | 241 | if (port_config.strap_state == AUTO_CONFIG_EP || |
| 245 | port_config.strap_state == AUTO_CONFIG_EP_G1) | 242 | port_config.strap_state == AUTO_CONFIG_EP_G1) |
| 246 | pcie_ports[trio_index][mac].allow_ep = 1; | 243 | pcie_ports[trio_index].ports[mac].allow_ep = 1; |
| 247 | } | 244 | } |
| 248 | } | 245 | } |
| 249 | 246 | ||
| @@ -438,9 +435,10 @@ int __init tile_pci_init(void) | |||
| 438 | return 0; | 435 | return 0; |
| 439 | 436 | ||
| 440 | /* | 437 | /* |
| 441 | * Now determine which PCIe ports are configured to operate in RC mode. | 438 | * Now determine which PCIe ports are configured to operate in RC |
| 442 | * We look at the Board Information Block first and then see if there | 439 | * mode. To use a port, it must be allowed to be in RC mode by the |
| 443 | * are any overriding configuration by the HW strapping pin. | 440 | * Board Information Block, and the hardware strapping pins must be |
| 441 | * set to RC mode. | ||
| 444 | */ | 442 | */ |
| 445 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | 443 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { |
| 446 | gxio_trio_context_t *context = &trio_contexts[i]; | 444 | gxio_trio_context_t *context = &trio_contexts[i]; |
| @@ -449,7 +447,7 @@ int __init tile_pci_init(void) | |||
| 449 | continue; | 447 | continue; |
| 450 | 448 | ||
| 451 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { | 449 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { |
| 452 | if (pcie_ports[i][j].allow_rc && | 450 | if (pcie_ports[i].ports[j].allow_rc && |
| 453 | strapped_for_rc(context, j)) { | 451 | strapped_for_rc(context, j)) { |
| 454 | pcie_rc[i][j] = 1; | 452 | pcie_rc[i][j] = 1; |
| 455 | num_rc_controllers++; | 453 | num_rc_controllers++; |
| @@ -736,7 +734,7 @@ int __init pcibios_init(void) | |||
| 736 | __gxio_mmio_read(trio_context->mmio_base_mac + | 734 | __gxio_mmio_read(trio_context->mmio_base_mac + |
| 737 | reg_offset); | 735 | reg_offset); |
| 738 | if (!port_status.dl_up) { | 736 | if (!port_status.dl_up) { |
| 739 | if (pcie_ports[trio_index][mac].removable) { | 737 | if (pcie_ports[trio_index].ports[mac].removable) { |
| 740 | pr_info("PCI: link is down, MAC %d on TRIO %d\n", | 738 | pr_info("PCI: link is down, MAC %d on TRIO %d\n", |
| 741 | mac, trio_index); | 739 | mac, trio_index); |
| 742 | pr_info("This is expected if no PCIe card" | 740 | pr_info("This is expected if no PCIe card" |