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authorChris Metcalf <cmetcalf@tilera.com>2013-08-15 16:23:24 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-09-03 14:53:29 -0400
commitd7c9661115fd23b4dabb710b3080dd9919dfa891 (patch)
tree5eaeb8c4aab296f39d6aa896ec9408419ec17441 /arch/tile/include/asm/processor.h
parentd6a0aa314c06743b702931cb468f400b7615c5c9 (diff)
tile: remove support for TILE64
This chip is no longer being actively developed for (it was superceded by the TILEPro64 in 2008), and in any case the existing compiler and toolchain in the community do not support it. It's unlikely that the kernel works with TILE64 at this point as the configuration has not been tested in years. The support is also awkward as it requires maintaining a significant number of ifdefs. So, just remove it altogether. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/processor.h')
-rw-r--r--arch/tile/include/asm/processor.h16
1 files changed, 0 insertions, 16 deletions
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index 5aa54319d2ef..42323636c459 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -113,18 +113,14 @@ struct thread_struct {
113 unsigned long intctrl_0; 113 unsigned long intctrl_0;
114 /* Is this task currently doing a backtrace? */ 114 /* Is this task currently doing a backtrace? */
115 bool in_backtrace; 115 bool in_backtrace;
116#if CHIP_HAS_PROC_STATUS_SPR()
117 /* Any other miscellaneous processor state bits */ 116 /* Any other miscellaneous processor state bits */
118 unsigned long proc_status; 117 unsigned long proc_status;
119#endif
120#if !CHIP_HAS_FIXED_INTVEC_BASE() 118#if !CHIP_HAS_FIXED_INTVEC_BASE()
121 /* Interrupt base for PL0 interrupts */ 119 /* Interrupt base for PL0 interrupts */
122 unsigned long interrupt_vector_base; 120 unsigned long interrupt_vector_base;
123#endif 121#endif
124#if CHIP_HAS_TILE_RTF_HWM()
125 /* Tile cache retry fifo high-water mark */ 122 /* Tile cache retry fifo high-water mark */
126 unsigned long tile_rtf_hwm; 123 unsigned long tile_rtf_hwm;
127#endif
128#if CHIP_HAS_DSTREAM_PF() 124#if CHIP_HAS_DSTREAM_PF()
129 /* Data stream prefetch control */ 125 /* Data stream prefetch control */
130 unsigned long dstream_pf; 126 unsigned long dstream_pf;
@@ -137,12 +133,6 @@ struct thread_struct {
137 /* Async DMA TLB fault information */ 133 /* Async DMA TLB fault information */
138 struct async_tlb dma_async_tlb; 134 struct async_tlb dma_async_tlb;
139#endif 135#endif
140#if CHIP_HAS_SN_PROC()
141 /* Was static network processor when we were switched out? */
142 int sn_proc_running;
143 /* Async SNI TLB fault information */
144 struct async_tlb sn_async_tlb;
145#endif
146}; 136};
147 137
148#endif /* !__ASSEMBLY__ */ 138#endif /* !__ASSEMBLY__ */
@@ -286,7 +276,6 @@ extern char chip_model[64];
286/* Data on which physical memory controller corresponds to which NUMA node. */ 276/* Data on which physical memory controller corresponds to which NUMA node. */
287extern int node_controller[]; 277extern int node_controller[];
288 278
289#if CHIP_HAS_CBOX_HOME_MAP()
290/* Does the heap allocator return hash-for-home pages by default? */ 279/* Does the heap allocator return hash-for-home pages by default? */
291extern int hash_default; 280extern int hash_default;
292 281
@@ -296,11 +285,6 @@ extern int kstack_hash;
296/* Does MAP_ANONYMOUS return hash-for-home pages by default? */ 285/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
297#define uheap_hash hash_default 286#define uheap_hash hash_default
298 287
299#else
300#define hash_default 0
301#define kstack_hash 0
302#define uheap_hash 0
303#endif
304 288
305/* Are we using huge pages in the TLB for kernel data? */ 289/* Are we using huge pages in the TLB for kernel data? */
306extern int kdata_huge; 290extern int kdata_huge;