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authorPaul Mackerras <paulus@samba.org>2008-04-24 06:57:20 -0400
committerPaul Mackerras <paulus@samba.org>2008-04-24 06:57:20 -0400
commit36a23fc8aa0c72ecafe7aaee0a823b03b301e1df (patch)
tree364aa8cf248b477d822d0344d7bba3c80f86cf9c /arch/ppc/platforms
parent23386fe572028ca0f9249fb3c71ed31b54cf1665 (diff)
parentfc215fe7e6f0420afee0e0987fcc311929ee662f (diff)
Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/Makefile4
-rw-r--r--arch/ppc/platforms/fads.h25
-rw-r--r--arch/ppc/platforms/mpc8272ads_setup.c367
-rw-r--r--arch/ppc/platforms/mpc885ads.h93
-rw-r--r--arch/ppc/platforms/mpc885ads_setup.c476
-rw-r--r--arch/ppc/platforms/pq2ads.c53
-rw-r--r--arch/ppc/platforms/pq2ads.h94
-rw-r--r--arch/ppc/platforms/pq2ads_pd.h32
8 files changed, 0 insertions, 1144 deletions
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 40f53fbe6d35..6260231987cb 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o 5obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
6obj-$(CONFIG_PREP_RESIDUAL) += residual.o 6obj-$(CONFIG_PREP_RESIDUAL) += residual.o
7obj-$(CONFIG_PQ2ADS) += pq2ads.o
8obj-$(CONFIG_TQM8260) += tqm8260_setup.o 7obj-$(CONFIG_TQM8260) += tqm8260_setup.o
9obj-$(CONFIG_CPCI690) += cpci690.o 8obj-$(CONFIG_CPCI690) += cpci690.o
10obj-$(CONFIG_EV64260) += ev64260.o 9obj-$(CONFIG_EV64260) += ev64260.o
@@ -24,6 +23,3 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
24obj-$(CONFIG_SPRUCE) += spruce.o 23obj-$(CONFIG_SPRUCE) += spruce.o
25obj-$(CONFIG_LITE5200) += lite5200.o 24obj-$(CONFIG_LITE5200) += lite5200.o
26obj-$(CONFIG_EV64360) += ev64360.o 25obj-$(CONFIG_EV64360) += ev64360.o
27obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
28obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
29obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
index 2f9f0f60e3f7..5219366667b3 100644
--- a/arch/ppc/platforms/fads.h
+++ b/arch/ppc/platforms/fads.h
@@ -22,29 +22,6 @@
22 22
23#include <asm/ppcboot.h> 23#include <asm/ppcboot.h>
24 24
25#if defined(CONFIG_MPC86XADS)
26
27#define BOARD_CHIP_NAME "MPC86X"
28
29/* U-Boot maps BCSR to 0xff080000 */
30#define BCSR_ADDR ((uint)0xff080000)
31
32/* MPC86XADS has one more CPLD and an additional BCSR.
33 */
34#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
35#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
36
37#define BCSR5_T1_RST 0x10
38#define BCSR5_ATM155_RST 0x08
39#define BCSR5_ATM25_RST 0x04
40#define BCSR5_MII1_EN 0x02
41#define BCSR5_MII1_RST 0x01
42
43/* There is no PHY link change interrupt */
44#define PHY_INTERRUPT (-1)
45
46#else /* FADS */
47
48/* Memory map is configured by the PROM startup. 25/* Memory map is configured by the PROM startup.
49 * I tried to follow the FADS manual, although the startup PROM 26 * I tried to follow the FADS manual, although the startup PROM
50 * dictates this and we simply have to move some of the physical 27 * dictates this and we simply have to move some of the physical
@@ -55,8 +32,6 @@
55/* PHY link change interrupt */ 32/* PHY link change interrupt */
56#define PHY_INTERRUPT SIU_IRQ2 33#define PHY_INTERRUPT SIU_IRQ2
57 34
58#endif /* CONFIG_MPC86XADS */
59
60#define BCSR_SIZE ((uint)(64 * 1024)) 35#define BCSR_SIZE ((uint)(64 * 1024))
61#define BCSR0 ((uint)(BCSR_ADDR + 0x00)) 36#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
62#define BCSR1 ((uint)(BCSR_ADDR + 0x04)) 37#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
deleted file mode 100644
index 47f4b38edb5f..000000000000
--- a/arch/ppc/platforms/mpc8272ads_setup.c
+++ /dev/null
@@ -1,367 +0,0 @@
1/*
2 * arch/ppc/platforms/mpc8272ads_setup.c
3 *
4 * MPC82xx Board-specific PlatformDevice descriptions
5 *
6 * 2005 (c) MontaVista Software, Inc.
7 * Vitaly Bordug <vbordug@ru.mvista.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/device.h>
18#include <linux/ioport.h>
19#include <linux/fs_enet_pd.h>
20#include <linux/platform_device.h>
21#include <linux/phy.h>
22
23#include <asm/io.h>
24#include <asm/mpc8260.h>
25#include <asm/cpm2.h>
26#include <asm/immap_cpm2.h>
27#include <asm/irq.h>
28#include <asm/ppc_sys.h>
29#include <asm/ppcboot.h>
30#include <linux/fs_uart_pd.h>
31
32#include "pq2ads_pd.h"
33
34static void init_fcc1_ioports(struct fs_platform_info*);
35static void init_fcc2_ioports(struct fs_platform_info*);
36static void init_scc1_uart_ioports(struct fs_uart_platform_info*);
37static void init_scc4_uart_ioports(struct fs_uart_platform_info*);
38
39static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
40 [fsid_scc1_uart] = {
41 .init_ioports = init_scc1_uart_ioports,
42 .fs_no = fsid_scc1_uart,
43 .brg = 1,
44 .tx_num_fifo = 4,
45 .tx_buf_size = 32,
46 .rx_num_fifo = 4,
47 .rx_buf_size = 32,
48 },
49 [fsid_scc4_uart] = {
50 .init_ioports = init_scc4_uart_ioports,
51 .fs_no = fsid_scc4_uart,
52 .brg = 4,
53 .tx_num_fifo = 4,
54 .tx_buf_size = 32,
55 .rx_num_fifo = 4,
56 .rx_buf_size = 32,
57 },
58};
59
60static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
61 .mdio_dat.bit = 18,
62 .mdio_dir.bit = 18,
63 .mdc_dat.bit = 19,
64 .delay = 1,
65};
66
67static struct fs_platform_info mpc82xx_enet_pdata[] = {
68 [fsid_fcc1] = {
69 .fs_no = fsid_fcc1,
70 .cp_page = CPM_CR_FCC1_PAGE,
71 .cp_block = CPM_CR_FCC1_SBLOCK,
72
73 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
74 .clk_route = CMX1_CLK_ROUTE,
75 .clk_mask = CMX1_CLK_MASK,
76 .init_ioports = init_fcc1_ioports,
77
78 .mem_offset = FCC1_MEM_OFFSET,
79
80 .rx_ring = 32,
81 .tx_ring = 32,
82 .rx_copybreak = 240,
83 .use_napi = 0,
84 .napi_weight = 17,
85 .bus_id = "0:00",
86 },
87 [fsid_fcc2] = {
88 .fs_no = fsid_fcc2,
89 .cp_page = CPM_CR_FCC2_PAGE,
90 .cp_block = CPM_CR_FCC2_SBLOCK,
91 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
92 .clk_route = CMX2_CLK_ROUTE,
93 .clk_mask = CMX2_CLK_MASK,
94 .init_ioports = init_fcc2_ioports,
95
96 .mem_offset = FCC2_MEM_OFFSET,
97
98 .rx_ring = 32,
99 .tx_ring = 32,
100 .rx_copybreak = 240,
101 .use_napi = 0,
102 .napi_weight = 17,
103 .bus_id = "0:03",
104 },
105};
106
107static void init_fcc1_ioports(struct fs_platform_info* pdata)
108{
109 struct io_port *io;
110 u32 tempval;
111 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
112 u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
113
114 io = &immap->im_ioport;
115
116 /* Enable the PHY */
117 clrbits32(bcsr, BCSR1_FETHIEN);
118 setbits32(bcsr, BCSR1_FETH_RST);
119
120 /* FCC1 pins are on port A/C. */
121 /* Configure port A and C pins for FCC1 Ethernet. */
122
123 tempval = in_be32(&io->iop_pdira);
124 tempval &= ~PA1_DIRA0;
125 tempval |= PA1_DIRA1;
126 out_be32(&io->iop_pdira, tempval);
127
128 tempval = in_be32(&io->iop_psora);
129 tempval &= ~PA1_PSORA0;
130 tempval |= PA1_PSORA1;
131 out_be32(&io->iop_psora, tempval);
132
133 setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
134
135 /* Alter clocks */
136 tempval = PC_F1TXCLK|PC_F1RXCLK;
137
138 clrbits32(&io->iop_psorc, tempval);
139 clrbits32(&io->iop_pdirc, tempval);
140 setbits32(&io->iop_pparc, tempval);
141
142 clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
143 setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
144 iounmap(bcsr);
145 iounmap(immap);
146}
147
148static void init_fcc2_ioports(struct fs_platform_info* pdata)
149{
150 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
151 u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
152
153 struct io_port *io;
154 u32 tempval;
155
156 immap = cpm2_immr;
157
158 io = &immap->im_ioport;
159
160 /* Enable the PHY */
161 clrbits32(bcsr, BCSR3_FETHIEN2);
162 setbits32(bcsr, BCSR3_FETH2_RST);
163
164 /* FCC2 are port B/C. */
165 /* Configure port A and C pins for FCC2 Ethernet. */
166
167 tempval = in_be32(&io->iop_pdirb);
168 tempval &= ~PB2_DIRB0;
169 tempval |= PB2_DIRB1;
170 out_be32(&io->iop_pdirb, tempval);
171
172 tempval = in_be32(&io->iop_psorb);
173 tempval &= ~PB2_PSORB0;
174 tempval |= PB2_PSORB1;
175 out_be32(&io->iop_psorb, tempval);
176
177 setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
178
179 tempval = PC_F2RXCLK|PC_F2TXCLK;
180
181 /* Alter clocks */
182 clrbits32(&io->iop_psorc,tempval);
183 clrbits32(&io->iop_pdirc,tempval);
184 setbits32(&io->iop_pparc,tempval);
185
186 clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
187 setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
188
189 iounmap(bcsr);
190 iounmap(immap);
191}
192
193
194static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
195 int idx)
196{
197 bd_t* bi = (void*)__res;
198 int fs_no = fsid_fcc1+pdev->id-1;
199
200 if(fs_no >= ARRAY_SIZE(mpc82xx_enet_pdata)) {
201 return;
202 }
203
204 mpc82xx_enet_pdata[fs_no].dpram_offset=
205 (u32)cpm2_immr->im_dprambase;
206 mpc82xx_enet_pdata[fs_no].fcc_regs_c =
207 (u32)cpm2_immr->im_fcc_c;
208 memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
209
210 /* prevent dup mac */
211 if(fs_no == fsid_fcc2)
212 mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
213
214 pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
215}
216
217static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
218 int idx)
219{
220 bd_t *bd = (bd_t *) __res;
221 struct fs_uart_platform_info *pinfo;
222 int num = ARRAY_SIZE(mpc8272_uart_pdata);
223 int id = fs_uart_id_scc2fsid(idx);
224
225 /* no need to alter anything if console */
226 if ((id < num) && (!pdev->dev.platform_data)) {
227 pinfo = &mpc8272_uart_pdata[id];
228 pinfo->uart_clk = bd->bi_intfreq;
229 pdev->dev.platform_data = pinfo;
230 }
231}
232
233static void init_scc1_uart_ioports(struct fs_uart_platform_info* pdata)
234{
235 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
236
237 /* SCC1 is only on port D */
238 setbits32(&immap->im_ioport.iop_ppard,0x00000003);
239 clrbits32(&immap->im_ioport.iop_psord,0x00000001);
240 setbits32(&immap->im_ioport.iop_psord,0x00000002);
241 clrbits32(&immap->im_ioport.iop_pdird,0x00000001);
242 setbits32(&immap->im_ioport.iop_pdird,0x00000002);
243
244 /* Wire BRG1 to SCC1 */
245 clrbits32(&immap->im_cpmux.cmx_scr,0x00ffffff);
246
247 iounmap(immap);
248}
249
250static void init_scc4_uart_ioports(struct fs_uart_platform_info* pdata)
251{
252 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
253
254 setbits32(&immap->im_ioport.iop_ppard,0x00000600);
255 clrbits32(&immap->im_ioport.iop_psord,0x00000600);
256 clrbits32(&immap->im_ioport.iop_pdird,0x00000200);
257 setbits32(&immap->im_ioport.iop_pdird,0x00000400);
258
259 /* Wire BRG4 to SCC4 */
260 clrbits32(&immap->im_cpmux.cmx_scr,0x000000ff);
261 setbits32(&immap->im_cpmux.cmx_scr,0x0000001b);
262
263 iounmap(immap);
264}
265
266static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
267 int idx)
268{
269 m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
270 m82xx_mii_bb_pdata.irq[1] = PHY_POLL;
271 m82xx_mii_bb_pdata.irq[2] = PHY_POLL;
272 m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
273 m82xx_mii_bb_pdata.irq[31] = PHY_POLL;
274
275
276 m82xx_mii_bb_pdata.mdio_dat.offset =
277 (u32)&cpm2_immr->im_ioport.iop_pdatc;
278
279 m82xx_mii_bb_pdata.mdio_dir.offset =
280 (u32)&cpm2_immr->im_ioport.iop_pdirc;
281
282 m82xx_mii_bb_pdata.mdc_dat.offset =
283 (u32)&cpm2_immr->im_ioport.iop_pdatc;
284
285
286 pdev->dev.platform_data = &m82xx_mii_bb_pdata;
287}
288
289static int mpc8272ads_platform_notify(struct device *dev)
290{
291 static const struct platform_notify_dev_map dev_map[] = {
292 {
293 .bus_id = "fsl-cpm-fcc",
294 .rtn = mpc8272ads_fixup_enet_pdata,
295 },
296 {
297 .bus_id = "fsl-cpm-scc:uart",
298 .rtn = mpc8272ads_fixup_uart_pdata,
299 },
300 {
301 .bus_id = "fsl-bb-mdio",
302 .rtn = mpc8272ads_fixup_mdio_pdata,
303 },
304 {
305 .bus_id = NULL
306 }
307 };
308 platform_notify_map(dev_map,dev);
309
310 return 0;
311
312}
313
314int __init mpc8272ads_init(void)
315{
316 printk(KERN_NOTICE "mpc8272ads: Init\n");
317
318 platform_notify = mpc8272ads_platform_notify;
319
320 ppc_sys_device_initfunc();
321
322 ppc_sys_device_disable_all();
323 ppc_sys_device_enable(MPC82xx_CPM_FCC1);
324 ppc_sys_device_enable(MPC82xx_CPM_FCC2);
325
326 /* to be ready for console, let's attach pdata here */
327#ifdef CONFIG_SERIAL_CPM_SCC1
328 ppc_sys_device_setfunc(MPC82xx_CPM_SCC1, PPC_SYS_FUNC_UART);
329 ppc_sys_device_enable(MPC82xx_CPM_SCC1);
330
331#endif
332
333#ifdef CONFIG_SERIAL_CPM_SCC4
334 ppc_sys_device_setfunc(MPC82xx_CPM_SCC4, PPC_SYS_FUNC_UART);
335 ppc_sys_device_enable(MPC82xx_CPM_SCC4);
336#endif
337
338 ppc_sys_device_enable(MPC82xx_MDIO_BB);
339
340 return 0;
341}
342
343/*
344 To prevent confusion, console selection is gross:
345 by 0 assumed SCC1 and by 1 assumed SCC4
346 */
347struct platform_device* early_uart_get_pdev(int index)
348{
349 bd_t *bd = (bd_t *) __res;
350 struct fs_uart_platform_info *pinfo;
351
352 struct platform_device* pdev = NULL;
353 if(index) { /*assume SCC4 here*/
354 pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC4];
355 pinfo = &mpc8272_uart_pdata[fsid_scc4_uart];
356 } else { /*over SCC1*/
357 pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC1];
358 pinfo = &mpc8272_uart_pdata[fsid_scc1_uart];
359 }
360
361 pinfo->uart_clk = bd->bi_intfreq;
362 pdev->dev.platform_data = pinfo;
363 ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR);
364 return NULL;
365}
366
367arch_initcall(mpc8272ads_init);
diff --git a/arch/ppc/platforms/mpc885ads.h b/arch/ppc/platforms/mpc885ads.h
deleted file mode 100644
index d3bbbb3c9a1f..000000000000
--- a/arch/ppc/platforms/mpc885ads.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Freescale MPC885ADS board.
4 * Copied from the FADS stuff.
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_MPC885ADS_H__
16#define __ASM_MPC885ADS_H__
17
18
19#include <asm/ppcboot.h>
20
21/* U-Boot maps BCSR to 0xff080000 */
22#define BCSR_ADDR ((uint)0xff080000)
23#define BCSR_SIZE ((uint)32)
24#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
25#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
26#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
27#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
28#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
29
30#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
31#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
32
33#define IMAP_ADDR ((uint)0xff000000)
34#define IMAP_SIZE ((uint)(64 * 1024))
35
36#define PCMCIA_MEM_ADDR ((uint)0xff020000)
37#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
38
39/* Bits of interest in the BCSRs.
40 */
41#define BCSR1_ETHEN ((uint)0x20000000)
42#define BCSR1_IRDAEN ((uint)0x10000000)
43#define BCSR1_RS232EN_1 ((uint)0x01000000)
44#define BCSR1_PCCEN ((uint)0x00800000)
45#define BCSR1_PCCVCC0 ((uint)0x00400000)
46#define BCSR1_PCCVPP0 ((uint)0x00200000)
47#define BCSR1_PCCVPP1 ((uint)0x00100000)
48#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
49#define BCSR1_RS232EN_2 ((uint)0x00040000)
50#define BCSR1_PCCVCC1 ((uint)0x00010000)
51#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
52
53#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
54#define BCSR4_USB_LO_SPD ((uint)0x04000000)
55#define BCSR4_USB_VCC ((uint)0x02000000)
56#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
57#define BCSR4_USB_EN ((uint)0x00020000)
58
59#define BCSR5_MII2_EN 0x40
60#define BCSR5_MII2_RST 0x20
61#define BCSR5_T1_RST 0x10
62#define BCSR5_ATM155_RST 0x08
63#define BCSR5_ATM25_RST 0x04
64#define BCSR5_MII1_EN 0x02
65#define BCSR5_MII1_RST 0x01
66
67/* Interrupt level assignments */
68#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
69#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
70#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
71#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
72
73/* We don't use the 8259 */
74#define NR_8259_INTS 0
75
76/* CPM Ethernet through SCC3 */
77#define PA_ENET_RXD ((ushort)0x0040)
78#define PA_ENET_TXD ((ushort)0x0080)
79#define PE_ENET_TCLK ((uint)0x00004000)
80#define PE_ENET_RCLK ((uint)0x00008000)
81#define PE_ENET_TENA ((uint)0x00000010)
82#define PC_ENET_CLSN ((ushort)0x0400)
83#define PC_ENET_RENA ((ushort)0x0800)
84
85/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
86 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
87#define SICR_ENET_MASK ((uint)0x00ff0000)
88#define SICR_ENET_CLKRT ((uint)0x002c0000)
89
90#define BOARD_CHIP_NAME "MPC885"
91
92#endif /* __ASM_MPC885ADS_H__ */
93#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
deleted file mode 100644
index ba06cc08cdab..000000000000
--- a/arch/ppc/platforms/mpc885ads_setup.c
+++ /dev/null
@@ -1,476 +0,0 @@
1/*arch/ppc/platforms/mpc885ads_setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/ioport.h>
19#include <linux/device.h>
20
21#include <linux/fs_enet_pd.h>
22#include <linux/fs_uart_pd.h>
23#include <linux/mii.h>
24
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/time.h>
32#include <asm/ppcboot.h>
33#include <asm/8xx_immap.h>
34#include <asm/cpm1.h>
35#include <asm/ppc_sys.h>
36
37extern unsigned char __res[];
38static void setup_smc1_ioports(struct fs_uart_platform_info*);
39static void setup_smc2_ioports(struct fs_uart_platform_info*);
40
41static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
42static void setup_fec1_ioports(struct fs_platform_info*);
43static void setup_fec2_ioports(struct fs_platform_info*);
44static void setup_scc3_ioports(struct fs_platform_info*);
45
46static struct fs_uart_platform_info mpc885_uart_pdata[] = {
47 [fsid_smc1_uart] = {
48 .brg = 1,
49 .fs_no = fsid_smc1_uart,
50 .init_ioports = setup_smc1_ioports,
51 .tx_num_fifo = 4,
52 .tx_buf_size = 32,
53 .rx_num_fifo = 4,
54 .rx_buf_size = 32,
55 },
56 [fsid_smc2_uart] = {
57 .brg = 2,
58 .fs_no = fsid_smc2_uart,
59 .init_ioports = setup_smc2_ioports,
60 .tx_num_fifo = 4,
61 .tx_buf_size = 32,
62 .rx_num_fifo = 4,
63 .rx_buf_size = 32,
64 },
65};
66
67static struct fs_platform_info mpc8xx_enet_pdata[] = {
68 [fsid_fec1] = {
69 .rx_ring = 128,
70 .tx_ring = 16,
71 .rx_copybreak = 240,
72
73 .use_napi = 1,
74 .napi_weight = 17,
75
76 .init_ioports = setup_fec1_ioports,
77
78 .bus_id = "0:00",
79 .has_phy = 1,
80 },
81 [fsid_fec2] = {
82 .rx_ring = 128,
83 .tx_ring = 16,
84 .rx_copybreak = 240,
85
86 .use_napi = 1,
87 .napi_weight = 17,
88
89 .init_ioports = setup_fec2_ioports,
90
91 .bus_id = "0:01",
92 .has_phy = 1,
93 },
94 [fsid_scc3] = {
95 .rx_ring = 64,
96 .tx_ring = 8,
97 .rx_copybreak = 240,
98
99 .use_napi = 1,
100 .napi_weight = 17,
101
102 .init_ioports = setup_scc3_ioports,
103#ifdef CONFIG_FIXED_MII_10_FDX
104 .bus_id = "fixed@100:1",
105#else
106 .bus_id = "0:02",
107 #endif
108 },
109};
110
111void __init board_init(void)
112{
113 cpm8xx_t *cp = cpmp;
114 unsigned int *bcsr_io;
115
116#ifdef CONFIG_FS_ENET
117 immap_t *immap = (immap_t *) IMAP_ADDR;
118#endif
119 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
120
121 if (bcsr_io == NULL) {
122 printk(KERN_CRIT "Could not remap BCSR\n");
123 return;
124 }
125#ifdef CONFIG_SERIAL_CPM_SMC1
126 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
127 clrbits32(bcsr_io, BCSR1_RS232EN_1);
128 cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
129 cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
130#else
131 setbits32(bcsr_io,BCSR1_RS232EN_1);
132 cp->cp_smc[0].smc_smcmr = 0;
133 cp->cp_smc[0].smc_smce = 0;
134#endif
135
136#ifdef CONFIG_SERIAL_CPM_SMC2
137 cp->cp_simode &= ~(0xe0000000 >> 1);
138 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
139 clrbits32(bcsr_io,BCSR1_RS232EN_2);
140 cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
141 cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
142#else
143 setbits32(bcsr_io,BCSR1_RS232EN_2);
144 cp->cp_smc[1].smc_smcmr = 0;
145 cp->cp_smc[1].smc_smce = 0;
146#endif
147 iounmap(bcsr_io);
148
149#ifdef CONFIG_FS_ENET
150 /* use MDC for MII (common) */
151 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
152 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
153 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
154 clrbits32(bcsr_io,BCSR5_MII1_EN);
155 clrbits32(bcsr_io,BCSR5_MII1_RST);
156#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
157 clrbits32(bcsr_io,BCSR5_MII2_EN);
158 clrbits32(bcsr_io,BCSR5_MII2_RST);
159#endif
160 iounmap(bcsr_io);
161#endif
162}
163
164static void setup_fec1_ioports(struct fs_platform_info* pdata)
165{
166 immap_t *immap = (immap_t *) IMAP_ADDR;
167
168 /* configure FEC1 pins */
169 setbits16(&immap->im_ioport.iop_papar, 0xf830);
170 setbits16(&immap->im_ioport.iop_padir, 0x0830);
171 clrbits16(&immap->im_ioport.iop_padir, 0xf000);
172 setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
173
174 clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
175 setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
176 clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
177 setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
178
179 setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
180 clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
181 clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
182}
183
184static void setup_fec2_ioports(struct fs_platform_info* pdata)
185{
186 immap_t *immap = (immap_t *) IMAP_ADDR;
187
188 /* configure FEC2 pins */
189 setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
190 setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
191 clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
192 setbits32(&immap->im_cpm.cp_peso, 0x00037800);
193 clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
194}
195
196static void setup_scc3_ioports(struct fs_platform_info* pdata)
197{
198 immap_t *immap = (immap_t *) IMAP_ADDR;
199 unsigned *bcsr_io;
200
201 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
202
203 if (bcsr_io == NULL) {
204 printk(KERN_CRIT "Could not remap BCSR\n");
205 return;
206 }
207
208 /* Enable the PHY.
209 */
210 clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
211 udelay(1000);
212 setbits32(bcsr_io+4, BCSR4_ETH10_RST);
213 /* Configure port A pins for Txd and Rxd.
214 */
215 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
216 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
217
218 /* Configure port C pins to enable CLSN and RENA.
219 */
220 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
221 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
222 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
223
224 /* Configure port E for TCLK and RCLK.
225 */
226 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
227 clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
228 clrbits32(&immap->im_cpm.cp_pedir,
229 PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
230 clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
231 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
232
233 /* Configure Serial Interface clock routing.
234 * First, clear all SCC bits to zero, then set the ones we want.
235 */
236 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
237 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
238
239 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
240 */
241 immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
242 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
243 * by H/W setting after reset. SCC ethernet controller support only half duplex.
244 * This discrepancy of modes causes a lot of carrier lost errors.
245 */
246
247 /* In the original SCC enet driver the following code is placed at
248 the end of the initialization */
249 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
250 clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
251 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
252
253 setbits32(bcsr_io+4, BCSR1_ETHEN);
254 iounmap(bcsr_io);
255}
256
257static int mac_count = 0;
258
259static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
260{
261 struct fs_platform_info *fpi;
262 bd_t *bd = (bd_t *) __res;
263 char *e;
264 int i;
265
266 if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
267 printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
268 return;
269 }
270
271 fpi = &mpc8xx_enet_pdata[fs_no];
272
273 switch (fs_no) {
274 case fsid_fec1:
275 fpi->init_ioports = &setup_fec1_ioports;
276 break;
277 case fsid_fec2:
278 fpi->init_ioports = &setup_fec2_ioports;
279 break;
280 case fsid_scc3:
281 fpi->init_ioports = &setup_scc3_ioports;
282 break;
283 default:
284 printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
285 return;
286 }
287
288 pdev->dev.platform_data = fpi;
289 fpi->fs_no = fs_no;
290
291 e = (unsigned char *)&bd->bi_enetaddr;
292 for (i = 0; i < 6; i++)
293 fpi->macaddr[i] = *e++;
294
295 fpi->macaddr[5] += mac_count++;
296
297}
298
299static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
300 int idx)
301{
302 /* This is for FEC devices only */
303 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
304 return;
305 mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
306}
307
308static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
309 int idx)
310{
311 /* This is for SCC devices only */
312 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
313 return;
314
315 mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
316}
317
318static void setup_smc1_ioports(struct fs_uart_platform_info* pdata)
319{
320 immap_t *immap = (immap_t *) IMAP_ADDR;
321 unsigned *bcsr_io;
322 unsigned int iobits = 0x000000c0;
323
324 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
325
326 if (bcsr_io == NULL) {
327 printk(KERN_CRIT "Could not remap BCSR1\n");
328 return;
329 }
330 clrbits32(bcsr_io,BCSR1_RS232EN_1);
331 iounmap(bcsr_io);
332
333 setbits32(&immap->im_cpm.cp_pbpar, iobits);
334 clrbits32(&immap->im_cpm.cp_pbdir, iobits);
335 clrbits16(&immap->im_cpm.cp_pbodr, iobits);
336}
337
338static void setup_smc2_ioports(struct fs_uart_platform_info* pdata)
339{
340 immap_t *immap = (immap_t *) IMAP_ADDR;
341 unsigned *bcsr_io;
342 unsigned int iobits = 0x00000c00;
343
344 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
345
346 if (bcsr_io == NULL) {
347 printk(KERN_CRIT "Could not remap BCSR1\n");
348 return;
349 }
350 clrbits32(bcsr_io,BCSR1_RS232EN_2);
351 iounmap(bcsr_io);
352
353#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
354 setbits32(&immap->im_cpm.cp_pbpar, iobits);
355 clrbits32(&immap->im_cpm.cp_pbdir, iobits);
356 clrbits16(&immap->im_cpm.cp_pbodr, iobits);
357#else
358 setbits16(&immap->im_ioport.iop_papar, iobits);
359 clrbits16(&immap->im_ioport.iop_padir, iobits);
360 clrbits16(&immap->im_ioport.iop_paodr, iobits);
361#endif
362}
363
364static void __init mpc885ads_fixup_uart_pdata(struct platform_device *pdev,
365 int idx)
366{
367 bd_t *bd = (bd_t *) __res;
368 struct fs_uart_platform_info *pinfo;
369 int num = ARRAY_SIZE(mpc885_uart_pdata);
370
371 int id = fs_uart_id_smc2fsid(idx);
372
373 /* no need to alter anything if console */
374 if ((id < num) && (!pdev->dev.platform_data)) {
375 pinfo = &mpc885_uart_pdata[id];
376 pinfo->uart_clk = bd->bi_intfreq;
377 pdev->dev.platform_data = pinfo;
378 }
379}
380
381
382static int mpc885ads_platform_notify(struct device *dev)
383{
384
385 static const struct platform_notify_dev_map dev_map[] = {
386 {
387 .bus_id = "fsl-cpm-fec",
388 .rtn = mpc885ads_fixup_fec_enet_pdata,
389 },
390 {
391 .bus_id = "fsl-cpm-scc",
392 .rtn = mpc885ads_fixup_scc_enet_pdata,
393 },
394 {
395 .bus_id = "fsl-cpm-smc:uart",
396 .rtn = mpc885ads_fixup_uart_pdata
397 },
398 {
399 .bus_id = NULL
400 }
401 };
402
403 platform_notify_map(dev_map,dev);
404
405 return 0;
406}
407
408int __init mpc885ads_init(void)
409{
410 struct fs_mii_fec_platform_info* fmpi;
411 bd_t *bd = (bd_t *) __res;
412
413 printk(KERN_NOTICE "mpc885ads: Init\n");
414
415 platform_notify = mpc885ads_platform_notify;
416
417 ppc_sys_device_initfunc();
418 ppc_sys_device_disable_all();
419
420 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
421
422 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
423 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
424 &mpc8xx_mdio_fec_pdata;
425
426 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
427
428 /* No PHY interrupt line here */
429 fmpi->irq[0xf] = SIU_IRQ7;
430
431#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
432 ppc_sys_device_enable(MPC8xx_CPM_SCC3);
433
434#endif
435#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
436 ppc_sys_device_enable(MPC8xx_CPM_FEC2);
437#endif
438
439#ifdef CONFIG_SERIAL_CPM_SMC1
440 ppc_sys_device_enable(MPC8xx_CPM_SMC1);
441 ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
442#endif
443
444#ifdef CONFIG_SERIAL_CPM_SMC2
445 ppc_sys_device_enable(MPC8xx_CPM_SMC2);
446 ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
447#endif
448 return 0;
449}
450
451arch_initcall(mpc885ads_init);
452
453/*
454 To prevent confusion, console selection is gross:
455 by 0 assumed SMC1 and by 1 assumed SMC2
456 */
457struct platform_device* early_uart_get_pdev(int index)
458{
459 bd_t *bd = (bd_t *) __res;
460 struct fs_uart_platform_info *pinfo;
461
462 struct platform_device* pdev = NULL;
463 if(index) { /*assume SMC2 here*/
464 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
465 pinfo = &mpc885_uart_pdata[1];
466 } else { /*over SMC1*/
467 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
468 pinfo = &mpc885_uart_pdata[0];
469 }
470
471 pinfo->uart_clk = bd->bi_intfreq;
472 pdev->dev.platform_data = pinfo;
473 ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
474 return NULL;
475}
476
diff --git a/arch/ppc/platforms/pq2ads.c b/arch/ppc/platforms/pq2ads.c
deleted file mode 100644
index 7fc2e02f5246..000000000000
--- a/arch/ppc/platforms/pq2ads.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * PQ2ADS platform support
3 *
4 * Author: Kumar Gala <galak@kernel.crashing.org>
5 * Derived from: est8260_setup.c by Allen Curtis
6 *
7 * Copyright 2004 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16
17#include <asm/io.h>
18#include <asm/mpc8260.h>
19#include <asm/cpm2.h>
20#include <asm/immap_cpm2.h>
21
22void __init
23m82xx_board_setup(void)
24{
25 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
26 u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
27
28 /* Enable the 2nd UART port */
29 clrbits32(bcsr, BCSR1_RS232_EN2);
30
31#ifdef CONFIG_SERIAL_CPM_SCC1
32 clrbits32((u32*)&immap->im_scc[0].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
33 clrbits32((u32*)&immap->im_scc[0].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
34#endif
35
36#ifdef CONFIG_SERIAL_CPM_SCC2
37 clrbits32((u32*)&immap->im_scc[1].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
38 clrbits32((u32*)&immap->im_scc[1].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
39#endif
40
41#ifdef CONFIG_SERIAL_CPM_SCC3
42 clrbits32((u32*)&immap->im_scc[2].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
43 clrbits32((u32*)&immap->im_scc[2].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
44#endif
45
46#ifdef CONFIG_SERIAL_CPM_SCC4
47 clrbits32((u32*)&immap->im_scc[3].scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
48 clrbits32((u32*)&immap->im_scc[3].scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
49#endif
50
51 iounmap(bcsr);
52 iounmap(immap);
53}
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
deleted file mode 100644
index 2b287f4e0ca3..000000000000
--- a/arch/ppc/platforms/pq2ads.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
4 * Copied from the RPX-Classic and SBS8260 stuff.
5 *
6 * Copyright (c) 2001 Dan Malek (dan@mvista.com)
7 */
8#ifdef __KERNEL__
9#ifndef __MACH_ADS8260_DEFS
10#define __MACH_ADS8260_DEFS
11
12
13#include <asm/ppcboot.h>
14
15#if defined(CONFIG_ADS8272)
16#define BOARD_CHIP_NAME "8272"
17#endif
18
19/* Memory map is configured by the PROM startup.
20 * We just map a few things we need. The CSR is actually 4 byte-wide
21 * registers that can be accessed as 8-, 16-, or 32-bit values.
22 */
23#define CPM_MAP_ADDR ((uint)0xf0000000)
24#define BCSR_ADDR ((uint)0xf4500000)
25#define BCSR_SIZE ((uint)(32 * 1024))
26
27#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
28
29/* For our show_cpuinfo hooks. */
30#define CPUINFO_VENDOR "Motorola"
31#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
32
33/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
34 * only on word boundaries.
35 * Not all are used (yet), or are interesting to us (yet).
36 */
37
38/* Things of interest in the CSR.
39*/
40#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
41#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
42#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
43#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
44#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
45#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
46#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable */
47#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
48
49#define PHY_INTERRUPT SIU_INT_IRQ7
50
51#ifdef CONFIG_PCI
52/* PCI interrupt controller */
53#define PCI_INT_STAT_REG 0xF8200000
54#define PCI_INT_MASK_REG 0xF8200004
55#define PIRQA (NR_CPM_INTS + 0)
56#define PIRQB (NR_CPM_INTS + 1)
57#define PIRQC (NR_CPM_INTS + 2)
58#define PIRQD (NR_CPM_INTS + 3)
59
60/*
61 * PCI memory map definitions for MPC8266ADS-PCI.
62 *
63 * processor view
64 * local address PCI address target
65 * 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
66 * 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
67 * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
68 *
69 * PCI master view
70 * local address PCI address target
71 * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
72 */
73
74/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
75 Here we should redefine what is unique for this board */
76#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
77#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
78#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
79
80#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
81#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
82
83#if defined(CONFIG_ADS8272)
84#define PCI_INT_TO_SIU SIU_INT_IRQ2
85#elif defined(CONFIG_PQ2FADS)
86#define PCI_INT_TO_SIU SIU_INT_IRQ6
87#else
88#warning PCI Bridge will be without interrupts support
89#endif
90
91#endif /* CONFIG_PCI */
92
93#endif /* __MACH_ADS8260_DEFS */
94#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
deleted file mode 100644
index 672483df8079..000000000000
--- a/arch/ppc/platforms/pq2ads_pd.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef __PQ2ADS_PD_H
2#define __PQ2ADS_PD_H
3/*
4 * arch/ppc/platforms/82xx/pq2ads_pd.h
5 *
6 * Some defines for MPC82xx board-specific PlatformDevice descriptions
7 *
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
17 Can only choose from CLK9-12 */
18
19#define F1_RXCLK 11
20#define F1_TXCLK 10
21
22/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
23 Can only choose from CLK13-16 */
24#define F2_RXCLK 15
25#define F2_TXCLK 16
26
27/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
28 Can only choose from CLK13-16 */
29#define F3_RXCLK 13
30#define F3_TXCLK 14
31
32#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 18:23:39 -0500