Merge branch 'topic/ppc-kvm' into next

Merge in some commits we're sharing with the KVM tree.

I manually propagated the change from commit d3d4ffaae439
("powerpc/powernv/ioda2: Reduce upper limit for DMA window size") into
pci-ioda-tce.c.

Conflicts:
        arch/powerpc/include/asm/cputable.h
        arch/powerpc/platforms/powernv/pci-ioda.c
        arch/powerpc/platforms/powernv/pci.h

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 3459015092fa..4758173df426 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -319,7 +319,7 @@ void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
                  * The FW told us to call it. This happens for some
                  * interrupt sources that need additional HW whacking
                  * beyond the ESB manipulation. For example LPC interrupts
-                 * on P9 DD1.0 need a latch to be clared in the LPC bridge
+                 * on P9 DD1.0 needed a latch to be clared in the LPC bridge
                  * itself. The Firmware will take care of it.
                  */
                 if (WARN_ON_ONCE(!xive_ops->eoi))
@@ -337,9 +337,9 @@ void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
                  * This allows us to then do a re-trigger if Q was set
                  * rather than synthesizing an interrupt in software
                  *
-                 * For LSIs, using the HW EOI cycle works around a problem
-                 * on P9 DD1 PHBs where the other ESB accesses don't work
-                 * properly.
+                 * For LSIs the HW EOI cycle is used rather than PQ bits,
+                 * as they are automatically re-triggred in HW when still
+                 * pending.
                  */
                 if (xd->flags & XIVE_IRQ_FLAG_LSI)
                         xive_esb_read(xd, XIVE_ESB_LOAD_EOI);