diff options
author | Michael Ellerman <mpe@ellerman.id.au> | 2018-07-19 00:37:57 -0400 |
---|---|---|
committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-07-19 00:37:57 -0400 |
commit | ce57c6610cc2d7cde61fc005a2d2090bce46fc73 (patch) | |
tree | be1230fb1773e3de7fb7f6a0adde68ca0468273e /arch/powerpc/mm/hash_utils_64.c | |
parent | 9c3250a127901c93b23723dc5859c71a0d068fb8 (diff) | |
parent | a68bd1267b7286b1687905651b404e765046de25 (diff) |
Merge branch 'topic/ppc-kvm' into next
Merge in some commits we're sharing with the KVM tree.
I manually propagated the change from commit d3d4ffaae439
("powerpc/powernv/ioda2: Reduce upper limit for DMA window size") into
pci-ioda-tce.c.
Conflicts:
arch/powerpc/include/asm/cputable.h
arch/powerpc/platforms/powernv/pci-ioda.c
arch/powerpc/platforms/powernv/pci.h
Diffstat (limited to 'arch/powerpc/mm/hash_utils_64.c')
-rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 8318716e5075..5a72e980e25a 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c | |||
@@ -808,31 +808,6 @@ int hash__remove_section_mapping(unsigned long start, unsigned long end) | |||
808 | } | 808 | } |
809 | #endif /* CONFIG_MEMORY_HOTPLUG */ | 809 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
810 | 810 | ||
811 | static void update_hid_for_hash(void) | ||
812 | { | ||
813 | unsigned long hid0; | ||
814 | unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */ | ||
815 | |||
816 | asm volatile("ptesync": : :"memory"); | ||
817 | /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */ | ||
818 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | ||
819 | : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory"); | ||
820 | asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory"); | ||
821 | trace_tlbie(0, 0, rb, 0, 2, 0, 0); | ||
822 | |||
823 | /* | ||
824 | * now switch the HID | ||
825 | */ | ||
826 | hid0 = mfspr(SPRN_HID0); | ||
827 | hid0 &= ~HID0_POWER9_RADIX; | ||
828 | mtspr(SPRN_HID0, hid0); | ||
829 | asm volatile("isync": : :"memory"); | ||
830 | |||
831 | /* Wait for it to happen */ | ||
832 | while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) | ||
833 | cpu_relax(); | ||
834 | } | ||
835 | |||
836 | static void __init hash_init_partition_table(phys_addr_t hash_table, | 811 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
837 | unsigned long htab_size) | 812 | unsigned long htab_size) |
838 | { | 813 | { |
@@ -845,8 +820,6 @@ static void __init hash_init_partition_table(phys_addr_t hash_table, | |||
845 | htab_size = __ilog2(htab_size) - 18; | 820 | htab_size = __ilog2(htab_size) - 18; |
846 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); | 821 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
847 | pr_info("Partition table %p\n", partition_tb); | 822 | pr_info("Partition table %p\n", partition_tb); |
848 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | ||
849 | update_hid_for_hash(); | ||
850 | } | 823 | } |
851 | 824 | ||
852 | static void __init htab_initialize(void) | 825 | static void __init htab_initialize(void) |
@@ -1077,9 +1050,6 @@ void hash__early_init_mmu_secondary(void) | |||
1077 | /* Initialize hash table for that CPU */ | 1050 | /* Initialize hash table for that CPU */ |
1078 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { | 1051 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
1079 | 1052 | ||
1080 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | ||
1081 | update_hid_for_hash(); | ||
1082 | |||
1083 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) | 1053 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1084 | mtspr(SPRN_SDR1, _SDR1); | 1054 | mtspr(SPRN_SDR1, _SDR1); |
1085 | else | 1055 | else |