diff options
| author | Diana CRACIUN <Diana.Craciun@freescale.com> | 2012-02-09 08:41:00 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-03-29 09:14:15 -0400 |
| commit | 8a57d734004b8018f3d320455c1816b1e6810265 (patch) | |
| tree | 2587de9c6f4e1ea3aa0b4564f81976df5c8c682a /arch/powerpc/boot/dts/p2041rdb.dts | |
| parent | 3b588c7efc84f15548afdda6a0d2f892fe83babc (diff) | |
powerpc/dts: Removed fsl,msi property from dts.
The association in the decice tree between PCI and MSI
using fsl,msi property was an artificial one and it does
not reflect the actual hardware.
Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p2041rdb.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/p2041rdb.dts | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts index 4f957db01230..285213976a7f 100644 --- a/arch/powerpc/boot/dts/p2041rdb.dts +++ b/arch/powerpc/boot/dts/p2041rdb.dts | |||
| @@ -135,7 +135,6 @@ | |||
| 135 | reg = <0xf 0xfe200000 0 0x1000>; | 135 | reg = <0xf 0xfe200000 0 0x1000>; |
| 136 | ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 | 136 | ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
| 137 | 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; | 137 | 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; |
| 138 | fsl,msi = <&msi0>; | ||
| 139 | pcie@0 { | 138 | pcie@0 { |
| 140 | ranges = <0x02000000 0 0xe0000000 | 139 | ranges = <0x02000000 0 0xe0000000 |
| 141 | 0x02000000 0 0xe0000000 | 140 | 0x02000000 0 0xe0000000 |
| @@ -151,7 +150,6 @@ | |||
| 151 | reg = <0xf 0xfe201000 0 0x1000>; | 150 | reg = <0xf 0xfe201000 0 0x1000>; |
| 152 | ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 | 151 | ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
| 153 | 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; | 152 | 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; |
| 154 | fsl,msi = <&msi1>; | ||
| 155 | pcie@0 { | 153 | pcie@0 { |
| 156 | ranges = <0x02000000 0 0xe0000000 | 154 | ranges = <0x02000000 0 0xe0000000 |
| 157 | 0x02000000 0 0xe0000000 | 155 | 0x02000000 0 0xe0000000 |
| @@ -167,7 +165,6 @@ | |||
| 167 | reg = <0xf 0xfe202000 0 0x1000>; | 165 | reg = <0xf 0xfe202000 0 0x1000>; |
| 168 | ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 | 166 | ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 |
| 169 | 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; | 167 | 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
| 170 | fsl,msi = <&msi2>; | ||
| 171 | pcie@0 { | 168 | pcie@0 { |
| 172 | ranges = <0x02000000 0 0xe0000000 | 169 | ranges = <0x02000000 0 0xe0000000 |
| 173 | 0x02000000 0 0xe0000000 | 170 | 0x02000000 0 0xe0000000 |