diff options
author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-04-18 10:16:57 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-04-21 03:31:22 -0400 |
commit | 5a4c0738998a037f4d29dc3f25215f4e2cc98919 (patch) | |
tree | ec9383d47abdc8eb4db166a839dd9f5fa2fb978c /arch/mips | |
parent | a9da1ac37ccfc29e8b29855604477a09c9b7b114 (diff) |
Revert "MIPS: Lantiq: Fix cascaded IRQ setup"
This reverts commit 362721c4957dcda7b1fbd45380e7a6617a1d077c which is
commit 6c356eda225e3ee134ed4176b9ae3a76f793f4dd upstream.
It shouldn't have been included in a stable release.
Reported-by: Amit Pundir <amit.pundir@linaro.org>
Cc: Felix Fietkau <nbd@nbd.name>
Cc: John Crispin <john@phrozen.org>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/lantiq/irq.c | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 0ddf3698b85d..8ac0e5994ed2 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c | |||
@@ -269,11 +269,6 @@ static void ltq_hw5_irqdispatch(void) | |||
269 | DEFINE_HWx_IRQDISPATCH(5) | 269 | DEFINE_HWx_IRQDISPATCH(5) |
270 | #endif | 270 | #endif |
271 | 271 | ||
272 | static void ltq_hw_irq_handler(struct irq_desc *desc) | ||
273 | { | ||
274 | ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); | ||
275 | } | ||
276 | |||
277 | #ifdef CONFIG_MIPS_MT_SMP | 272 | #ifdef CONFIG_MIPS_MT_SMP |
278 | void __init arch_init_ipiirq(int irq, struct irqaction *action) | 273 | void __init arch_init_ipiirq(int irq, struct irqaction *action) |
279 | { | 274 | { |
@@ -318,19 +313,23 @@ static struct irqaction irq_call = { | |||
318 | asmlinkage void plat_irq_dispatch(void) | 313 | asmlinkage void plat_irq_dispatch(void) |
319 | { | 314 | { |
320 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; | 315 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
321 | int irq; | 316 | unsigned int i; |
322 | 317 | ||
323 | if (!pending) { | 318 | if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { |
324 | spurious_interrupt(); | 319 | do_IRQ(MIPS_CPU_TIMER_IRQ); |
325 | return; | 320 | goto out; |
321 | } else { | ||
322 | for (i = 0; i < MAX_IM; i++) { | ||
323 | if (pending & (CAUSEF_IP2 << i)) { | ||
324 | ltq_hw_irqdispatch(i); | ||
325 | goto out; | ||
326 | } | ||
327 | } | ||
326 | } | 328 | } |
329 | pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); | ||
327 | 330 | ||
328 | pending >>= CAUSEB_IP; | 331 | out: |
329 | while (pending) { | 332 | return; |
330 | irq = fls(pending) - 1; | ||
331 | do_IRQ(MIPS_CPU_IRQ_BASE + irq); | ||
332 | pending &= ~BIT(irq); | ||
333 | } | ||
334 | } | 333 | } |
335 | 334 | ||
336 | static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) | 335 | static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
@@ -355,6 +354,11 @@ static const struct irq_domain_ops irq_domain_ops = { | |||
355 | .map = icu_map, | 354 | .map = icu_map, |
356 | }; | 355 | }; |
357 | 356 | ||
357 | static struct irqaction cascade = { | ||
358 | .handler = no_action, | ||
359 | .name = "cascade", | ||
360 | }; | ||
361 | |||
358 | int __init icu_of_init(struct device_node *node, struct device_node *parent) | 362 | int __init icu_of_init(struct device_node *node, struct device_node *parent) |
359 | { | 363 | { |
360 | struct device_node *eiu_node; | 364 | struct device_node *eiu_node; |
@@ -386,7 +390,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) | |||
386 | mips_cpu_irq_init(); | 390 | mips_cpu_irq_init(); |
387 | 391 | ||
388 | for (i = 0; i < MAX_IM; i++) | 392 | for (i = 0; i < MAX_IM; i++) |
389 | irq_set_chained_handler(i + 2, ltq_hw_irq_handler); | 393 | setup_irq(i + 2, &cascade); |
390 | 394 | ||
391 | if (cpu_has_vint) { | 395 | if (cpu_has_vint) { |
392 | pr_info("Setting up vectored interrupts\n"); | 396 | pr_info("Setting up vectored interrupts\n"); |