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authorChristoph Hellwig <hch@lst.de>2018-08-19 08:53:20 -0400
committerChristoph Hellwig <hch@lst.de>2018-09-20 03:01:15 -0400
commitf3ecc0ff0457eae93503792c6fc35921fa8a6204 (patch)
treecbaa1fbb29ea8d5b33fb8d1798e595147cb72729 /arch/mips/mm
parent5748e1b35ba28368515d850e8087929a3a65e055 (diff)
dma-mapping: move the dma_coherent flag to struct device
Various architectures support both coherent and non-coherent dma on a per-device basis. Move the dma_noncoherent flag from the mips archdata field to struct device proper to prepare the infrastructure for reuse on other architectures. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Paul Burton <paul.burton@mips.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/dma-noncoherent.c32
1 files changed, 6 insertions, 26 deletions
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 2aca1236af36..d408ac51f56c 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -14,26 +14,6 @@
14#include <asm/dma-coherence.h> 14#include <asm/dma-coherence.h>
15#include <asm/io.h> 15#include <asm/io.h>
16 16
17#ifdef CONFIG_DMA_PERDEV_COHERENT
18static inline int dev_is_coherent(struct device *dev)
19{
20 return dev->archdata.dma_coherent;
21}
22#else
23static inline int dev_is_coherent(struct device *dev)
24{
25 switch (coherentio) {
26 default:
27 case IO_COHERENCE_DEFAULT:
28 return hw_coherentio;
29 case IO_COHERENCE_ENABLED:
30 return 1;
31 case IO_COHERENCE_DISABLED:
32 return 0;
33 }
34}
35#endif /* CONFIG_DMA_PERDEV_COHERENT */
36
37/* 17/*
38 * The affected CPUs below in 'cpu_needs_post_dma_flush()' can speculatively 18 * The affected CPUs below in 'cpu_needs_post_dma_flush()' can speculatively
39 * fill random cachelines with stale data at any time, requiring an extra 19 * fill random cachelines with stale data at any time, requiring an extra
@@ -49,7 +29,7 @@ static inline int dev_is_coherent(struct device *dev)
49 */ 29 */
50static inline bool cpu_needs_post_dma_flush(struct device *dev) 30static inline bool cpu_needs_post_dma_flush(struct device *dev)
51{ 31{
52 if (dev_is_coherent(dev)) 32 if (dev_is_dma_coherent(dev))
53 return false; 33 return false;
54 34
55 switch (boot_cpu_type()) { 35 switch (boot_cpu_type()) {
@@ -76,7 +56,7 @@ void *arch_dma_alloc(struct device *dev, size_t size,
76 if (!ret) 56 if (!ret)
77 return NULL; 57 return NULL;
78 58
79 if (!dev_is_coherent(dev) && !(attrs & DMA_ATTR_NON_CONSISTENT)) { 59 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_NON_CONSISTENT)) {
80 dma_cache_wback_inv((unsigned long) ret, size); 60 dma_cache_wback_inv((unsigned long) ret, size);
81 ret = (void *)UNCAC_ADDR(ret); 61 ret = (void *)UNCAC_ADDR(ret);
82 } 62 }
@@ -87,7 +67,7 @@ void *arch_dma_alloc(struct device *dev, size_t size,
87void arch_dma_free(struct device *dev, size_t size, void *cpu_addr, 67void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
88 dma_addr_t dma_addr, unsigned long attrs) 68 dma_addr_t dma_addr, unsigned long attrs)
89{ 69{
90 if (!(attrs & DMA_ATTR_NON_CONSISTENT) && !dev_is_coherent(dev)) 70 if (!(attrs & DMA_ATTR_NON_CONSISTENT) && !dev_is_dma_coherent(dev))
91 cpu_addr = (void *)CAC_ADDR((unsigned long)cpu_addr); 71 cpu_addr = (void *)CAC_ADDR((unsigned long)cpu_addr);
92 dma_direct_free(dev, size, cpu_addr, dma_addr, attrs); 72 dma_direct_free(dev, size, cpu_addr, dma_addr, attrs);
93} 73}
@@ -103,7 +83,7 @@ int arch_dma_mmap(struct device *dev, struct vm_area_struct *vma,
103 unsigned long pfn; 83 unsigned long pfn;
104 int ret = -ENXIO; 84 int ret = -ENXIO;
105 85
106 if (!dev_is_coherent(dev)) 86 if (!dev_is_dma_coherent(dev))
107 addr = CAC_ADDR(addr); 87 addr = CAC_ADDR(addr);
108 88
109 pfn = page_to_pfn(virt_to_page((void *)addr)); 89 pfn = page_to_pfn(virt_to_page((void *)addr));
@@ -187,7 +167,7 @@ static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
187void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, 167void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
188 size_t size, enum dma_data_direction dir) 168 size_t size, enum dma_data_direction dir)
189{ 169{
190 if (!dev_is_coherent(dev)) 170 if (!dev_is_dma_coherent(dev))
191 dma_sync_phys(paddr, size, dir); 171 dma_sync_phys(paddr, size, dir);
192} 172}
193 173
@@ -203,6 +183,6 @@ void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
203{ 183{
204 BUG_ON(direction == DMA_NONE); 184 BUG_ON(direction == DMA_NONE);
205 185
206 if (!dev_is_coherent(dev)) 186 if (!dev_is_dma_coherent(dev))
207 dma_sync_virt(vaddr, size, direction); 187 dma_sync_virt(vaddr, size, direction);
208} 188}