diff options
author | James Hogan <james.hogan@imgtec.com> | 2016-06-14 04:40:10 -0400 |
---|---|---|
committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-06-14 05:02:48 -0400 |
commit | f943176a7205a064da05f81fc94dccc4c7379010 (patch) | |
tree | 4dcb7e1af560631bbb2cc63664098819fd5a4437 /arch/mips/kvm | |
parent | 35fec26242bd3ff5a770789185852d27b44ffaec (diff) |
MIPS: KVM: Generalise fpu_inuse for other state
Rename fpu_inuse and the related definitions to aux_inuse so it can be
used for lazy context management of other auxiliary processor state too,
such as VZ guest timer, watchpoints and performance counters.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/mips/kvm')
-rw-r--r-- | arch/mips/kvm/emulate.c | 8 | ||||
-rw-r--r-- | arch/mips/kvm/mips.c | 38 |
2 files changed, 23 insertions, 23 deletions
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 5b89c0803405..8647bd97b934 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c | |||
@@ -1154,7 +1154,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, | |||
1154 | * it first. | 1154 | * it first. |
1155 | */ | 1155 | */ |
1156 | if (change & ST0_CU1 && !(val & ST0_FR) && | 1156 | if (change & ST0_CU1 && !(val & ST0_FR) && |
1157 | vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) | 1157 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
1158 | kvm_lose_fpu(vcpu); | 1158 | kvm_lose_fpu(vcpu); |
1159 | 1159 | ||
1160 | /* | 1160 | /* |
@@ -1165,7 +1165,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, | |||
1165 | * the near future. | 1165 | * the near future. |
1166 | */ | 1166 | */ |
1167 | if (change & ST0_CU1 && | 1167 | if (change & ST0_CU1 && |
1168 | vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) | 1168 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
1169 | change_c0_status(ST0_CU1, val); | 1169 | change_c0_status(ST0_CU1, val); |
1170 | 1170 | ||
1171 | preempt_enable(); | 1171 | preempt_enable(); |
@@ -1200,7 +1200,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, | |||
1200 | * context is already loaded. | 1200 | * context is already loaded. |
1201 | */ | 1201 | */ |
1202 | if (change & MIPS_CONF5_FRE && | 1202 | if (change & MIPS_CONF5_FRE && |
1203 | vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) | 1203 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
1204 | change_c0_config5(MIPS_CONF5_FRE, val); | 1204 | change_c0_config5(MIPS_CONF5_FRE, val); |
1205 | 1205 | ||
1206 | /* | 1206 | /* |
@@ -1210,7 +1210,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, | |||
1210 | * quickly enabled again in the near future. | 1210 | * quickly enabled again in the near future. |
1211 | */ | 1211 | */ |
1212 | if (change & MIPS_CONF5_MSAEN && | 1212 | if (change & MIPS_CONF5_MSAEN && |
1213 | vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) | 1213 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
1214 | change_c0_config5(MIPS_CONF5_MSAEN, | 1214 | change_c0_config5(MIPS_CONF5_MSAEN, |
1215 | val); | 1215 | val); |
1216 | 1216 | ||
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c index 6e753761b5d6..9093262ff3ce 100644 --- a/arch/mips/kvm/mips.c +++ b/arch/mips/kvm/mips.c | |||
@@ -1447,7 +1447,7 @@ void kvm_own_fpu(struct kvm_vcpu *vcpu) | |||
1447 | * not to clobber the status register directly via the commpage. | 1447 | * not to clobber the status register directly via the commpage. |
1448 | */ | 1448 | */ |
1449 | if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && | 1449 | if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && |
1450 | vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) | 1450 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
1451 | kvm_lose_fpu(vcpu); | 1451 | kvm_lose_fpu(vcpu); |
1452 | 1452 | ||
1453 | /* | 1453 | /* |
@@ -1462,9 +1462,9 @@ void kvm_own_fpu(struct kvm_vcpu *vcpu) | |||
1462 | enable_fpu_hazard(); | 1462 | enable_fpu_hazard(); |
1463 | 1463 | ||
1464 | /* If guest FPU state not active, restore it now */ | 1464 | /* If guest FPU state not active, restore it now */ |
1465 | if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) { | 1465 | if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { |
1466 | __kvm_restore_fpu(&vcpu->arch); | 1466 | __kvm_restore_fpu(&vcpu->arch); |
1467 | vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; | 1467 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
1468 | } | 1468 | } |
1469 | 1469 | ||
1470 | preempt_enable(); | 1470 | preempt_enable(); |
@@ -1491,8 +1491,8 @@ void kvm_own_msa(struct kvm_vcpu *vcpu) | |||
1491 | * interacts with MSA state, so play it safe and save it first. | 1491 | * interacts with MSA state, so play it safe and save it first. |
1492 | */ | 1492 | */ |
1493 | if (!(sr & ST0_FR) && | 1493 | if (!(sr & ST0_FR) && |
1494 | (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | | 1494 | (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | |
1495 | KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU) | 1495 | KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) |
1496 | kvm_lose_fpu(vcpu); | 1496 | kvm_lose_fpu(vcpu); |
1497 | 1497 | ||
1498 | change_c0_status(ST0_CU1 | ST0_FR, sr); | 1498 | change_c0_status(ST0_CU1 | ST0_FR, sr); |
@@ -1506,20 +1506,20 @@ void kvm_own_msa(struct kvm_vcpu *vcpu) | |||
1506 | set_c0_config5(MIPS_CONF5_MSAEN); | 1506 | set_c0_config5(MIPS_CONF5_MSAEN); |
1507 | enable_fpu_hazard(); | 1507 | enable_fpu_hazard(); |
1508 | 1508 | ||
1509 | switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) { | 1509 | switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { |
1510 | case KVM_MIPS_FPU_FPU: | 1510 | case KVM_MIPS_AUX_FPU: |
1511 | /* | 1511 | /* |
1512 | * Guest FPU state already loaded, only restore upper MSA state | 1512 | * Guest FPU state already loaded, only restore upper MSA state |
1513 | */ | 1513 | */ |
1514 | __kvm_restore_msa_upper(&vcpu->arch); | 1514 | __kvm_restore_msa_upper(&vcpu->arch); |
1515 | vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; | 1515 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
1516 | break; | 1516 | break; |
1517 | case 0: | 1517 | case 0: |
1518 | /* Neither FPU or MSA already active, restore full MSA state */ | 1518 | /* Neither FPU or MSA already active, restore full MSA state */ |
1519 | __kvm_restore_msa(&vcpu->arch); | 1519 | __kvm_restore_msa(&vcpu->arch); |
1520 | vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; | 1520 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
1521 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) | 1521 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) |
1522 | vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; | 1522 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
1523 | break; | 1523 | break; |
1524 | default: | 1524 | default: |
1525 | break; | 1525 | break; |
@@ -1533,13 +1533,13 @@ void kvm_own_msa(struct kvm_vcpu *vcpu) | |||
1533 | void kvm_drop_fpu(struct kvm_vcpu *vcpu) | 1533 | void kvm_drop_fpu(struct kvm_vcpu *vcpu) |
1534 | { | 1534 | { |
1535 | preempt_disable(); | 1535 | preempt_disable(); |
1536 | if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { | 1536 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
1537 | disable_msa(); | 1537 | disable_msa(); |
1538 | vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA; | 1538 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; |
1539 | } | 1539 | } |
1540 | if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { | 1540 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
1541 | clear_c0_status(ST0_CU1 | ST0_FR); | 1541 | clear_c0_status(ST0_CU1 | ST0_FR); |
1542 | vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; | 1542 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
1543 | } | 1543 | } |
1544 | preempt_enable(); | 1544 | preempt_enable(); |
1545 | } | 1545 | } |
@@ -1555,7 +1555,7 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu) | |||
1555 | */ | 1555 | */ |
1556 | 1556 | ||
1557 | preempt_disable(); | 1557 | preempt_disable(); |
1558 | if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { | 1558 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
1559 | set_c0_config5(MIPS_CONF5_MSAEN); | 1559 | set_c0_config5(MIPS_CONF5_MSAEN); |
1560 | enable_fpu_hazard(); | 1560 | enable_fpu_hazard(); |
1561 | 1561 | ||
@@ -1563,17 +1563,17 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu) | |||
1563 | 1563 | ||
1564 | /* Disable MSA & FPU */ | 1564 | /* Disable MSA & FPU */ |
1565 | disable_msa(); | 1565 | disable_msa(); |
1566 | if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { | 1566 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
1567 | clear_c0_status(ST0_CU1 | ST0_FR); | 1567 | clear_c0_status(ST0_CU1 | ST0_FR); |
1568 | disable_fpu_hazard(); | 1568 | disable_fpu_hazard(); |
1569 | } | 1569 | } |
1570 | vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA); | 1570 | vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); |
1571 | } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { | 1571 | } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
1572 | set_c0_status(ST0_CU1); | 1572 | set_c0_status(ST0_CU1); |
1573 | enable_fpu_hazard(); | 1573 | enable_fpu_hazard(); |
1574 | 1574 | ||
1575 | __kvm_save_fpu(&vcpu->arch); | 1575 | __kvm_save_fpu(&vcpu->arch); |
1576 | vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; | 1576 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
1577 | 1577 | ||
1578 | /* Disable FPU */ | 1578 | /* Disable FPU */ |
1579 | clear_c0_status(ST0_CU1 | ST0_FR); | 1579 | clear_c0_status(ST0_CU1 | ST0_FR); |