Merge tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Pull MIPS updates from James Hogan:
 "These are the main MIPS changes for 4.17. Rough overview:

   (1) generic platform: Add support for Microsemi Ocelot SoCs

   (2) crypto: Add CRC32 and CRC32C HW acceleration module

   (3) Various cleanups and misc improvements

  More detailed summary:

  Miscellaneous:
   - hang more efficiently on halt/powerdown/restart
   - pm-cps: Block system suspend when a JTAG probe is present
   - expand make help text for generic defconfigs
   - refactor handling of legacy defconfigs
   - determine the entry point from the ELF file header to fix microMIPS
     for certain toolchains
   - introduce isa-rev.h for MIPS_ISA_REV and use to simplify other code

  Minor cleanups:
   - DTS: boston/ci20: Unit name cleanups and correction
   - kdump: Make the default for PHYSICAL_START always 64-bit
   - constify gpio_led in Alchemy, AR7, and TXX9
   - silence a couple of W=1 warnings
   - remove duplicate includes

  Platform support:
  Generic platform:
   - add support for Microsemi Ocelot
   - dt-bindings: Add vendor prefix for Microsemi Corporation
   - dt-bindings: Add bindings for Microsemi SoCs
   - add ocelot SoC & PCB123 board DTS files
   - MAINTAINERS: Add entry for Microsemi MIPS SoCs
   - enable crc32-mips on r6 configs

  ath79:
   - fix AR724X_PLL_REG_PCIE_CONFIG offset

  BCM47xx:
   - firmware: Use mac_pton() for MAC address parsing
   - add Luxul XAP1500/XWR1750 WiFi LEDs
   - use standard reset button for Luxul XWR-1750

  BMIPS:
   - enable CONFIG_BRCMSTB_PM in bmips_stb_defconfig for build coverage
   - add STB PM, wake-up timer, watchdog DT nodes

  Octeon:
   - drop '.' after newlines in printk calls

  ralink:
   - pci-mt7621: Enable PCIe on MT7688"

* tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (37 commits)
  MIPS: BCM47XX: Use standard reset button for Luxul XWR-1750
  MIPS: BCM47XX: Add Luxul XAP1500/XWR1750 WiFi LEDs
  MIPS: Make the default for PHYSICAL_START always 64-bit
  MIPS: Use the entry point from the ELF file header
  MAINTAINERS: Add entry for Microsemi MIPS SoCs
  MIPS: generic: Add support for Microsemi Ocelot
  MIPS: mscc: Add ocelot PCB123 device tree
  MIPS: mscc: Add ocelot dtsi
  dt-bindings: mips: Add bindings for Microsemi SoCs
  dt-bindings: Add vendor prefix for Microsemi Corporation
  MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset
  MIPS: pci-mt7620: Enable PCIe on MT7688
  MIPS: pm-cps: Block system suspend when a JTAG probe is present
  MIPS: VDSO: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: BPF: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV
  MIPS: Introduce isa-rev.h to define MIPS_ISA_REV
  MIPS: Hang more efficiently on halt/powerdown/restart
  FIRMWARE: bcm47xx_nvram: Replace mac address parsing
  MIPS: BMIPS: Add Broadcom STB watchdog nodes
  ...

4 files changed, 99 insertions, 8 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cf3fd549e16d..6b07b739f914 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -848,6 +848,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
         if (config5 & MIPS_CONF5_CA2)
                 c->ases |= MIPS_ASE_MIPS16E2;
 
+        if (config5 & MIPS_CONF5_CRCP)
+                elf_hwcap |= HWCAP_MIPS_CRC32;
+
         return config5 & MIPS_CONF_M;
 }
 
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 421e06dfee72..55c3fbeb2df6 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
+#include <linux/suspend.h>
 
 #include <asm/asm-offsets.h>
 #include <asm/cacheflush.h>
@@ -670,6 +671,34 @@ static int cps_pm_online_cpu(unsigned int cpu)
         return 0;
 }
 
+static int cps_pm_power_notifier(struct notifier_block *this,
+                                 unsigned long event, void *ptr)
+{
+        unsigned int stat;
+
+        switch (event) {
+        case PM_SUSPEND_PREPARE:
+                stat = read_cpc_cl_stat_conf();
+                /*
+                 * If we're attempting to suspend the system and power down all
+                 * of the cores, the JTAG detect bit indicates that the CPC will
+                 * instead put the cores into clock-off state. In this state
+                 * a connected debugger can cause the CPU to attempt
+                 * interactions with the powered down system. At best this will
+                 * fail. At worst, it can hang the NoC, requiring a hard reset.
+                 * To avoid this, just block system suspend if a JTAG probe
+                 * is detected.
+                 */
+                if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
+                        pr_warn("JTAG probe is connected - abort suspend\n");
+                        return NOTIFY_BAD;
+                }
+                return NOTIFY_DONE;
+        default:
+                return NOTIFY_DONE;
+        }
+}
+
 static int __init cps_pm_init(void)
 {
         /* A CM is required for all non-coherent states */
@@ -705,6 +734,8 @@ static int __init cps_pm_init(void)
                 pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
         }
 
+        pm_notifier(cps_pm_power_notifier, 0);
+
         return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
                                  cps_pm_online_cpu, NULL);
 }
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 7c746d3458e7..6288780b779e 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -13,6 +13,9 @@
 #include <linux/reboot.h>
 #include <linux/delay.h>
 
+#include <asm/compiler.h>
+#include <asm/idle.h>
+#include <asm/mipsregs.h>
 #include <asm/reboot.h>
 
 /*
@@ -26,6 +29,62 @@ void (*pm_power_off)(void);
 
 EXPORT_SYMBOL(pm_power_off);
 
+static void machine_hang(void)
+{
+        /*
+         * We're hanging the system so we don't want to be interrupted anymore.
+         * Any interrupt handlers that ran would at best be useless & at worst
+         * go awry because the system isn't in a functional state.
+         */
+        local_irq_disable();
+
+        /*
+         * Mask all interrupts, giving us a better chance of remaining in the
+         * low power wait state.
+         */
+        clear_c0_status(ST0_IM);
+
+        while (true) {
+                if (cpu_has_mips_r) {
+                        /*
+                         * We know that the wait instruction is supported so
+                         * make use of it directly, leaving interrupts
+                         * disabled.
+                         */
+                        asm volatile(
+                                ".set   push\n\t"
+                                ".set   " MIPS_ISA_ARCH_LEVEL "\n\t"
+                                "wait\n\t"
+                                ".set   pop");
+                } else if (cpu_wait) {
+                        /*
+                         * Try the cpu_wait() callback. This isn't ideal since
+                         * it'll re-enable interrupts, but that ought to be
+                         * harmless given that they're all masked.
+                         */
+                        cpu_wait();
+                        local_irq_disable();
+                } else {
+                        /*
+                         * We're going to burn some power running round the
+                         * loop, but we don't really have a choice. This isn't
+                         * a path we should expect to run for long during
+                         * typical use anyway.
+                         */
+                }
+
+                /*
+                 * In most modern MIPS CPUs interrupts will cause the wait
+                 * instruction to graduate even when disabled, and in some
+                 * cases even when masked. In order to prevent a timer
+                 * interrupt from continuously taking us out of the low power
+                 * wait state, we clear any pending timer interrupt here.
+                 */
+                if (cpu_has_counter)
+                        write_c0_compare(0);
+        }
+}
+
 void machine_restart(char *command)
 {
         if (_machine_restart)
@@ -38,8 +97,7 @@ void machine_restart(char *command)
         do_kernel_restart(command);
         mdelay(1000);
         pr_emerg("Reboot failed -- System halted\n");
-        local_irq_disable();
-        while (1);
+        machine_hang();
 }
 
 void machine_halt(void)
@@ -51,8 +109,7 @@ void machine_halt(void)
         preempt_disable();
         smp_send_stop();
 #endif
-        local_irq_disable();
-        while (1);
+        machine_hang();
 }
 
 void machine_power_off(void)
@@ -64,6 +121,5 @@ void machine_power_off(void)
         preempt_disable();
         smp_send_stop();
 #endif
-        local_irq_disable();
-        while (1);
+        machine_hang();
 }
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 5f8b0a9e30b3..563188ac6fa2 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -155,7 +155,8 @@ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_add
         add_memory_region(start, size, BOOT_MEM_RAM);
 }
 
-bool __init memory_region_available(phys_addr_t start, phys_addr_t size)
+static bool __init __maybe_unused memory_region_available(phys_addr_t start,
+                                                          phys_addr_t size)
 {
         int i;
         bool in_ram = false, free = true;
@@ -453,7 +454,7 @@ static void __init bootmem_init(void)
                 pr_info("Wasting %lu bytes for tracking %lu unused pages\n",
                         (min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page),
                         min_low_pfn - ARCH_PFN_OFFSET);
-        } else if (min_low_pfn < ARCH_PFN_OFFSET) {
+        } else if (ARCH_PFN_OFFSET - min_low_pfn > 0UL) {
                 pr_info("%lu free pages won't be used\n",
                         ARCH_PFN_OFFSET - min_low_pfn);
         }