Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the MIPS pull request for the next kernel:

   - Zubair's patch series adds CMA support for MIPS.  Doing so it also
     touches ARM64 and x86.
   - remove the last instance of IRQF_DISABLED from arch/mips
   - updates to two of the MIPS defconfig files.
   - cleanup of how cache coherency bits are handled on MIPS and
     implement support for write-combining.
   - platform upgrades for Alchemy
   - move MIPS DTS files to arch/mips/boot/dts/"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (24 commits)
  MIPS: ralink: remove deprecated IRQF_DISABLED
  MIPS: pgtable.h: Implement the pgprot_writecombine function for MIPS
  MIPS: cpu-probe: Set the write-combine CCA value on per core basis
  MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
  MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks
  MIPS: DMA: Add cma support
  x86: use generic dma-contiguous.h
  arm64: use generic dma-contiguous.h
  asm-generic: Add dma-contiguous.h
  MIPS: BPF: Add new emit_long_instr macro
  MIPS: ralink: Move device-trees to arch/mips/boot/dts/
  MIPS: Netlogic: Move device-trees to arch/mips/boot/dts/
  MIPS: sead3: Move device-trees to arch/mips/boot/dts/
  MIPS: Lantiq: Move device-trees to arch/mips/boot/dts/
  MIPS: Octeon: Move device-trees to arch/mips/boot/dts/
  MIPS: Add support for building device-tree binaries
  MIPS: Create common infrastructure for building built-in device-trees
  MIPS: SEAD3: Enable DEVTMPFS
  MIPS: SEAD3: Regenerate defconfigs
  MIPS: Alchemy: DB1300: Add touch penirq support
  ...

2 files changed, 30 insertions, 0 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e34b10be782e..94c4a0c0a577 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -27,6 +27,7 @@
 #include <asm/msa.h>
 #include <asm/watch.h>
 #include <asm/elf.h>
+#include <asm/pgtable-bits.h>
 #include <asm/spram.h>
 #include <asm/uaccess.h>
 
@@ -764,6 +765,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         break;
                 case PRID_REV_LOONGSON3A:
                         c->cputype = CPU_LOONGSON3;
+                        c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                         __cpu_name[cpu] = "ICT Loongson-3";
                         set_elf_platform(cpu, "loongson3a");
                         break;
@@ -798,67 +800,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
+        c->writecombine = _CACHE_UNCACHED_ACCELERATED;
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_4KC:
                 c->cputype = CPU_4KC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 4Kc";
                 break;
         case PRID_IMP_4KEC:
         case PRID_IMP_4KECR2:
                 c->cputype = CPU_4KEC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 4KEc";
                 break;
         case PRID_IMP_4KSC:
         case PRID_IMP_4KSD:
                 c->cputype = CPU_4KSC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 4KSc";
                 break;
         case PRID_IMP_5KC:
                 c->cputype = CPU_5KC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 5Kc";
                 break;
         case PRID_IMP_5KE:
                 c->cputype = CPU_5KE;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 5KE";
                 break;
         case PRID_IMP_20KC:
                 c->cputype = CPU_20KC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 20Kc";
                 break;
         case PRID_IMP_24K:
                 c->cputype = CPU_24K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 24Kc";
                 break;
         case PRID_IMP_24KE:
                 c->cputype = CPU_24K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 24KEc";
                 break;
         case PRID_IMP_25KF:
                 c->cputype = CPU_25KF;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 25Kc";
                 break;
         case PRID_IMP_34K:
                 c->cputype = CPU_34K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 34Kc";
                 break;
         case PRID_IMP_74K:
                 c->cputype = CPU_74K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 74Kc";
                 break;
         case PRID_IMP_M14KC:
                 c->cputype = CPU_M14KC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS M14Kc";
                 break;
         case PRID_IMP_M14KEC:
                 c->cputype = CPU_M14KEC;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS M14KEc";
                 break;
         case PRID_IMP_1004K:
                 c->cputype = CPU_1004K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 1004Kc";
                 break;
         case PRID_IMP_1074K:
                 c->cputype = CPU_1074K;
+                c->writecombine = _CACHE_UNCACHED;
                 __cpu_name[cpu] = "MIPS 1074Kc";
                 break;
         case PRID_IMP_INTERAPTIV_UP:
@@ -932,6 +950,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
 
+        c->writecombine = _CACHE_UNCACHED_ACCELERATED;
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_SB1:
                 c->cputype = CPU_SB1;
@@ -1063,6 +1082,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_JZRISC:
                 c->cputype = CPU_JZRISC;
+                c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                 __cpu_name[cpu] = "Ingenic JZRISC";
                 break;
         default:
@@ -1169,6 +1189,7 @@ void cpu_probe(void)
         c->processor_id = PRID_IMP_UNKNOWN;
         c->fpu_id       = FPIR_IMP_NONE;
         c->cputype      = CPU_UNKNOWN;
+        c->writecombine = _CACHE_UNCACHED;
 
         c->processor_id = read_c0_prid();
         switch (c->processor_id & PRID_COMP_MASK) {
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 7c1fe2b42d40..b3b8f0d9d4a7 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -24,6 +24,8 @@
 #include <linux/debugfs.h>
 #include <linux/kexec.h>
 #include <linux/sizes.h>
+#include <linux/device.h>
+#include <linux/dma-contiguous.h>
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
@@ -476,6 +478,7 @@ static void __init bootmem_init(void)
  *  o bootmem_init()
  *  o sparse_init()
  *  o paging_init()
+ *  o dma_continguous_reserve()
  *
  * At this stage the bootmem allocator is ready to use.
  *
@@ -609,6 +612,7 @@ static void __init request_crashkernel(struct resource *res)
 
 static void __init arch_mem_init(char **cmdline_p)
 {
+        struct memblock_region *reg;
         extern void plat_mem_setup(void);
 
         /* call board setup routine */
@@ -675,6 +679,11 @@ static void __init arch_mem_init(char **cmdline_p)
         sparse_init();
         plat_swiotlb_setup();
         paging_init();
+
+        dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
+        /* Tell bootmem about cma reserved memblock section */
+        for_each_memblock(reserved, reg)
+                reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
 }
 
 static void __init resource_init(void)