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authorMaciej W. Rozycki <macro@imgtec.com>2016-10-31 12:27:01 -0400
committerRalf Baechle <ralf@linux-mips.org>2016-11-03 20:38:52 -0400
commit758ef0a939d4c003381d2a97d9fb51b2d6d7e162 (patch)
tree99a480803264184a3215421820a07863ae6803ac /arch/mips/kernel
parent6daaa3266db9cc488612690e42c23b0763e2b49a (diff)
MIPS: Fix ISA I/II FP signal context offsets
Fix a regression introduced with commit 2db9ca0a3551 ("MIPS: Use struct mips_abi offsets to save FP context") for MIPS I/I FP signal contexts, by converting save/restore code to the updated internal API. Start FGR offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status Register (FCSR). Document the new internal API and adjust assembly code formatting for consistency. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14476/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/r2300_fpu.S159
-rw-r--r--arch/mips/kernel/r6000_fpu.S89
2 files changed, 131 insertions, 117 deletions
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index ce249eae91ce..70ca63752cfa 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -26,97 +26,104 @@
26 26
27 .set noreorder 27 .set noreorder
28 .set mips1 28 .set mips1
29 /* Save floating point context */ 29
30/**
31 * _save_fp_context() - save FP context from the FPU
32 * @a0 - pointer to fpregs field of sigcontext
33 * @a1 - pointer to fpc_csr field of sigcontext
34 *
35 * Save FP context, including the 32 FP data registers and the FP
36 * control & status register, from the FPU to signal context.
37 */
30LEAF(_save_fp_context) 38LEAF(_save_fp_context)
31 .set push 39 .set push
32 SET_HARDFLOAT 40 SET_HARDFLOAT
33 li v0, 0 # assume success 41 li v0, 0 # assume success
34 cfc1 t1,fcr31 42 cfc1 t1, fcr31
35 EX(swc1 $f0,(SC_FPREGS+0)(a0)) 43 EX(swc1 $f0, 0(a0))
36 EX(swc1 $f1,(SC_FPREGS+8)(a0)) 44 EX(swc1 $f1, 8(a0))
37 EX(swc1 $f2,(SC_FPREGS+16)(a0)) 45 EX(swc1 $f2, 16(a0))
38 EX(swc1 $f3,(SC_FPREGS+24)(a0)) 46 EX(swc1 $f3, 24(a0))
39 EX(swc1 $f4,(SC_FPREGS+32)(a0)) 47 EX(swc1 $f4, 32(a0))
40 EX(swc1 $f5,(SC_FPREGS+40)(a0)) 48 EX(swc1 $f5, 40(a0))
41 EX(swc1 $f6,(SC_FPREGS+48)(a0)) 49 EX(swc1 $f6, 48(a0))
42 EX(swc1 $f7,(SC_FPREGS+56)(a0)) 50 EX(swc1 $f7, 56(a0))
43 EX(swc1 $f8,(SC_FPREGS+64)(a0)) 51 EX(swc1 $f8, 64(a0))
44 EX(swc1 $f9,(SC_FPREGS+72)(a0)) 52 EX(swc1 $f9, 72(a0))
45 EX(swc1 $f10,(SC_FPREGS+80)(a0)) 53 EX(swc1 $f10, 80(a0))
46 EX(swc1 $f11,(SC_FPREGS+88)(a0)) 54 EX(swc1 $f11, 88(a0))
47 EX(swc1 $f12,(SC_FPREGS+96)(a0)) 55 EX(swc1 $f12, 96(a0))
48 EX(swc1 $f13,(SC_FPREGS+104)(a0)) 56 EX(swc1 $f13, 104(a0))
49 EX(swc1 $f14,(SC_FPREGS+112)(a0)) 57 EX(swc1 $f14, 112(a0))
50 EX(swc1 $f15,(SC_FPREGS+120)(a0)) 58 EX(swc1 $f15, 120(a0))
51 EX(swc1 $f16,(SC_FPREGS+128)(a0)) 59 EX(swc1 $f16, 128(a0))
52 EX(swc1 $f17,(SC_FPREGS+136)(a0)) 60 EX(swc1 $f17, 136(a0))
53 EX(swc1 $f18,(SC_FPREGS+144)(a0)) 61 EX(swc1 $f18, 144(a0))
54 EX(swc1 $f19,(SC_FPREGS+152)(a0)) 62 EX(swc1 $f19, 152(a0))
55 EX(swc1 $f20,(SC_FPREGS+160)(a0)) 63 EX(swc1 $f20, 160(a0))
56 EX(swc1 $f21,(SC_FPREGS+168)(a0)) 64 EX(swc1 $f21, 168(a0))
57 EX(swc1 $f22,(SC_FPREGS+176)(a0)) 65 EX(swc1 $f22, 176(a0))
58 EX(swc1 $f23,(SC_FPREGS+184)(a0)) 66 EX(swc1 $f23, 184(a0))
59 EX(swc1 $f24,(SC_FPREGS+192)(a0)) 67 EX(swc1 $f24, 192(a0))
60 EX(swc1 $f25,(SC_FPREGS+200)(a0)) 68 EX(swc1 $f25, 200(a0))
61 EX(swc1 $f26,(SC_FPREGS+208)(a0)) 69 EX(swc1 $f26, 208(a0))
62 EX(swc1 $f27,(SC_FPREGS+216)(a0)) 70 EX(swc1 $f27, 216(a0))
63 EX(swc1 $f28,(SC_FPREGS+224)(a0)) 71 EX(swc1 $f28, 224(a0))
64 EX(swc1 $f29,(SC_FPREGS+232)(a0)) 72 EX(swc1 $f29, 232(a0))
65 EX(swc1 $f30,(SC_FPREGS+240)(a0)) 73 EX(swc1 $f30, 240(a0))
66 EX(swc1 $f31,(SC_FPREGS+248)(a0)) 74 EX(swc1 $f31, 248(a0))
67 jr ra 75 jr ra
68 EX(sw t1,(SC_FPC_CSR)(a0)) 76 EX(sw t1, (a1))
69 .set pop 77 .set pop
70 END(_save_fp_context) 78 END(_save_fp_context)
71 79
72/* 80/**
73 * Restore FPU state: 81 * _restore_fp_context() - restore FP context to the FPU
74 * - fp gp registers 82 * @a0 - pointer to fpregs field of sigcontext
75 * - cp1 status/control register 83 * @a1 - pointer to fpc_csr field of sigcontext
76 * 84 *
77 * We base the decision which registers to restore from the signal stack 85 * Restore FP context, including the 32 FP data registers and the FP
78 * frame on the current content of c0_status, not on the content of the 86 * control & status register, from signal context to the FPU.
79 * stack frame which might have been changed by the user.
80 */ 87 */
81LEAF(_restore_fp_context) 88LEAF(_restore_fp_context)
82 .set push 89 .set push
83 SET_HARDFLOAT 90 SET_HARDFLOAT
84 li v0, 0 # assume success 91 li v0, 0 # assume success
85 EX(lw t0,(SC_FPC_CSR)(a0)) 92 EX(lw t0, (a1))
86 EX(lwc1 $f0,(SC_FPREGS+0)(a0)) 93 EX(lwc1 $f0, 0(a0))
87 EX(lwc1 $f1,(SC_FPREGS+8)(a0)) 94 EX(lwc1 $f1, 8(a0))
88 EX(lwc1 $f2,(SC_FPREGS+16)(a0)) 95 EX(lwc1 $f2, 16(a0))
89 EX(lwc1 $f3,(SC_FPREGS+24)(a0)) 96 EX(lwc1 $f3, 24(a0))
90 EX(lwc1 $f4,(SC_FPREGS+32)(a0)) 97 EX(lwc1 $f4, 32(a0))
91 EX(lwc1 $f5,(SC_FPREGS+40)(a0)) 98 EX(lwc1 $f5, 40(a0))
92 EX(lwc1 $f6,(SC_FPREGS+48)(a0)) 99 EX(lwc1 $f6, 48(a0))
93 EX(lwc1 $f7,(SC_FPREGS+56)(a0)) 100 EX(lwc1 $f7, 56(a0))
94 EX(lwc1 $f8,(SC_FPREGS+64)(a0)) 101 EX(lwc1 $f8, 64(a0))
95 EX(lwc1 $f9,(SC_FPREGS+72)(a0)) 102 EX(lwc1 $f9, 72(a0))
96 EX(lwc1 $f10,(SC_FPREGS+80)(a0)) 103 EX(lwc1 $f10, 80(a0))
97 EX(lwc1 $f11,(SC_FPREGS+88)(a0)) 104 EX(lwc1 $f11, 88(a0))
98 EX(lwc1 $f12,(SC_FPREGS+96)(a0)) 105 EX(lwc1 $f12, 96(a0))
99 EX(lwc1 $f13,(SC_FPREGS+104)(a0)) 106 EX(lwc1 $f13, 104(a0))
100 EX(lwc1 $f14,(SC_FPREGS+112)(a0)) 107 EX(lwc1 $f14, 112(a0))
101 EX(lwc1 $f15,(SC_FPREGS+120)(a0)) 108 EX(lwc1 $f15, 120(a0))
102 EX(lwc1 $f16,(SC_FPREGS+128)(a0)) 109 EX(lwc1 $f16, 128(a0))
103 EX(lwc1 $f17,(SC_FPREGS+136)(a0)) 110 EX(lwc1 $f17, 136(a0))
104 EX(lwc1 $f18,(SC_FPREGS+144)(a0)) 111 EX(lwc1 $f18, 144(a0))
105 EX(lwc1 $f19,(SC_FPREGS+152)(a0)) 112 EX(lwc1 $f19, 152(a0))
106 EX(lwc1 $f20,(SC_FPREGS+160)(a0)) 113 EX(lwc1 $f20, 160(a0))
107 EX(lwc1 $f21,(SC_FPREGS+168)(a0)) 114 EX(lwc1 $f21, 168(a0))
108 EX(lwc1 $f22,(SC_FPREGS+176)(a0)) 115 EX(lwc1 $f22, 176(a0))
109 EX(lwc1 $f23,(SC_FPREGS+184)(a0)) 116 EX(lwc1 $f23, 184(a0))
110 EX(lwc1 $f24,(SC_FPREGS+192)(a0)) 117 EX(lwc1 $f24, 192(a0))
111 EX(lwc1 $f25,(SC_FPREGS+200)(a0)) 118 EX(lwc1 $f25, 200(a0))
112 EX(lwc1 $f26,(SC_FPREGS+208)(a0)) 119 EX(lwc1 $f26, 208(a0))
113 EX(lwc1 $f27,(SC_FPREGS+216)(a0)) 120 EX(lwc1 $f27, 216(a0))
114 EX(lwc1 $f28,(SC_FPREGS+224)(a0)) 121 EX(lwc1 $f28, 224(a0))
115 EX(lwc1 $f29,(SC_FPREGS+232)(a0)) 122 EX(lwc1 $f29, 232(a0))
116 EX(lwc1 $f30,(SC_FPREGS+240)(a0)) 123 EX(lwc1 $f30, 240(a0))
117 EX(lwc1 $f31,(SC_FPREGS+248)(a0)) 124 EX(lwc1 $f31, 248(a0))
118 jr ra 125 jr ra
119 ctc1 t0,fcr31 126 ctc1 t0, fcr31
120 .set pop 127 .set pop
121 END(_restore_fp_context) 128 END(_restore_fp_context)
122 .set reorder 129 .set reorder
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index 47077380c15c..9cc7bfab3419 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -21,7 +21,14 @@
21 .set push 21 .set push
22 SET_HARDFLOAT 22 SET_HARDFLOAT
23 23
24 /* Save floating point context */ 24/**
25 * _save_fp_context() - save FP context from the FPU
26 * @a0 - pointer to fpregs field of sigcontext
27 * @a1 - pointer to fpc_csr field of sigcontext
28 *
29 * Save FP context, including the 32 FP data registers and the FP
30 * control & status register, from the FPU to signal context.
31 */
25 LEAF(_save_fp_context) 32 LEAF(_save_fp_context)
26 mfc0 t0,CP0_STATUS 33 mfc0 t0,CP0_STATUS
27 sll t0,t0,2 34 sll t0,t0,2
@@ -30,59 +37,59 @@
30 37
31 cfc1 t1,fcr31 38 cfc1 t1,fcr31
32 /* Store the 16 double precision registers */ 39 /* Store the 16 double precision registers */
33 sdc1 $f0,(SC_FPREGS+0)(a0) 40 sdc1 $f0,0(a0)
34 sdc1 $f2,(SC_FPREGS+16)(a0) 41 sdc1 $f2,16(a0)
35 sdc1 $f4,(SC_FPREGS+32)(a0) 42 sdc1 $f4,32(a0)
36 sdc1 $f6,(SC_FPREGS+48)(a0) 43 sdc1 $f6,48(a0)
37 sdc1 $f8,(SC_FPREGS+64)(a0) 44 sdc1 $f8,64(a0)
38 sdc1 $f10,(SC_FPREGS+80)(a0) 45 sdc1 $f10,80(a0)
39 sdc1 $f12,(SC_FPREGS+96)(a0) 46 sdc1 $f12,96(a0)
40 sdc1 $f14,(SC_FPREGS+112)(a0) 47 sdc1 $f14,112(a0)
41 sdc1 $f16,(SC_FPREGS+128)(a0) 48 sdc1 $f16,128(a0)
42 sdc1 $f18,(SC_FPREGS+144)(a0) 49 sdc1 $f18,144(a0)
43 sdc1 $f20,(SC_FPREGS+160)(a0) 50 sdc1 $f20,160(a0)
44 sdc1 $f22,(SC_FPREGS+176)(a0) 51 sdc1 $f22,176(a0)
45 sdc1 $f24,(SC_FPREGS+192)(a0) 52 sdc1 $f24,192(a0)
46 sdc1 $f26,(SC_FPREGS+208)(a0) 53 sdc1 $f26,208(a0)
47 sdc1 $f28,(SC_FPREGS+224)(a0) 54 sdc1 $f28,224(a0)
48 sdc1 $f30,(SC_FPREGS+240)(a0) 55 sdc1 $f30,240(a0)
49 jr ra 56 jr ra
50 sw t0,SC_FPC_CSR(a0) 57 sw t0,(a1)
511: jr ra 581: jr ra
52 nop 59 nop
53 END(_save_fp_context) 60 END(_save_fp_context)
54 61
55/* Restore FPU state: 62/**
56 * - fp gp registers 63 * _restore_fp_context() - restore FP context to the FPU
57 * - cp1 status/control register 64 * @a0 - pointer to fpregs field of sigcontext
65 * @a1 - pointer to fpc_csr field of sigcontext
58 * 66 *
59 * We base the decision which registers to restore from the signal stack 67 * Restore FP context, including the 32 FP data registers and the FP
60 * frame on the current content of c0_status, not on the content of the 68 * control & status register, from signal context to the FPU.
61 * stack frame which might have been changed by the user.
62 */ 69 */
63 LEAF(_restore_fp_context) 70 LEAF(_restore_fp_context)
64 mfc0 t0,CP0_STATUS 71 mfc0 t0,CP0_STATUS
65 sll t0,t0,2 72 sll t0,t0,2
66 73
67 bgez t0,1f 74 bgez t0,1f
68 lw t0,SC_FPC_CSR(a0) 75 lw t0,(a1)
69 /* Restore the 16 double precision registers */ 76 /* Restore the 16 double precision registers */
70 ldc1 $f0,(SC_FPREGS+0)(a0) 77 ldc1 $f0,0(a0)
71 ldc1 $f2,(SC_FPREGS+16)(a0) 78 ldc1 $f2,16(a0)
72 ldc1 $f4,(SC_FPREGS+32)(a0) 79 ldc1 $f4,32(a0)
73 ldc1 $f6,(SC_FPREGS+48)(a0) 80 ldc1 $f6,48(a0)
74 ldc1 $f8,(SC_FPREGS+64)(a0) 81 ldc1 $f8,64(a0)
75 ldc1 $f10,(SC_FPREGS+80)(a0) 82 ldc1 $f10,80(a0)
76 ldc1 $f12,(SC_FPREGS+96)(a0) 83 ldc1 $f12,96(a0)
77 ldc1 $f14,(SC_FPREGS+112)(a0) 84 ldc1 $f14,112(a0)
78 ldc1 $f16,(SC_FPREGS+128)(a0) 85 ldc1 $f16,128(a0)
79 ldc1 $f18,(SC_FPREGS+144)(a0) 86 ldc1 $f18,144(a0)
80 ldc1 $f20,(SC_FPREGS+160)(a0) 87 ldc1 $f20,160(a0)
81 ldc1 $f22,(SC_FPREGS+176)(a0) 88 ldc1 $f22,176(a0)
82 ldc1 $f24,(SC_FPREGS+192)(a0) 89 ldc1 $f24,192(a0)
83 ldc1 $f26,(SC_FPREGS+208)(a0) 90 ldc1 $f26,208(a0)
84 ldc1 $f28,(SC_FPREGS+224)(a0) 91 ldc1 $f28,224(a0)
85 ldc1 $f30,(SC_FPREGS+240)(a0) 92 ldc1 $f30,240(a0)
86 jr ra 93 jr ra
87 ctc1 t0,fcr31 94 ctc1 t0,fcr31
881: jr ra 951: jr ra
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 20:20:13 -0400