diff options
| author | Matt Redfearn <matt.redfearn@imgtec.com> | 2016-09-07 05:45:18 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-10-04 10:13:57 -0400 |
| commit | 77451997237fa7e8ba4f5e2f0fcd99898f78ff9b (patch) | |
| tree | d4419fd748abf7e2a66cdc4c9c74730ef536440e /arch/mips/kernel/pm-cps.c | |
| parent | 929d4f51e6b87900c9179eb62d6b43db6ce4930d (diff) | |
MIPS: pm-cps: Support CM3 changes to Coherence Enable Register
MIPS CM3 changed the management of coherence. Instead of a coherence
control register with a bitmask of coherent domains, CM3 simply has a
coherence enable register with a single bit to enable coherence of the
local core. Support this by clearing and setting this single bit to
disable / enable coherence.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Tony Wu <tung7970@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nikolay Martynov <mar.kolya@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14226/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/pm-cps.c')
| -rw-r--r-- | arch/mips/kernel/pm-cps.c | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 440e79259566..05bcdedcf9bd 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c | |||
| @@ -480,18 +480,20 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) | |||
| 480 | uasm_i_sync(&p, STYPE_SYNC); | 480 | uasm_i_sync(&p, STYPE_SYNC); |
| 481 | uasm_i_ehb(&p); | 481 | uasm_i_ehb(&p); |
| 482 | 482 | ||
| 483 | /* | 483 | if (mips_cm_revision() < CM_REV_CM3) { |
| 484 | * Disable all but self interventions. The load from COHCTL is defined | 484 | /* |
| 485 | * by the interAptiv & proAptiv SUMs as ensuring that the operation | 485 | * Disable all but self interventions. The load from COHCTL is |
| 486 | * resulting from the preceding store is complete. | 486 | * defined by the interAptiv & proAptiv SUMs as ensuring that the |
| 487 | */ | 487 | * operation resulting from the preceding store is complete. |
| 488 | uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core); | 488 | */ |
| 489 | uasm_i_sw(&p, t0, 0, r_pcohctl); | 489 | uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core); |
| 490 | uasm_i_lw(&p, t0, 0, r_pcohctl); | 490 | uasm_i_sw(&p, t0, 0, r_pcohctl); |
| 491 | 491 | uasm_i_lw(&p, t0, 0, r_pcohctl); | |
| 492 | /* Barrier to ensure write to coherence control is complete */ | 492 | |
| 493 | uasm_i_sync(&p, STYPE_SYNC); | 493 | /* Barrier to ensure write to coherence control is complete */ |
| 494 | uasm_i_ehb(&p); | 494 | uasm_i_sync(&p, STYPE_SYNC); |
| 495 | uasm_i_ehb(&p); | ||
| 496 | } | ||
| 495 | 497 | ||
| 496 | /* Disable coherence */ | 498 | /* Disable coherence */ |
| 497 | uasm_i_sw(&p, zero, 0, r_pcohctl); | 499 | uasm_i_sw(&p, zero, 0, r_pcohctl); |
| @@ -566,7 +568,10 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) | |||
| 566 | * will run this. The first will actually re-enable coherence & the | 568 | * will run this. The first will actually re-enable coherence & the |
| 567 | * rest will just be performing a rather unusual nop. | 569 | * rest will just be performing a rather unusual nop. |
| 568 | */ | 570 | */ |
| 569 | uasm_i_addiu(&p, t0, zero, CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK); | 571 | uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3 |
| 572 | ? CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK | ||
| 573 | : CM3_GCR_Cx_COHERENCE_COHEN_MSK); | ||
| 574 | |||
| 570 | uasm_i_sw(&p, t0, 0, r_pcohctl); | 575 | uasm_i_sw(&p, t0, 0, r_pcohctl); |
| 571 | uasm_i_lw(&p, t0, 0, r_pcohctl); | 576 | uasm_i_lw(&p, t0, 0, r_pcohctl); |
| 572 | 577 | ||